mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-i2c
This commit is contained in:
Tom Rini
commit
76a8265b4f
14 changed files with 476 additions and 319 deletions
6
README
6
README
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@ -2125,6 +2125,12 @@ CBFS (Coreboot Filesystem) support
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|||
- set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
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- set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
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- drivers/i2c/s3c24x0_i2c.c:
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- activate this driver with CONFIG_SYS_I2C_S3C24X0
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- This driver adds i2c buses (11 for Exynos5250, Exynos5420
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9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
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with a fix speed from 100000 and the slave addr 0!
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -150,8 +150,6 @@ int power_init_board(void)
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set_ps_hold_ctrl();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (pmic_init(I2C_PMIC))
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return -1;
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@ -57,15 +57,18 @@ int board_init(void)
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void i2c_init_board(void)
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{
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struct exynos4_gpio_part1 *gpio1 =
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(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
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int err;
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struct exynos4_gpio_part2 *gpio2 =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
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/* I2C_5 -> PMIC -> Adapter 0 */
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s5p_gpio_direction_output(&gpio1->b, 7, 1);
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s5p_gpio_direction_output(&gpio1->b, 6, 1);
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/* I2C_9 -> FG -> Adapter 1 */
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/* I2C_5 -> PMIC */
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err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
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if (err) {
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debug("I2C%d not configured\n", (I2C_5));
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return;
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}
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/* I2C_8 -> FG */
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s5p_gpio_direction_output(&gpio2->y4, 0, 1);
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s5p_gpio_direction_output(&gpio2->y4, 1, 1);
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}
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@ -290,10 +293,10 @@ int power_init_board(void)
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* The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
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* to logical I2C adapter 1
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*/
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ret = pmic_init(I2C_0);
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ret = pmic_init(I2C_5);
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ret |= pmic_init_max8997();
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ret |= power_fg_init(I2C_1);
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ret |= power_muic_init(I2C_0);
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ret |= power_fg_init(I2C_8);
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ret |= power_muic_init(I2C_5);
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ret |= power_bat_init(0);
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if (ret)
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return ret;
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@ -115,12 +115,17 @@ static void board_external_gpio_init(void)
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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static void board_init_i2c(void)
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{
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int err;
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gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
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gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
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/* I2C_7 */
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s5p_gpio_direction_output(&gpio1->d0, 2, 1);
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s5p_gpio_direction_output(&gpio1->d0, 3, 1);
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err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
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if (err) {
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debug("I2C%d not configured\n", (I2C_7));
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return;
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}
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/* I2C_8 */
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s5p_gpio_direction_output(&gpio1->f1, 4, 1);
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@ -132,6 +137,24 @@ static void board_init_i2c(void)
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}
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#endif
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#ifdef CONFIG_SYS_I2C_SOFT
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int get_soft_i2c_scl_pin(void)
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{
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if (I2C_ADAP_HWNR)
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return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
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else
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return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
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}
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int get_soft_i2c_sda_pin(void)
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{
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if (I2C_ADAP_HWNR)
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return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
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else
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return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
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}
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#endif
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int board_early_init_f(void)
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{
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check_hw_revision();
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@ -167,11 +190,11 @@ int power_init_board(void)
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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board_init_i2c();
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#endif
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pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */
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pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
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pmic_init_max77686();
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pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
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power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */
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power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */
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pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */
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power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */
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power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */
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power_bat_init(0);
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p_chrg = pmic_get("MAX77693_PMIC");
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@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
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#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
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spi_read (addr, alen, buffer, len);
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#else
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if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0)
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if (i2c_read(addr[0], offset, alen - 1, buffer, len))
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rcode = 1;
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#endif
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buffer += len;
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@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
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/* Write is enabled ... now write eeprom value.
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*/
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#endif
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if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0)
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if (i2c_write(addr[0], offset, alen - 1, buffer, len))
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rcode = 1;
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#endif
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@ -12,7 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
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obj-$(CONFIG_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
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obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
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obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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@ -24,6 +23,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
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obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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@ -13,67 +13,78 @@
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#include "fti2c010.h"
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#ifndef CONFIG_HARD_I2C
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#error "fti2c010: CONFIG_HARD_I2C is not defined"
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#endif
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#ifndef CONFIG_SYS_I2C_SPEED
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SPEED 5000
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#endif
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#ifndef CONFIG_FTI2C010_FREQ
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#define CONFIG_FTI2C010_FREQ clk_get_rate("I2C")
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#ifndef CONFIG_SYS_I2C_SLAVE
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#define CONFIG_SYS_I2C_SLAVE 0
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#endif
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/* command timeout */
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#define CFG_CMD_TIMEOUT 10 /* ms */
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#ifndef CONFIG_FTI2C010_CLOCK
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#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
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#endif
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/* 7-bit chip address + 1-bit read/write */
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#define I2C_RD(chip) ((((chip) << 1) & 0xff) | 1)
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#define I2C_WR(chip) (((chip) << 1) & 0xff)
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#ifndef CONFIG_FTI2C010_TIMEOUT
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#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
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#endif
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/* 7-bit dev address + 1-bit read/write */
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#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
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#define I2C_WR(dev) (((dev) << 1) & 0xfe)
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struct fti2c010_chip {
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void __iomem *regs;
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uint bus;
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uint speed;
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struct fti2c010_regs *regs;
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};
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static struct fti2c010_chip chip_list[] = {
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{
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.bus = 0,
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.regs = (void __iomem *)CONFIG_FTI2C010_BASE,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
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},
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#ifdef CONFIG_I2C_MULTI_BUS
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# ifdef CONFIG_FTI2C010_BASE1
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#ifdef CONFIG_FTI2C010_BASE1
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{
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.bus = 1,
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.regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
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},
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# endif
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# ifdef CONFIG_FTI2C010_BASE2
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#endif
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#ifdef CONFIG_FTI2C010_BASE2
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{
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.bus = 2,
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.regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
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},
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# endif
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# ifdef CONFIG_FTI2C010_BASE3
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#endif
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#ifdef CONFIG_FTI2C010_BASE3
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{
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.bus = 3,
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.regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
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},
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# endif
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#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
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#endif
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};
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static struct fti2c010_chip *curr = chip_list;
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static int fti2c010_reset(struct fti2c010_chip *chip)
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{
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ulong ts;
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int ret = -1;
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struct fti2c010_regs *regs = chip->regs;
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static int fti2c010_wait(uint32_t mask)
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writel(CR_I2CRST, ®s->cr);
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for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
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if (!(readl(®s->cr) & CR_I2CRST)) {
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ret = 0;
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break;
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}
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}
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if (ret)
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printf("fti2c010: reset timeout\n");
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return ret;
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}
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static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
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{
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int ret = -1;
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uint32_t stat, ts;
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struct fti2c010_regs *regs = curr->regs;
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struct fti2c010_regs *regs = chip->regs;
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for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
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for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
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stat = readl(®s->sr);
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if ((stat & mask) == mask) {
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ret = 0;
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@ -84,88 +95,124 @@ static int fti2c010_wait(uint32_t mask)
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return ret;
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}
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/*
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* u-boot I2C API
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*/
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static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
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unsigned int speed)
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{
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struct fti2c010_regs *regs = chip->regs;
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unsigned int clk = CONFIG_FTI2C010_CLOCK;
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unsigned int gsr = 0;
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unsigned int tsr = 32;
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unsigned int div, rate;
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for (div = 0; div < 0x3ffff; ++div) {
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/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
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rate = clk / (2 * (div + 2) + gsr);
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if (rate <= speed)
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break;
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}
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writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
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writel(CDR_DIV(div), ®s->cdr);
|
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return rate;
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}
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|
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/*
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* Initialization, must be called once on start up, may be called
|
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* repeatedly to change the speed and slave addresses.
|
||||
*/
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void i2c_init(int speed, int slaveaddr)
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static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
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{
|
||||
if (speed || !curr->speed)
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i2c_set_bus_speed(speed);
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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|
||||
/* if slave mode disabled */
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||||
if (!slaveaddr)
|
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if (adap->init_done)
|
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return;
|
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|
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/*
|
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* TODO:
|
||||
* Implement slave mode, but is it really necessary?
|
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*/
|
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
|
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/* Call board specific i2c bus reset routine before accessing the
|
||||
* environment, which might be in a chip on that bus. For details
|
||||
* about this problem see doc/I2C_Edge_Conditions.
|
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*/
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i2c_init_board();
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#endif
|
||||
|
||||
/* master init */
|
||||
|
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fti2c010_reset(chip);
|
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|
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set_i2c_bus_speed(chip, speed);
|
||||
|
||||
/* slave init, don't care */
|
||||
|
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#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
|
||||
/* Call board specific i2c bus reset routine AFTER the bus has been
|
||||
* initialized. Use either this callpoint or i2c_init_board;
|
||||
* which is called before fti2c010_init operations.
|
||||
* For details about this problem see doc/I2C_Edge_Conditions.
|
||||
*/
|
||||
i2c_board_late_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Probe the given I2C chip address. Returns 0 if a chip responded,
|
||||
* not 0 on failure.
|
||||
*/
|
||||
int i2c_probe(uchar chip)
|
||||
static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
|
||||
{
|
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
|
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struct fti2c010_regs *regs = chip->regs;
|
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int ret;
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struct fti2c010_regs *regs = curr->regs;
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|
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i2c_init(0, 0);
|
||||
|
||||
/* 1. Select slave device (7bits Address + 1bit R/W) */
|
||||
writel(I2C_WR(chip), ®s->dr);
|
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writel(I2C_WR(dev), ®s->dr);
|
||||
writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
|
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ret = fti2c010_wait(SR_DT);
|
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ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
return ret;
|
||||
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/* 2. Select device register */
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||||
writel(0, ®s->dr);
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||||
writel(CR_ENABLE | CR_TBEN, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
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||||
ret = fti2c010_wait(chip, SR_DT);
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||||
|
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return ret;
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||||
}
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||||
|
||||
/*
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||||
* Read/Write interface:
|
||||
* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
|
||||
* memories, 0 for register type devices with only one
|
||||
* register)
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* buffer: Where to read/write the data
|
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* len: How many bytes to read/write
|
||||
*
|
||||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
|
||||
{
|
||||
int i, shift;
|
||||
|
||||
if (!buf || alen <= 0)
|
||||
return;
|
||||
|
||||
/* MSB first */
|
||||
i = 0;
|
||||
shift = (alen - 1) * 8;
|
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while (alen-- > 0) {
|
||||
buf[i] = (u8)(addr >> shift);
|
||||
shift -= 8;
|
||||
}
|
||||
}
|
||||
|
||||
static int fti2c010_read(struct i2c_adapter *adap,
|
||||
u8 dev, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
|
||||
struct fti2c010_regs *regs = chip->regs;
|
||||
int ret, pos;
|
||||
uchar paddr[4];
|
||||
struct fti2c010_regs *regs = curr->regs;
|
||||
|
||||
i2c_init(0, 0);
|
||||
|
||||
paddr[0] = (addr >> 0) & 0xFF;
|
||||
paddr[1] = (addr >> 8) & 0xFF;
|
||||
paddr[2] = (addr >> 16) & 0xFF;
|
||||
paddr[3] = (addr >> 24) & 0xFF;
|
||||
to_i2c_addr(paddr, addr, alen);
|
||||
|
||||
/*
|
||||
* Phase A. Set register address
|
||||
*/
|
||||
|
||||
/* A.1 Select slave device (7bits Address + 1bit R/W) */
|
||||
writel(I2C_WR(chip), ®s->dr);
|
||||
writel(I2C_WR(dev), ®s->dr);
|
||||
writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
|
||||
ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -175,7 +222,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
|
||||
writel(paddr[pos], ®s->dr);
|
||||
writel(ctrl, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
|
||||
ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -185,9 +232,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
*/
|
||||
|
||||
/* B.1 Select slave device (7bits Address + 1bit R/W) */
|
||||
writel(I2C_RD(chip), ®s->dr);
|
||||
writel(I2C_RD(dev), ®s->dr);
|
||||
writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
|
||||
ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -201,7 +248,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
stat |= SR_ACK;
|
||||
}
|
||||
writel(ctrl, ®s->cr);
|
||||
ret = fti2c010_wait(stat);
|
||||
ret = fti2c010_wait(chip, stat);
|
||||
if (ret)
|
||||
break;
|
||||
buf[pos] = (uchar)(readl(®s->dr) & 0xFF);
|
||||
|
|
@ -210,39 +257,24 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read/Write interface:
|
||||
* chip: I2C chip address, range 0..127
|
||||
* addr: Memory (register) address within the chip
|
||||
* alen: Number of bytes to use for addr (typically 1, 2 for larger
|
||||
* memories, 0 for register type devices with only one
|
||||
* register)
|
||||
* buffer: Where to read/write the data
|
||||
* len: How many bytes to read/write
|
||||
*
|
||||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
static int fti2c010_write(struct i2c_adapter *adap,
|
||||
u8 dev, uint addr, int alen, u8 *buf, int len)
|
||||
{
|
||||
struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
|
||||
struct fti2c010_regs *regs = chip->regs;
|
||||
int ret, pos;
|
||||
uchar paddr[4];
|
||||
struct fti2c010_regs *regs = curr->regs;
|
||||
|
||||
i2c_init(0, 0);
|
||||
|
||||
paddr[0] = (addr >> 0) & 0xFF;
|
||||
paddr[1] = (addr >> 8) & 0xFF;
|
||||
paddr[2] = (addr >> 16) & 0xFF;
|
||||
paddr[3] = (addr >> 24) & 0xFF;
|
||||
to_i2c_addr(paddr, addr, alen);
|
||||
|
||||
/*
|
||||
* Phase A. Set register address
|
||||
*
|
||||
* A.1 Select slave device (7bits Address + 1bit R/W)
|
||||
*/
|
||||
writel(I2C_WR(chip), ®s->dr);
|
||||
writel(I2C_WR(dev), ®s->dr);
|
||||
writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
|
||||
ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -252,7 +284,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
|
||||
writel(paddr[pos], ®s->dr);
|
||||
writel(ctrl, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
|
||||
ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -267,7 +299,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
ctrl |= CR_STOP;
|
||||
writel(buf[pos], ®s->dr);
|
||||
writel(ctrl, ®s->cr);
|
||||
ret = fti2c010_wait(SR_DT);
|
||||
ret = fti2c010_wait(chip, SR_DT);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
|
@ -275,94 +307,40 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Functions for setting the current I2C bus and its speed
|
||||
*/
|
||||
#ifdef CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/*
|
||||
* i2c_set_bus_num:
|
||||
*
|
||||
* Change the active I2C bus. Subsequent read/write calls will
|
||||
* go to this one.
|
||||
*
|
||||
* bus - bus index, zero based
|
||||
*
|
||||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
int i2c_set_bus_num(uint bus)
|
||||
static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
|
||||
unsigned int speed)
|
||||
{
|
||||
if (bus >= ARRAY_SIZE(chip_list))
|
||||
return -1;
|
||||
curr = chip_list + bus;
|
||||
i2c_init(0, 0);
|
||||
return 0;
|
||||
struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
|
||||
int ret;
|
||||
|
||||
fti2c010_reset(chip);
|
||||
ret = set_i2c_bus_speed(chip, speed);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* i2c_get_bus_num:
|
||||
*
|
||||
* Returns index of currently active I2C bus. Zero-based.
|
||||
* Register i2c adapters
|
||||
*/
|
||||
|
||||
uint i2c_get_bus_num(void)
|
||||
{
|
||||
return curr->bus;
|
||||
}
|
||||
|
||||
#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
|
||||
|
||||
/*
|
||||
* i2c_set_bus_speed:
|
||||
*
|
||||
* Change the speed of the active I2C bus
|
||||
*
|
||||
* speed - bus speed in Hz
|
||||
*
|
||||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
int i2c_set_bus_speed(uint speed)
|
||||
{
|
||||
struct fti2c010_regs *regs = curr->regs;
|
||||
uint clk = CONFIG_FTI2C010_FREQ;
|
||||
uint gsr = 0, tsr = 32;
|
||||
uint spd, div;
|
||||
|
||||
if (!speed)
|
||||
speed = CONFIG_SYS_I2C_SPEED;
|
||||
|
||||
for (div = 0; div < 0x3ffff; ++div) {
|
||||
/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
|
||||
spd = clk / (2 * (div + 2) + gsr);
|
||||
if (spd <= speed)
|
||||
break;
|
||||
}
|
||||
|
||||
if (curr->speed == spd)
|
||||
return 0;
|
||||
|
||||
writel(CR_I2CRST, ®s->cr);
|
||||
mdelay(100);
|
||||
if (readl(®s->cr) & CR_I2CRST) {
|
||||
printf("fti2c010: reset timeout\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
curr->speed = spd;
|
||||
|
||||
writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
|
||||
writel(CDR_DIV(div), ®s->cdr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* i2c_get_bus_speed:
|
||||
*
|
||||
* Returns speed of currently active I2C bus in Hz
|
||||
*/
|
||||
|
||||
uint i2c_get_bus_speed(void)
|
||||
{
|
||||
return curr->speed;
|
||||
}
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
|
||||
fti2c010_write, fti2c010_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
|
||||
0)
|
||||
#ifdef CONFIG_FTI2C010_BASE1
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
|
||||
fti2c010_write, fti2c010_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
|
||||
1)
|
||||
#endif
|
||||
#ifdef CONFIG_FTI2C010_BASE2
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
|
||||
fti2c010_write, fti2c010_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
|
||||
2)
|
||||
#endif
|
||||
#ifdef CONFIG_FTI2C010_BASE3
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
|
||||
fti2c010_write, fti2c010_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
|
||||
3)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -158,7 +158,6 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
|
|||
udelay(1000);
|
||||
flush_fifo(adap);
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
writew(0, &i2c_base->cnt);
|
||||
}
|
||||
|
||||
static void flush_fifo(struct i2c_adapter *adap)
|
||||
|
|
@ -198,8 +197,6 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
|||
return res;
|
||||
|
||||
/* No data transfer, slave addr only */
|
||||
writew(0, &i2c_base->cnt);
|
||||
/* Set slave address */
|
||||
writew(chip, &i2c_base->sa);
|
||||
/* Stop bit needed here */
|
||||
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
|
||||
|
|
@ -234,7 +231,6 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
|||
pr_exit:
|
||||
flush_fifo(adap);
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
writew(0, &i2c_base->cnt);
|
||||
return res;
|
||||
}
|
||||
|
||||
|
|
@ -372,7 +368,6 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
|||
rd_exit:
|
||||
flush_fifo(adap);
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
writew(0, &i2c_base->cnt);
|
||||
return i2c_error;
|
||||
}
|
||||
|
||||
|
|
@ -473,7 +468,6 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
|||
wr_exit:
|
||||
flush_fifo(adap);
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
writew(0, &i2c_base->cnt);
|
||||
return i2c_error;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -23,8 +23,6 @@
|
|||
#include <i2c.h>
|
||||
#include "s3c24x0_i2c.h"
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
#define I2C_WRITE 0
|
||||
#define I2C_READ 1
|
||||
|
||||
|
|
@ -127,7 +125,6 @@
|
|||
* For SPL boot some boards need i2c before SDRAM is initialised so force
|
||||
* variables to live in SRAM
|
||||
*/
|
||||
static unsigned int g_current_bus __attribute__((section(".data")));
|
||||
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
|
||||
__attribute__((section(".data")));
|
||||
|
||||
|
|
@ -254,17 +251,17 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
|
|||
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
|
||||
}
|
||||
|
||||
static struct s3c24x0_i2c *get_base_i2c(void)
|
||||
static struct s3c24x0_i2c *get_base_i2c(int bus)
|
||||
{
|
||||
#ifdef CONFIG_EXYNOS4
|
||||
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
|
||||
+ (EXYNOS4_I2C_SPACING
|
||||
* g_current_bus));
|
||||
* bus));
|
||||
return i2c;
|
||||
#elif defined CONFIG_EXYNOS5
|
||||
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
|
||||
+ (EXYNOS5_I2C_SPACING
|
||||
* g_current_bus));
|
||||
* bus));
|
||||
return i2c;
|
||||
#else
|
||||
return s3c24x0_get_base_i2c();
|
||||
|
|
@ -298,7 +295,6 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
|
|||
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_I2C_MULTI_BUS
|
||||
static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
|
||||
{
|
||||
struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
|
||||
|
|
@ -307,8 +303,10 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
|
|||
unsigned int i = 0, utemp0 = 0, utemp1 = 0;
|
||||
unsigned int t_ftl_cycle;
|
||||
|
||||
#if defined CONFIG_EXYNOS5
|
||||
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
|
||||
clkin = get_i2c_clk();
|
||||
#else
|
||||
clkin = get_PCLK();
|
||||
#endif
|
||||
/* FPCLK / FI2C =
|
||||
* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
|
||||
|
|
@ -330,7 +328,6 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
|
|||
}
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
|
||||
{
|
||||
|
|
@ -401,49 +398,18 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
|
|||
hsi2c_ch_init(i2c_bus);
|
||||
}
|
||||
|
||||
/*
|
||||
* MULTI BUS I2C support
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_I2C_MULTI_BUS
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c_bus;
|
||||
|
||||
i2c_bus = get_bus(bus);
|
||||
if (!i2c_bus)
|
||||
return -1;
|
||||
g_current_bus = bus;
|
||||
|
||||
if (i2c_bus->is_highspeed) {
|
||||
if (hsi2c_get_clk_details(i2c_bus))
|
||||
return -1;
|
||||
hsi2c_ch_init(i2c_bus);
|
||||
} else {
|
||||
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
|
||||
CONFIG_SYS_I2C_SLAVE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_num(void)
|
||||
{
|
||||
return g_current_bus;
|
||||
}
|
||||
#endif
|
||||
|
||||
void i2c_init(int speed, int slaveadd)
|
||||
static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
|
||||
{
|
||||
struct s3c24x0_i2c *i2c;
|
||||
struct s3c24x0_i2c_bus *bus;
|
||||
|
||||
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
|
||||
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
|
||||
#endif
|
||||
ulong start_time = get_timer(0);
|
||||
|
||||
/* By default i2c channel 0 is the current bus */
|
||||
g_current_bus = 0;
|
||||
i2c = get_base_i2c();
|
||||
i2c = get_base_i2c(adap->hwadapnr);
|
||||
|
||||
/*
|
||||
* In case the previous transfer is still going, wait to give it a
|
||||
|
|
@ -505,6 +471,10 @@ void i2c_init(int speed, int slaveadd)
|
|||
}
|
||||
#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
|
||||
i2c_ch_init(i2c, speed, slaveadd);
|
||||
|
||||
bus = &i2c_bus[adap->hwadapnr];
|
||||
bus->active = true;
|
||||
bus->regs = i2c;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -728,6 +698,40 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
|
|||
return rv;
|
||||
}
|
||||
|
||||
static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
|
||||
unsigned int speed)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c_bus;
|
||||
|
||||
i2c_bus = get_bus(adap->hwadapnr);
|
||||
if (!i2c_bus)
|
||||
return -1;
|
||||
|
||||
i2c_bus->clock_frequency = speed;
|
||||
|
||||
if (i2c_bus->is_highspeed) {
|
||||
if (hsi2c_get_clk_details(i2c_bus))
|
||||
return -1;
|
||||
hsi2c_ch_init(i2c_bus);
|
||||
} else {
|
||||
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_EXYNOS5
|
||||
static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
||||
{
|
||||
/* This will override the speed selected in the fdt for that port */
|
||||
debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
|
||||
if (i2c_set_bus_speed(speed))
|
||||
printf("i2c_init: failed to init bus %d for speed = %d\n",
|
||||
adap->hwadapnr, speed);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* cmd_type is 0 for write, 1 for read.
|
||||
*
|
||||
|
|
@ -840,13 +844,13 @@ bailout:
|
|||
return result;
|
||||
}
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c_bus;
|
||||
uchar buf[1];
|
||||
int ret;
|
||||
|
||||
i2c_bus = get_bus(g_current_bus);
|
||||
i2c_bus = get_bus(adap->hwadapnr);
|
||||
if (!i2c_bus)
|
||||
return -1;
|
||||
buf[0] = 0;
|
||||
|
|
@ -864,11 +868,11 @@ int i2c_probe(uchar chip)
|
|||
I2C_READ, chip << 1, 0, 0, buf, 1);
|
||||
}
|
||||
|
||||
|
||||
return ret != I2C_OK;
|
||||
}
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
||||
int alen, uchar *buffer, int len)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c_bus;
|
||||
uchar xaddr[4];
|
||||
|
|
@ -902,7 +906,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
chip |= ((addr >> (alen * 8)) &
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
i2c_bus = get_bus(g_current_bus);
|
||||
i2c_bus = get_bus(adap->hwadapnr);
|
||||
if (!i2c_bus)
|
||||
return -1;
|
||||
|
||||
|
|
@ -922,7 +926,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
||||
int alen, uchar *buffer, int len)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c_bus;
|
||||
uchar xaddr[4];
|
||||
|
|
@ -955,7 +960,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
chip |= ((addr >> (alen * 8)) &
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
i2c_bus = get_bus(g_current_bus);
|
||||
i2c_bus = get_bus(adap->hwadapnr);
|
||||
if (!i2c_bus)
|
||||
return -1;
|
||||
|
||||
|
|
@ -1001,8 +1006,8 @@ static void process_nodes(const void *blob, int node_list[], int count,
|
|||
|
||||
bus->id = pinmux_decode_periph_id(blob, node);
|
||||
bus->clock_frequency = fdtdec_get_int(blob, node,
|
||||
"clock-frequency",
|
||||
CONFIG_SYS_I2C_SPEED);
|
||||
"clock-frequency",
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED);
|
||||
bus->node = node;
|
||||
bus->bus_num = i;
|
||||
exynos_pinmux_config(bus->id, 0);
|
||||
|
|
@ -1044,7 +1049,6 @@ int i2c_get_bus_num_fdt(int node)
|
|||
return -1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_I2C_MULTI_BUS
|
||||
int i2c_reset_port_fdt(const void *blob, int node)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c_bus;
|
||||
|
|
@ -1068,12 +1072,178 @@ int i2c_reset_port_fdt(const void *blob, int node)
|
|||
hsi2c_ch_init(i2c_bus);
|
||||
} else {
|
||||
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
|
||||
CONFIG_SYS_I2C_SLAVE);
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
/*
|
||||
* Register s3c24x0 i2c adapters
|
||||
*/
|
||||
#if defined(CONFIG_EXYNOS5420)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
|
||||
#elif defined(CONFIG_EXYNOS5250)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
|
||||
#elif defined(CONFIG_EXYNOS4)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
|
||||
U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
|
||||
#else
|
||||
U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
|
||||
s3c24x0_i2c_read, s3c24x0_i2c_write,
|
||||
s3c24x0_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_S3C24X0_SPEED,
|
||||
CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -73,12 +73,12 @@
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|||
* the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
|
||||
* address 0x50 with 16bit addressing
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
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||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
/* we use the built-in I2C controller */
|
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#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
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#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */
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||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
|
|
|||
|
|
@ -214,13 +214,12 @@
|
|||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
|
|
|
|||
|
|
@ -249,13 +249,13 @@
|
|||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
*/
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* which is in a S5P Family */
|
||||
#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
|
||||
#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
|
||||
#define CONFIG_TRATS /* working with TRATS */
|
||||
#define CONFIG_TIZEN /* TIZEN lib */
|
||||
|
|
@ -268,31 +269,21 @@
|
|||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
|
||||
#define I2C_SOFT_DECLARATIONS2
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SOFT_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 15
|
||||
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
/* I2C PMIC */
|
||||
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
|
||||
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
|
||||
|
||||
/* I2C FG */
|
||||
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
|
||||
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
|
||||
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
|
||||
#define I2C_INIT multi_i2c_init()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
|
||||
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
|
|
|
|||
|
|
@ -260,30 +260,25 @@
|
|||
#include <asm/arch/gpio.h>
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SOFT
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
|
||||
#define I2C_SOFT_DECLARATIONS2
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
|
||||
#define I2C_SOFT_DECLARATIONS3
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00
|
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SOFT_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 15
|
||||
|
||||
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
|
||||
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
|
||||
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
|
||||
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
|
||||
#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
|
||||
#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
|
||||
#define I2C_INIT multi_i2c_init()
|
||||
#ifndef __ASSEMBLY__
|
||||
int get_soft_i2c_scl_pin(void);
|
||||
int get_soft_i2c_sda_pin(void);
|
||||
#endif
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
|
||||
|
||||
/* POWER */
|
||||
#define CONFIG_POWER
|
||||
|
|
|
|||
Loading…
Reference in a new issue