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arm64: mvebu: a8k: align memory regions

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1. RAM: base address 0x0 size 2Gbytes
2. MMIO: base address 0xf0000000 size 1Gbytes

Signed-off-by: Ofir Fedida <ofedida@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
jinghua 2021-04-30 15:29:47 +02:00 committed by Stefan Roese
parent 9c84159ce1
commit 762f9fba0f
1 changed files with 7 additions and 55 deletions
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62
arch/arm/mach-mvebu/armada8k/cpu.c
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@ -8,6 +8,7 @@
#include <dm.h> #include <dm.h>
#include <fdtdec.h> #include <fdtdec.h>
#include <linux/libfdt.h> #include <linux/libfdt.h>
#include <linux/sizes.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/arch/cpu.h> #include <asm/arch/cpu.h>
@ -23,62 +24,22 @@
#define BOOT_MODE_MASK 0x3f #define BOOT_MODE_MASK 0x3f
#define BOOT_MODE_OFFSET 4 #define BOOT_MODE_OFFSET 4
/*
* The following table includes all memory regions for Armada 7k and
* 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
* define these regions at the beginning of the struct so that they
* can be easier removed later dynamically if an Armada 7k device is detected.
* For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
*/
#define ARMADA_7K8K_COMMON_REGIONS_START 2
static struct mm_region mvebu_mem_map[] = { static struct mm_region mvebu_mem_map[] = {
/* Armada 80x0 memory regions include the CP1 (slave) units */ /* Armada 80x0 memory regions include the CP1 (slave) units */
{
/* SRAM, MMIO regions - CP110 slave region */
.phys = 0xf4000000UL,
.virt = 0xf4000000UL,
.size = 0x02000000UL, /* 32MiB internal registers */
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
},
{
/* PCI CP1 regions */
.phys = 0xfa000000UL,
.virt = 0xfa000000UL,
.size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
},
/* Armada 80x0 and 70x0 common memory regions start here */
{ {
/* RAM */ /* RAM */
.phys = 0x0UL, .phys = 0x0UL,
.virt = 0x0UL, .virt = 0x0UL,
.size = 0x80000000UL, .size = SZ_2G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE PTE_BLOCK_INNER_SHARE
}, },
{ {
/* SRAM, MMIO regions - AP806 region */ /* MMIO regions */
.phys = 0xf0000000UL, .phys = SOC_REGS_PHY_BASE,
.virt = 0xf0000000UL, .virt = SOC_REGS_PHY_BASE,
.size = 0x01000000UL, /* 16MiB internal registers */ .size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
},
{
/* SRAM, MMIO regions - CP110 master region */
.phys = 0xf2000000UL,
.virt = 0xf2000000UL,
.size = 0x02000000UL, /* 32MiB internal registers */
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
},
{
/* PCI CP0 regions */
.phys = 0xf6000000UL,
.virt = 0xf6000000UL,
.size = 0x04000000UL, /* 64MiB CP110 master PCI space */
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE PTE_BLOCK_NON_SHARE
}, },
@ -91,15 +52,6 @@ struct mm_region *mem_map = mvebu_mem_map;
void enable_caches(void) void enable_caches(void)
{ {
/*
* Armada 7k is not equipped with the CP110 slave CP. In case this
* code runs on an Armada 7k device, lets remove the CP110 slave
* entries from the memory mapping by moving the start to the
* common regions.
*/
if (of_machine_is_compatible("marvell,armada7040"))
mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
icache_enable(); icache_enable();
dcache_enable(); dcache_enable();
} }