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powerpc/mpc85xx: Skip zero values for DDR debug registers

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Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.

Also add debug messages for workarounds and debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2012-08-17 08:22:36 +00:00 committed by Andy Fleming
parent 709389b654
commit 744713a6a3
1 changed files with 11 additions and 3 deletions
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14
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
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@ -1,5 +1,5 @@
/* /*
* Copyright 2008-2011 Freescale Semiconductor, Inc. * Copyright 2008-2012 Freescale Semiconductor, Inc.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
@ -43,6 +43,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->eor, regs->ddr_eor); out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
debug("Workaround for ERRATUM_DDR111_DDR134\n");
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
cs_ea = regs->cs[i].bnds & 0xfff; cs_ea = regs->cs[i].bnds & 0xfff;
@ -115,8 +116,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
out_be32(&ddr->err_disable, regs->err_disable); out_be32(&ddr->err_disable, regs->err_disable);
out_be32(&ddr->err_int_en, regs->err_int_en); out_be32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) for (i = 0; i < 32; i++) {
out_be32(&ddr->debug[i], regs->debug[i]); if (regs->debug[i]) {
debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015); out_be32(&ddr->debug[12], 0x00000015);
@ -128,6 +133,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg); out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
debug("Workaround for ERRATUM_DDR_A003\n");
if (regs->ddr_sdram_rcw_2 & 0x00f00000) { if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
out_be32(&ddr->debug[2], 0x00000400); out_be32(&ddr->debug[2], 0x00000400);
@ -209,6 +215,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
* This erratum does not affect DDR3 mode, only for DDR2 mode. * This erratum does not affect DDR3 mode, only for DDR2 mode.
*/ */
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
debug("Workaround for ERRATUM_DDR_115\n");
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg) & 0x80000) { && in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */ /* set DEBUG_1[31] */
@ -216,6 +223,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
} }
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
debug("Workaround for ERRATUM_DDR111_DDR134\n");
/* /*
* This is the combined workaround for DDR111 and DDR134 * This is the combined workaround for DDR111 and DDR134
* following the published errata for MPC8572 * following the published errata for MPC8572