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https://github.com/AsahiLinux/u-boot
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Merge tag 'u-boot-nand-20221009' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next
- mtd: Update the function name to 'rfree' - Support NAND ONFI EDO mode for imx8mn architecture - dm: clk: add missing stub when CONFIG_CLK is deactivated -----BEGIN PGP SIGNATURE----- iQJYBAABCgBCFiEE6GOTDNYiFygVXvMmQBtB6IWRjvEFAmNCjWEkHGRhcmlvLmJp bmFjY2hpQGFtYXJ1bGFzb2x1dGlvbnMuY29tAAoJEEAbQeiFkY7xDX8QAJThWN9n SosBNLqlxhe3s928K/KZsvnIdlJ6pMQ5NMFVWEMXptPx8v9PtFPj3mJwR8nqAjq6 5FYkfkt3TimPz48+n7q/bBVsD1jpJz5/POsPUPbnmMdVKtuIguLKg0SxxQXUpwPh 8e00KvyqBmP66PbSP4UfzaGm7RojhT8riWbxVo81DYd2kKRSDcQc2PFUic1wjkz+ l1FHkARz0dBjxgdFGyvUQV82hXlbwTk9ZDtCE6vdtBcfdem0XdnIRknV+j8G7pSc vCRv583AniyiOCNmVomLxvcyBpOtIruUdmRHDRY1pKdyDWNmdRgQqLpApKdWH9Bz x0x50GAvGGuh9/Rl5bR+QGjJw5egL7DcuOJXHcQcuG5zNdeUgbBBLUdasGZER0P9 BxPiGY60N46sZNEEVpl68c2tVcHvoA4Zl8UWoJijbJZC08DYp5aeAECN70N1k4ok FOuMex99LZK3gYKZfMueL+rX2jtalQbcAMcJtGQJa2d4PhlOKy/fq5ckcEzj46b7 iwGLxV48fxKb6UH/WjnVYihY2gwux4PwfCfpQwvEGjDqP80fkqp5E1Od63xaF5gw vMdjbYQ9aOH3QTSkfcs4oYhvqp1qKMG8fJNZJeArZlMgdfW/MSmaA79H846iUT9x XfoSDHCEy+6wmQT/SW3h33WoGW2RSTqP4mge =VPkV -----END PGP SIGNATURE----- Merge tag 'u-boot-nand-20221009' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash - mtd: Update the function name to 'rfree' - Support NAND ONFI EDO mode for imx8mn architecture - dm: clk: add missing stub when CONFIG_CLK is deactivated
This commit is contained in:
Tom Rini
commit
73e741b8ee
10 changed files with 343 additions and 56 deletions
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@ -93,6 +93,11 @@ struct mxs_gpmi_regs {
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#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
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#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
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#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
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#define GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0
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#define GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1
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#define GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2
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#define GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3
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#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
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#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
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#define GPMI_CTRL1_BCH_MODE (1 << 18)
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@ -111,6 +116,10 @@ struct mxs_gpmi_regs {
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#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
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#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
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#define GPMI_CTRL1_GPMI_MODE (1 << 0)
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#define GPMI_CTRL1_CLEAR_MASK (GPMI_CTRL1_WRN_DLY_SEL_MASK | \
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GPMI_CTRL1_DLL_ENABLE | \
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GPMI_CTRL1_RDN_DELAY_MASK | \
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GPMI_CTRL1_HALF_PERIOD)
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#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
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#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
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@ -20,6 +20,7 @@
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <linux/bug.h>
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#include <linux/clk-provider.h>
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#include <clk.h>
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#include "clk.h"
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@ -33,6 +34,7 @@ struct clk_gate2 {
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u8 bit_idx;
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u8 cgr_val;
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u8 flags;
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unsigned int *share_count;
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};
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#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
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@ -42,6 +44,9 @@ static int clk_gate2_enable(struct clk *clk)
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struct clk_gate2 *gate = to_clk_gate2(clk);
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u32 reg;
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if (gate->share_count && (*gate->share_count)++ > 0)
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return 0;
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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reg |= gate->cgr_val << gate->bit_idx;
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@ -55,6 +60,13 @@ static int clk_gate2_disable(struct clk *clk)
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struct clk_gate2 *gate = to_clk_gate2(clk);
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u32 reg;
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if (gate->share_count) {
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if (WARN_ON(*gate->share_count == 0))
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return 0;
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else if (--(*gate->share_count) > 0)
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return 0;
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}
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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writel(reg, gate->reg);
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@ -82,7 +94,7 @@ static const struct clk_ops clk_gate2_ops = {
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate2_flags)
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u8 clk_gate2_flags, unsigned int *share_count)
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{
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struct clk_gate2 *gate;
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struct clk *clk;
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@ -96,6 +108,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
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gate->bit_idx = bit_idx;
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gate->cgr_val = cgr_val;
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gate->flags = clk_gate2_flags;
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gate->share_count = share_count;
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clk = &gate->clk;
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@ -15,6 +15,8 @@
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#include "clk.h"
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static u32 share_count_nand;
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static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
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static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
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static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
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@ -90,6 +92,10 @@ static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
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static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
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"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
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static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
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"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
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"sys_pll2_250m", "video_pll1_out", };
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static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
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"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
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"clk_ext3", "audio_pll2_out", };
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@ -268,6 +274,8 @@ static int imx8mn_clk_probe(struct udevice *dev)
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clk_dm(IMX8MN_CLK_USDHC3,
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imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
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base + 0xbc80));
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clk_dm(IMX8MN_CLK_NAND,
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imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
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clk_dm(IMX8MN_CLK_QSPI,
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imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
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clk_dm(IMX8MN_CLK_USB_CORE_REF,
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@ -299,6 +307,12 @@ static int imx8mn_clk_probe(struct udevice *dev)
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imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
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clk_dm(IMX8MN_CLK_QSPI_ROOT,
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imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
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clk_dm(IMX8MN_CLK_NAND_ROOT,
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imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
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clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
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imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
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"nand_usdhc_bus", base + 0x4300, 0,
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&share_count_nand));
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clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
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imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
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@ -53,7 +53,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate_flags);
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u8 clk_gate_flags, unsigned int *share_count);
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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@ -63,7 +63,26 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0);
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shift, 0x3, 0, NULL);
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}
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static inline struct clk *imx_clk_gate2_shared(const char *name,
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const char *parent,
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void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0, share_count);
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}
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static inline struct clk *imx_clk_gate2_shared2(const char *name,
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const char *parent,
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void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
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share_count);
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}
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static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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@ -71,7 +90,7 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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{
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return clk_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0);
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reg, shift, 0x3, 0, NULL);
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}
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static inline struct clk *imx_clk_gate4_flags(const char *name,
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@ -80,7 +99,7 @@ static inline struct clk *imx_clk_gate4_flags(const char *name,
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{
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return clk_register_gate2(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0);
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reg, shift, 0x3, 0, NULL);
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}
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static inline struct clk *imx_clk_fixed_factor(const char *name,
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@ -14,6 +14,7 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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@ -26,10 +27,12 @@
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#include <asm/io.h>
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#include <asm/mach-imx/regs-bch.h>
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#include <asm/mach-imx/regs-gpmi.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#include <linux/math64.h>
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#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
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@ -49,6 +52,10 @@
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#endif
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#define MXS_NAND_BCH_TIMEOUT 10000
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#define USEC_PER_SEC 1000000
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#define NSEC_PER_SEC 1000000000L
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#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
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struct nand_ecclayout fake_ecc_layout;
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@ -1344,6 +1351,196 @@ err1:
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return ret;
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}
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/*
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* <1> Firstly, we should know what's the GPMI-clock means.
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* The GPMI-clock is the internal clock in the gpmi nand controller.
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* If you set 100MHz to gpmi nand controller, the GPMI-clock's period
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* is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
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*
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* <2> Secondly, we should know what's the frequency on the nand chip pins.
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* The frequency on the nand chip pins is derived from the GPMI-clock.
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* We can get it from the following equation:
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*
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* F = G / (DS + DH)
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*
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* F : the frequency on the nand chip pins.
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* G : the GPMI clock, such as 100MHz.
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* DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
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* DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
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*
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* <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
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* the nand EDO(extended Data Out) timing could be applied.
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* The GPMI implements a feedback read strobe to sample the read data.
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* The feedback read strobe can be delayed to support the nand EDO timing
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* where the read strobe may deasserts before the read data is valid, and
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* read data is valid for some time after read strobe.
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*
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* The following figure illustrates some aspects of a NAND Flash read:
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*
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* |<---tREA---->|
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* | |
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* | | |
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* |<--tRP-->| |
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* | | |
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* __ ___|__________________________________
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* RDN \________/ |
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* |
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* /---------\
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* Read Data --------------< >---------
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* \---------/
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* | |
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* |<-D->|
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* FeedbackRDN ________ ____________
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* \___________/
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*
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* D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
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*
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*
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* <4> Now, we begin to describe how to compute the right RDN_DELAY.
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*
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* 4.1) From the aspect of the nand chip pins:
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* Delay = (tREA + C - tRP) {1}
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*
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* tREA : the maximum read access time.
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* C : a constant to adjust the delay. default is 4000ps.
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* tRP : the read pulse width, which is exactly:
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* tRP = (GPMI-clock-period) * DATA_SETUP
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*
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* 4.2) From the aspect of the GPMI nand controller:
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* Delay = RDN_DELAY * 0.125 * RP {2}
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*
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* RP : the DLL reference period.
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* if (GPMI-clock-period > DLL_THRETHOLD)
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* RP = GPMI-clock-period / 2;
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* else
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* RP = GPMI-clock-period;
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*
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* Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
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* is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
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* is 16000ps, but in mx6q, we use 12000ps.
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*
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* 4.3) since {1} equals {2}, we get:
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*
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* (tREA + 4000 - tRP) * 8
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* RDN_DELAY = ----------------------- {3}
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* RP
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*/
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static void mxs_compute_timings(struct nand_chip *chip,
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const struct nand_sdr_timings *sdr)
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{
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struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
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unsigned long clk_rate;
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unsigned int dll_wait_time_us;
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unsigned int dll_threshold_ps = nand_info->max_chain_delay;
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unsigned int period_ps, reference_period_ps;
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unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles;
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unsigned int tRP_ps;
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bool use_half_period;
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int sample_delay_ps, sample_delay_factor;
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u16 busy_timeout_cycles;
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u8 wrn_dly_sel;
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u32 timing0;
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u32 timing1;
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u32 ctrl1n;
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if (sdr->tRC_min >= 30000) {
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/* ONFI non-EDO modes [0-3] */
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clk_rate = 22000000;
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wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
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} else if (sdr->tRC_min >= 25000) {
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/* ONFI EDO mode 4 */
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clk_rate = 80000000;
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wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
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debug("%s, setting ONFI onfi edo 4\n", __func__);
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} else {
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/* ONFI EDO mode 5 */
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clk_rate = 100000000;
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wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
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debug("%s, setting ONFI onfi edo 5\n", __func__);
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}
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/* SDR core timings are given in picoseconds */
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period_ps = div_u64((u64)NSEC_PER_SEC * 1000, clk_rate);
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addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps);
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data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps);
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data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps);
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busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
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timing0 = (addr_setup_cycles << GPMI_TIMING0_ADDRESS_SETUP_OFFSET) |
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(data_hold_cycles << GPMI_TIMING0_DATA_HOLD_OFFSET) |
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(data_setup_cycles << GPMI_TIMING0_DATA_SETUP_OFFSET);
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timing1 = (busy_timeout_cycles * 4096) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET;
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/*
|
||||
* Derive NFC ideal delay from {3}:
|
||||
*
|
||||
* (tREA + 4000 - tRP) * 8
|
||||
* RDN_DELAY = -----------------------
|
||||
* RP
|
||||
*/
|
||||
if (period_ps > dll_threshold_ps) {
|
||||
use_half_period = true;
|
||||
reference_period_ps = period_ps / 2;
|
||||
} else {
|
||||
use_half_period = false;
|
||||
reference_period_ps = period_ps;
|
||||
}
|
||||
|
||||
tRP_ps = data_setup_cycles * period_ps;
|
||||
sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8;
|
||||
if (sample_delay_ps > 0)
|
||||
sample_delay_factor = sample_delay_ps / reference_period_ps;
|
||||
else
|
||||
sample_delay_factor = 0;
|
||||
|
||||
ctrl1n = (wrn_dly_sel << GPMI_CTRL1_WRN_DLY_SEL_OFFSET);
|
||||
if (sample_delay_factor)
|
||||
ctrl1n |= (sample_delay_factor << GPMI_CTRL1_RDN_DELAY_OFFSET) |
|
||||
GPMI_CTRL1_DLL_ENABLE |
|
||||
(use_half_period ? GPMI_CTRL1_HALF_PERIOD : 0);
|
||||
|
||||
writel(timing0, &nand_info->gpmi_regs->hw_gpmi_timing0);
|
||||
writel(timing1, &nand_info->gpmi_regs->hw_gpmi_timing1);
|
||||
|
||||
/*
|
||||
* Clear several CTRL1 fields, DLL must be disabled when setting
|
||||
* RDN_DELAY or HALF_PERIOD.
|
||||
*/
|
||||
writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr);
|
||||
writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set);
|
||||
|
||||
clk_set_rate(nand_info->gpmi_clk, clk_rate);
|
||||
|
||||
/* Wait 64 clock cycles before using the GPMI after enabling the DLL */
|
||||
dll_wait_time_us = USEC_PER_SEC / clk_rate * 64;
|
||||
if (!dll_wait_time_us)
|
||||
dll_wait_time_us = 1;
|
||||
|
||||
/* Wait for the DLL to settle. */
|
||||
udelay(dll_wait_time_us);
|
||||
}
|
||||
|
||||
static int mxs_nand_setup_interface(struct mtd_info *mtd, int chipnr,
|
||||
const struct nand_data_interface *conf)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
const struct nand_sdr_timings *sdr;
|
||||
|
||||
sdr = nand_get_sdr_timings(conf);
|
||||
if (IS_ERR(sdr))
|
||||
return PTR_ERR(sdr);
|
||||
|
||||
/* Stop here if this call was just a check */
|
||||
if (chipnr < 0)
|
||||
return 0;
|
||||
|
||||
/* Do the actual derivation of the controller timings */
|
||||
mxs_compute_timings(chip, sdr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mxs_nand_init_spl(struct nand_chip *nand)
|
||||
{
|
||||
struct mxs_nand_info *nand_info;
|
||||
|
|
@ -1432,6 +1629,9 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info)
|
|||
nand->read_buf = mxs_nand_read_buf;
|
||||
nand->write_buf = mxs_nand_write_buf;
|
||||
|
||||
if (nand_info->gpmi_clk)
|
||||
nand->setup_data_interface = mxs_nand_setup_interface;
|
||||
|
||||
/* first scan to find the device and get the page size */
|
||||
if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
|
||||
goto err_free_buffers;
|
||||
|
|
|
|||
|
|
@ -22,22 +22,27 @@
|
|||
|
||||
struct mxs_nand_dt_data {
|
||||
unsigned int max_ecc_strength_supported;
|
||||
int max_chain_delay; /* See the async EDO mode */
|
||||
};
|
||||
|
||||
static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
|
||||
.max_ecc_strength_supported = 40,
|
||||
.max_chain_delay = 12000,
|
||||
};
|
||||
|
||||
static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = {
|
||||
.max_ecc_strength_supported = 62,
|
||||
.max_chain_delay = 12000,
|
||||
};
|
||||
|
||||
static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
|
||||
.max_ecc_strength_supported = 62,
|
||||
.max_chain_delay = 12000,
|
||||
};
|
||||
|
||||
static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
|
||||
.max_ecc_strength_supported = 62,
|
||||
.max_chain_delay = 12000,
|
||||
};
|
||||
|
||||
static const struct udevice_id mxs_nand_dt_ids[] = {
|
||||
|
|
@ -72,8 +77,10 @@ static int mxs_nand_dt_probe(struct udevice *dev)
|
|||
int ret;
|
||||
|
||||
data = (void *)dev_get_driver_data(dev);
|
||||
if (data)
|
||||
if (data) {
|
||||
info->max_ecc_strength_supported = data->max_ecc_strength_supported;
|
||||
info->max_chain_delay = data->max_chain_delay;
|
||||
}
|
||||
|
||||
info->dev = dev;
|
||||
|
||||
|
|
@ -92,69 +99,61 @@ static int mxs_nand_dt_probe(struct udevice *dev)
|
|||
|
||||
info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
|
||||
|
||||
if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) {
|
||||
if (IS_ENABLED(CONFIG_CLK) &&
|
||||
(IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
|
||||
/* Assigned clock already set clock */
|
||||
struct clk gpmi_clk;
|
||||
|
||||
ret = clk_get_by_name(dev, "gpmi_io", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
info->gpmi_clk = devm_clk_get(dev, "gpmi_io");
|
||||
|
||||
if (IS_ERR(info->gpmi_clk)) {
|
||||
ret = PTR_ERR(info->gpmi_clk);
|
||||
debug("Can't get gpmi io clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
ret = clk_enable(info->gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi io clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_apb clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
if (IS_ENABLED(CONFIG_IMX8)) {
|
||||
ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_apb clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi_apb clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_bch clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi_bch clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "gpmi_apb_bch", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_apb_bch clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi_apb_bch clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* this clock is used for apbh_dma, since the apbh dma does not support DM,
|
||||
* we optionally enable it here
|
||||
*/
|
||||
ret = clk_get_by_name(dev, "gpmi_apbh_dma", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_apbh_dma clk: %d\n", ret);
|
||||
} else {
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi_apbh_dma clk: %d\n", ret);
|
||||
debug("Can't enable gpmi_apb clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_bch clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi_bch clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't get gpmi_bch_apb clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&gpmi_clk);
|
||||
if (ret < 0) {
|
||||
debug("Can't enable gpmi_bch_apb clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ int nand_curr_device = -1;
|
|||
|
||||
static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
|
||||
|
||||
#ifndef CONFIG_SYS_NAND_SELF_INIT
|
||||
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
|
||||
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
|
||||
static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -88,8 +88,9 @@ struct clk_bulk {
|
|||
unsigned int count;
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
|
||||
struct phandle_1_arg;
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
|
||||
/**
|
||||
* clk_get_by_phandle() - Get a clock by its phandle information (of-platadata)
|
||||
* @dev: Device containing the phandle
|
||||
|
|
@ -258,12 +259,26 @@ int clk_release_all(struct clk *clk, int count);
|
|||
void devm_clk_put(struct udevice *dev, struct clk *clk);
|
||||
|
||||
#else
|
||||
|
||||
static inline int clk_get_by_phandle(struct udevice *dev, const
|
||||
struct phandle_1_arg *cells,
|
||||
struct clk *clk)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int clk_get_by_index(struct udevice *dev, int index,
|
||||
struct clk *clk)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int clk_get_by_index_nodev(ofnode node, int index,
|
||||
struct clk *clk)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
|
||||
{
|
||||
return -ENOSYS;
|
||||
|
|
@ -275,6 +290,17 @@ static inline int clk_get_by_name(struct udevice *dev, const char *name,
|
|||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get(struct udevice *dev, const char *id)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get_optional(struct udevice *dev,
|
||||
const char *id)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
static inline int
|
||||
clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
|
||||
{
|
||||
|
|
@ -285,6 +311,10 @@ static inline int clk_release_all(struct clk *clk, int count)
|
|||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline void devm_clk_put(struct udevice *dev, struct clk *clk)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ struct mtd_oob_region {
|
|||
* @ecc: function returning an ECC region in the OOB area.
|
||||
* Should return -ERANGE if %section exceeds the total number of
|
||||
* ECC sections.
|
||||
* @free: function returning a free region in the OOB area.
|
||||
* @rfree: function returning a free region in the OOB area.
|
||||
* Should return -ERANGE if %section exceeds the total number of
|
||||
* free sections.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <asm/cache.h>
|
||||
#include <nand.h>
|
||||
#include <asm/mach-imx/dma.h>
|
||||
#include <clk.h>
|
||||
|
||||
/**
|
||||
* @gf_len: The length of Galois Field. (e.g., 13 or 14)
|
||||
|
|
@ -43,6 +44,7 @@ struct mxs_nand_info {
|
|||
struct nand_chip chip;
|
||||
struct udevice *dev;
|
||||
unsigned int max_ecc_strength_supported;
|
||||
int max_chain_delay;
|
||||
bool use_minimum_ecc;
|
||||
int cur_chip;
|
||||
|
||||
|
|
@ -59,6 +61,7 @@ struct mxs_nand_info {
|
|||
|
||||
struct mxs_gpmi_regs *gpmi_regs;
|
||||
struct mxs_bch_regs *bch_regs;
|
||||
struct clk *gpmi_clk;
|
||||
|
||||
/* Functions with altered behaviour */
|
||||
int (*hooked_read_oob)(struct mtd_info *mtd,
|
||||
|
|
|
|||
Loading…
Reference in a new issue