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https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
dm: exynos: Move serial to driver model
Change the Exynos serial driver to work with driver model and switch over all relevant boards to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
9208fffebc
commit
73e256c2ac
4 changed files with 80 additions and 188 deletions
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@ -9,6 +9,8 @@
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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@ -18,26 +20,18 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define RX_FIFO_COUNT_MASK 0xff
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#define RX_FIFO_FULL_MASK (1 << 8)
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#define TX_FIFO_FULL_MASK (1 << 24)
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#define RX_FIFO_COUNT_SHIFT 0
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#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
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#define RX_FIFO_FULL (1 << 8)
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#define TX_FIFO_COUNT_SHIFT 16
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#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
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#define TX_FIFO_FULL (1 << 24)
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/* Information about a serial port */
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struct fdt_serial {
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u32 base_addr; /* address of registers in physical memory */
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struct s5p_serial_platdata {
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struct s5p_uart *reg; /* address of registers in physical memory */
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u8 port_id; /* uart port number */
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u8 enabled; /* 1 if enabled, 0 if disabled */
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} config __attribute__ ((section(".data")));
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static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
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{
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#ifdef CONFIG_OF_CONTROL
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return (struct s5p_uart *)(config.base_addr);
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#else
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u32 offset = dev_index * sizeof(struct s5p_uart);
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return (struct s5p_uart *)(samsung_get_base_uart() + offset);
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#endif
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}
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};
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/*
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* The coefficient, used to calculate the baudrate on S5P UARTs is
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@ -65,23 +59,13 @@ static const int udivslot[] = {
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0xffdf,
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};
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static void serial_setbrg_dev(const int dev_index)
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int s5p_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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u32 uclk = get_uart_clk(dev_index);
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u32 baudrate = gd->baudrate;
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struct s5p_serial_platdata *plat = dev->platdata;
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struct s5p_uart *const uart = plat->reg;
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u32 uclk = get_uart_clk(plat->port_id);
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u32 val;
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#if defined(CONFIG_SILENT_CONSOLE) && \
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defined(CONFIG_OF_CONTROL) && \
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!defined(CONFIG_SPL_BUILD)
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if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0))
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gd->flags |= GD_FLG_SILENT;
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#endif
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if (!config.enabled)
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return;
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val = uclk / baudrate;
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writel(val / 16 - 1, &uart->ubrdiv);
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@ -90,15 +74,14 @@ static void serial_setbrg_dev(const int dev_index)
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writew(udivslot[val % 16], &uart->rest.slot);
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else
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writeb(val % 16, &uart->rest.value);
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return 0;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int serial_init_dev(const int dev_index)
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static int s5p_serial_probe(struct udevice *dev)
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{
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struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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struct s5p_serial_platdata *plat = dev->platdata;
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struct s5p_uart *const uart = plat->reg;
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/* enable FIFOs, auto clear Rx FIFO */
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writel(0x3, &uart->ufcon);
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@ -108,14 +91,11 @@ static int serial_init_dev(const int dev_index)
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/* No interrupts, no DMA, pure polling */
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writel(0x245, &uart->ucon);
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serial_setbrg_dev(dev_index);
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return 0;
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}
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static int serial_err_check(const int dev_index, int op)
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static int serial_err_check(const struct s5p_uart *const uart, int op)
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{
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struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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unsigned int mask;
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/*
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@ -133,169 +113,78 @@ static int serial_err_check(const int dev_index, int op)
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return readl(&uart->uerstat) & mask;
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}
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/*
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* Read a single byte from the serial port. Returns 1 on success, 0
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* otherwise. When the function is succesfull, the character read is
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* written into its argument c.
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*/
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static int serial_getc_dev(const int dev_index)
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static int s5p_serial_getc(struct udevice *dev)
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{
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struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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struct s5p_serial_platdata *plat = dev->platdata;
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struct s5p_uart *const uart = plat->reg;
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if (!config.enabled)
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return 0;
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/* wait for character to arrive */
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while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
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RX_FIFO_FULL_MASK))) {
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if (serial_err_check(dev_index, 0))
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return 0;
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}
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if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
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return -EAGAIN;
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serial_err_check(uart, 0);
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return (int)(readb(&uart->urxh) & 0xff);
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}
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/*
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* Output a single byte to the serial port.
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*/
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static void serial_putc_dev(const char c, const int dev_index)
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static int s5p_serial_putc(struct udevice *dev, const char ch)
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{
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struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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struct s5p_serial_platdata *plat = dev->platdata;
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struct s5p_uart *const uart = plat->reg;
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if (!config.enabled)
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return;
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if (readl(&uart->ufstat) & TX_FIFO_FULL)
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return -EAGAIN;
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/* wait for room in the tx FIFO */
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while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
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if (serial_err_check(dev_index, 1))
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return;
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}
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writeb(c, &uart->utxh);
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/* If \n, also do \r */
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if (c == '\n')
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serial_putc('\r');
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}
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/*
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* Test whether a character is in the RX buffer
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*/
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static int serial_tstc_dev(const int dev_index)
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{
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struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
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if (!config.enabled)
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return 0;
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return (int)(readl(&uart->utrstat) & 0x1);
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}
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static void serial_puts_dev(const char *s, const int dev_index)
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{
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while (*s)
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serial_putc_dev(*s++, dev_index);
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}
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/* Multi serial device functions */
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#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \
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static int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
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static void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
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static int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
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static int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
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static void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
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static void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
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#define INIT_S5P_SERIAL_STRUCTURE(port, __name) { \
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.name = __name, \
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.start = s5p_serial##port##_init, \
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.stop = NULL, \
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.setbrg = s5p_serial##port##_setbrg, \
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.getc = s5p_serial##port##_getc, \
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.tstc = s5p_serial##port##_tstc, \
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.putc = s5p_serial##port##_putc, \
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.puts = s5p_serial##port##_puts, \
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}
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DECLARE_S5P_SERIAL_FUNCTIONS(0);
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struct serial_device s5p_serial0_device =
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INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0");
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DECLARE_S5P_SERIAL_FUNCTIONS(1);
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struct serial_device s5p_serial1_device =
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INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1");
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DECLARE_S5P_SERIAL_FUNCTIONS(2);
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struct serial_device s5p_serial2_device =
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INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2");
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DECLARE_S5P_SERIAL_FUNCTIONS(3);
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struct serial_device s5p_serial3_device =
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INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
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#ifdef CONFIG_OF_CONTROL
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int fdtdec_decode_console(int *index, struct fdt_serial *uart)
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{
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const void *blob = gd->fdt_blob;
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int node;
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node = fdt_path_offset(blob, "console");
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if (node < 0)
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return node;
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uart->base_addr = fdtdec_get_addr(blob, node, "reg");
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if (uart->base_addr == FDT_ADDR_T_NONE)
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return -FDT_ERR_NOTFOUND;
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uart->port_id = fdtdec_get_int(blob, node, "id", -1);
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uart->enabled = fdtdec_get_is_enabled(blob, node);
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writeb(ch, &uart->utxh);
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serial_err_check(uart, 1);
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return 0;
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}
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#endif
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__weak struct serial_device *default_serial_console(void)
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static int s5p_serial_pending(struct udevice *dev, bool input)
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{
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#ifdef CONFIG_OF_CONTROL
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int index = 0;
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struct s5p_serial_platdata *plat = dev->platdata;
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struct s5p_uart *const uart = plat->reg;
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uint32_t ufstat = readl(&uart->ufstat);
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if ((!config.base_addr) && (fdtdec_decode_console(&index, &config))) {
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debug("Cannot decode default console node\n");
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return NULL;
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}
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switch (config.port_id) {
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case 0:
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return &s5p_serial0_device;
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case 1:
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return &s5p_serial1_device;
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case 2:
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return &s5p_serial2_device;
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case 3:
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return &s5p_serial3_device;
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default:
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debug("Unknown config.port_id: %d", config.port_id);
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break;
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}
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return NULL;
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#else
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config.enabled = 1;
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#if defined(CONFIG_SERIAL0)
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return &s5p_serial0_device;
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#elif defined(CONFIG_SERIAL1)
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return &s5p_serial1_device;
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#elif defined(CONFIG_SERIAL2)
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return &s5p_serial2_device;
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#elif defined(CONFIG_SERIAL3)
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return &s5p_serial3_device;
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#else
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#error "CONFIG_SERIAL? missing."
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#endif
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#endif
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if (input)
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return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
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else
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return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
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}
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void s5p_serial_initialize(void)
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static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
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{
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serial_register(&s5p_serial0_device);
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serial_register(&s5p_serial1_device);
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serial_register(&s5p_serial2_device);
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serial_register(&s5p_serial3_device);
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struct s5p_serial_platdata *plat = dev->platdata;
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fdt_addr_t addr;
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addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->reg = (struct s5p_uart *)addr;
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plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
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return 0;
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}
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static const struct dm_serial_ops s5p_serial_ops = {
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.putc = s5p_serial_putc,
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.pending = s5p_serial_pending,
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.getc = s5p_serial_getc,
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.setbrg = s5p_serial_setbrg,
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};
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static const struct udevice_id s5p_serial_ids[] = {
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{ .compatible = "samsung,exynos4210-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_s5p) = {
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.name = "serial_s5p",
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.id = UCLASS_SERIAL,
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.of_match = s5p_serial_ids,
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.ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
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.probe = s5p_serial_probe,
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.ops = &s5p_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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@ -20,6 +20,7 @@
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#define CONFIG_DM
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#define CONFIG_CMD_DM
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#define CONFIG_DM_GPIO
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#define CONFIG_DM_SERIAL
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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@ -292,5 +292,6 @@
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#define CONFIG_DM
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#define CONFIG_CMD_DM
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#define CONFIG_DM_GPIO
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#define CONFIG_DM_SERIAL
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#endif /* __CONFIG_H */
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@ -227,5 +227,6 @@
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#define CONFIG_DM
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#define CONFIG_CMD_DM
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#define CONFIG_DM_GPIO
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#define CONFIG_DM_SERIAL
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#endif /* __CONFIG_H */
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