mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
Blackfin: bf537-stamp: drop old spi_flash driver
The new common spi framework and spi flash subsystem provides all the same functionality as the old Blackfin-specific driver, so punt the old one as it has been sticking around long enough. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
b30453ace4
commit
7393a09800
2 changed files with 0 additions and 997 deletions
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@ -31,7 +31,6 @@ LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o cmd_bf537led.o
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COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o
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COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
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COBJS-$(CONFIG_POST) += post.o post-memory.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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@ -1,996 +0,0 @@
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/*
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* SPI flash driver
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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/* Configuration options:
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* CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK)
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* CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read
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* WARNING: make sure your SCLK + SPI_BAUD is slow enough
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/mach-common/bits/spi.h>
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#include <asm/mach-common/bits/dma.h>
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/* Forcibly phase out these */
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#ifdef CONFIG_SPI_FLASH_NUM_SECTORS
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# error do not set CONFIG_SPI_FLASH_NUM_SECTORS
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#endif
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#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE
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# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE
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#endif
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#if defined(CONFIG_SPI)
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struct flash_info {
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char *name;
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uint16_t id;
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uint16_t ext_id;
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unsigned sector_size;
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unsigned num_sectors;
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};
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/* SPI Speeds: 50 MHz / 33 MHz */
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static struct flash_info flash_spansion_serial_flash[] = {
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{ "S25FL016", 0x0215, 0, 64 * 1024, 32 },
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{ "S25FL032", 0x0216, 0, 64 * 1024, 64 },
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{ "S25FL064", 0x0217, 0, 64 * 1024, 128 },
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{ "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */
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{ "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */
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{ NULL, 0, 0, 0, 0 }
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};
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/* SPI Speeds: 50 MHz / 20 MHz */
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static struct flash_info flash_st_serial_flash[] = {
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{ "m25p05", 0x2010, 0, 32 * 1024, 2 },
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{ "m25p10", 0x2011, 0, 32 * 1024, 4 },
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{ "m25p20", 0x2012, 0, 64 * 1024, 4 },
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{ "m25p40", 0x2013, 0, 64 * 1024, 8 },
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{ "m25p80", 0x20FF, 0, 64 * 1024, 16 },
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{ "m25p16", 0x2015, 0, 64 * 1024, 32 },
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{ "m25p32", 0x2016, 0, 64 * 1024, 64 },
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{ "m25p64", 0x2017, 0, 64 * 1024, 128 },
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{ "m25p128", 0x2018, 0, 256 * 1024, 64 },
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{ NULL, 0, 0, 0, 0 }
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};
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/* SPI Speeds: 20 MHz / 40 MHz */
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static struct flash_info flash_sst_serial_flash[] = {
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{ "SST25WF512", 0x2501, 0, 4 * 1024, 128 },
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{ "SST25WF010", 0x2502, 0, 4 * 1024, 256 },
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{ "SST25WF020", 0x2503, 0, 4 * 1024, 512 },
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{ "SST25WF040", 0x2504, 0, 4 * 1024, 1024 },
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{ NULL, 0, 0, 0, 0 }
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};
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/* SPI Speeds: 66 MHz / 33 MHz */
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static struct flash_info flash_atmel_dataflash[] = {
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{ "AT45DB011x", 0x0c, 0, 264, 512 },
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{ "AT45DB021x", 0x14, 0, 264, 1025 },
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{ "AT45DB041x", 0x1c, 0, 264, 2048 },
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{ "AT45DB081x", 0x24, 0, 264, 4096 },
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{ "AT45DB161x", 0x2c, 0, 528, 4096 },
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{ "AT45DB321x", 0x34, 0, 528, 8192 },
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{ "AT45DB642x", 0x3c, 0, 1056, 8192 },
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{ NULL, 0, 0, 0, 0 }
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};
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/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */
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static struct flash_info flash_winbond_serial_flash[] = {
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{ "W25X10", 0x3011, 0, 16 * 256, 32 },
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{ "W25X20", 0x3012, 0, 16 * 256, 64 },
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{ "W25X40", 0x3013, 0, 16 * 256, 128 },
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{ "W25X80", 0x3014, 0, 16 * 256, 256 },
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{ "W25P80", 0x2014, 0, 256 * 256, 16 },
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{ "W25P16", 0x2015, 0, 256 * 256, 32 },
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{ NULL, 0, 0, 0, 0 }
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};
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struct flash_ops {
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uint8_t read, write, erase, status;
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};
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#ifdef CONFIG_SPI_FLASH_SLOW_READ
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# define OP_READ 0x03
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#else
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# define OP_READ 0x0B
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#endif
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static struct flash_ops flash_st_ops = {
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.read = OP_READ,
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.write = 0x02,
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.erase = 0xD8,
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.status = 0x05,
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};
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static struct flash_ops flash_sst_ops = {
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.read = OP_READ,
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.write = 0x02,
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.erase = 0x20,
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.status = 0x05,
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};
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static struct flash_ops flash_atmel_ops = {
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.read = OP_READ,
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.write = 0x82,
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.erase = 0x81,
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.status = 0xD7,
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};
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static struct flash_ops flash_winbond_ops = {
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.read = OP_READ,
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.write = 0x02,
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.erase = 0x20,
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.status = 0x05,
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};
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struct manufacturer_info {
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const char *name;
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uint8_t id;
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struct flash_info *flashes;
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struct flash_ops *ops;
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};
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static struct {
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struct manufacturer_info *manufacturer;
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struct flash_info *flash;
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struct flash_ops *ops;
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uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2;
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unsigned int write_length;
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unsigned long sector_size, num_sectors;
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} flash;
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enum {
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JED_MANU_SPANSION = 0x01,
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JED_MANU_ST = 0x20,
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JED_MANU_SST = 0xBF,
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JED_MANU_ATMEL = 0x1F,
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JED_MANU_WINBOND = 0xEF,
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};
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static struct manufacturer_info flash_manufacturers[] = {
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{
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.name = "Spansion",
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.id = JED_MANU_SPANSION,
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.flashes = flash_spansion_serial_flash,
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.ops = &flash_st_ops,
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},
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{
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.name = "ST",
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.id = JED_MANU_ST,
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.flashes = flash_st_serial_flash,
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.ops = &flash_st_ops,
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},
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{
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.name = "SST",
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.id = JED_MANU_SST,
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.flashes = flash_sst_serial_flash,
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.ops = &flash_sst_ops,
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},
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{
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.name = "Atmel",
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.id = JED_MANU_ATMEL,
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.flashes = flash_atmel_dataflash,
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.ops = &flash_atmel_ops,
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},
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{
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.name = "Winbond",
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.id = JED_MANU_WINBOND,
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.flashes = flash_winbond_serial_flash,
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.ops = &flash_winbond_ops,
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},
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};
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#define TIMEOUT 5000 /* timeout of 5 seconds */
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/* If part has multiple SPI flashes, assume SPI0 as that is
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* the one we can boot off of ...
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*/
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#ifndef pSPI_CTL
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# define pSPI_CTL pSPI0_CTL
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# define pSPI_BAUD pSPI0_BAUD
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# define pSPI_FLG pSPI0_FLG
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# define pSPI_RDBR pSPI0_RDBR
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# define pSPI_STAT pSPI0_STAT
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# define pSPI_TDBR pSPI0_TDBR
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#endif
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/* Default to the SPI SSEL that we boot off of:
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* BF54x, BF537, (everything new?): SSEL1
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* BF51x, BF533, BF561: SSEL2
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*/
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#ifndef CONFIG_SPI_FLASH_SSEL
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# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL
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#endif
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#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL)
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static void SPI_INIT(void)
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{
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/* [#3541] This delay appears to be necessary, but not sure
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* exactly why as the history behind it is non-existant.
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*/
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*pSPI_CTL = 0;
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udelay(CONFIG_CCLK_HZ / 25000000);
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/* enable SPI pins: SSEL, MOSI, MISO, SCK */
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#ifdef __ADSPBF54x__
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*pPORTE_FER |= (PE0 | PE1 | PE2 | PE4);
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#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
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*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
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#elif defined(__ADSPBF52x__)
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bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3);
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bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4);
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#elif defined(__ADSPBF51x__)
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bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1);
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bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15);
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#endif
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/* initate communication upon write of TDBR */
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*pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
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*pSPI_BAUD = CONFIG_SPI_BAUD;
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}
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static void SPI_DEINIT(void)
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{
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*pSPI_CTL = 0;
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*pSPI_BAUD = 0;
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SSYNC();
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}
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static void SPI_ON(void)
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{
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/* toggle SSEL to reset the device so it'll take a new command */
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*pSPI_FLG = 0xFF00 | SSEL_MASK;
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SSYNC();
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*pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK;
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SSYNC();
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}
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static void SPI_OFF(void)
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{
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/* put SPI settings back to reset state */
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*pSPI_FLG = 0xFF00;
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SSYNC();
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}
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static uint8_t spi_write_read_byte(uint8_t transmit)
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{
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*pSPI_TDBR = transmit;
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SSYNC();
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while ((*pSPI_STAT & TXS))
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if (ctrlc())
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break;
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while (!(*pSPI_STAT & SPIF))
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if (ctrlc())
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break;
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while (!(*pSPI_STAT & RXS))
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if (ctrlc())
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break;
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/* Read dummy to empty the receive register */
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return *pSPI_RDBR;
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}
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static uint8_t read_status_register(void)
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{
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uint8_t status_register;
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/* send instruction to read status register */
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SPI_ON();
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spi_write_read_byte(flash.ops->status);
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/* send dummy to receive the status register */
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status_register = spi_write_read_byte(0);
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SPI_OFF();
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return status_register;
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}
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static int wait_for_ready_status(void)
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{
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ulong start = get_timer(0);
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while (get_timer(0) - start < TIMEOUT) {
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switch (flash.manufacturer_id) {
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case JED_MANU_SPANSION:
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case JED_MANU_ST:
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case JED_MANU_SST:
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case JED_MANU_WINBOND:
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if (!(read_status_register() & 0x01))
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return 0;
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break;
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case JED_MANU_ATMEL:
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if (read_status_register() & 0x80)
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return 0;
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break;
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}
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if (ctrlc()) {
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puts("\nAbort\n");
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return -1;
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}
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}
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puts("Timeout\n");
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return -1;
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}
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static int enable_writing(void)
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{
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ulong start;
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if (flash.manufacturer_id == JED_MANU_ATMEL)
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return 0;
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/* A write enable instruction must previously have been executed */
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SPI_ON();
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spi_write_read_byte(0x06);
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SPI_OFF();
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/* The status register will be polled to check the write enable latch "WREN" */
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start = get_timer(0);
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while (get_timer(0) - start < TIMEOUT) {
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if (read_status_register() & 0x02)
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return 0;
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if (ctrlc()) {
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puts("\nAbort\n");
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return -1;
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}
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}
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puts("Timeout\n");
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return -1;
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}
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static void write_status_register(uint8_t val)
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{
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if (flash.manufacturer_id != JED_MANU_SST)
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hang();
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if (enable_writing())
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return;
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/* send instruction to write status register */
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SPI_ON();
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spi_write_read_byte(0x01);
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/* and clear it! */
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spi_write_read_byte(val);
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SPI_OFF();
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}
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/* Request and read the manufacturer and device id of parts which
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* are compatible with the JEDEC standard (JEP106) and use that to
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* setup other operating conditions.
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*/
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static int spi_detect_part(void)
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{
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uint16_t dev_id, dev_extid;
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size_t i;
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static char called_init;
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if (called_init)
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return 0;
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#ifdef CONFIG_SPI_FLASH_M25P80
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flash.manufacturer_id = JED_MANU_ST;
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flash.device_id1 = 0x20;
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flash.device_id2 = 0xFF;
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#else
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SPI_ON();
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/* Send the request for the part identification */
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spi_write_read_byte(0x9F);
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/* Now read in the manufacturer id bytes */
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do {
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flash.manufacturer_id = spi_write_read_byte(0);
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if (flash.manufacturer_id == 0x7F)
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puts("Warning: unhandled manufacturer continuation byte!\n");
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} while (flash.manufacturer_id == 0x7F);
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/* Now read in the first device id byte */
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flash.device_id1 = spi_write_read_byte(0);
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/* Now read in the second device id byte */
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flash.device_id2 = spi_write_read_byte(0);
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/* Read extended device ids */
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flash.device_extid1 = spi_write_read_byte(0);
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flash.device_extid2 = spi_write_read_byte(0);
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SPI_OFF();
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#endif
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dev_id = (flash.device_id1 << 8) | flash.device_id2;
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dev_extid = (flash.device_extid1 << 8) | flash.device_extid2;
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for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) {
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if (flash.manufacturer_id == flash_manufacturers[i].id)
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break;
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}
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if (i == ARRAY_SIZE(flash_manufacturers))
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goto unknown;
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flash.manufacturer = &flash_manufacturers[i];
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flash.ops = flash_manufacturers[i].ops;
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switch (flash.manufacturer_id) {
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case JED_MANU_SPANSION:
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case JED_MANU_ST:
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case JED_MANU_SST:
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case JED_MANU_WINBOND:
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for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
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if (dev_id == flash.manufacturer->flashes[i].id &&
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(flash.manufacturer->flashes[i].ext_id == 0 ||
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flash.manufacturer->flashes[i].ext_id == dev_extid))
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break;
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}
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if (!flash.manufacturer->flashes[i].name)
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goto unknown;
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flash.flash = &flash.manufacturer->flashes[i];
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flash.sector_size = flash.flash->sector_size;
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flash.num_sectors = flash.flash->num_sectors;
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if (flash.manufacturer_id == JED_MANU_SST)
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flash.write_length = 1; /* pwnt :( */
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else
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flash.write_length = 256;
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break;
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case JED_MANU_ATMEL: {
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uint8_t status = read_status_register();
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|
||||
for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
|
||||
if ((status & 0x3c) == flash.manufacturer->flashes[i].id)
|
||||
break;
|
||||
}
|
||||
if (!flash.manufacturer->flashes[i].name)
|
||||
goto unknown;
|
||||
|
||||
flash.flash = &flash.manufacturer->flashes[i];
|
||||
flash.sector_size = flash.flash->sector_size;
|
||||
flash.num_sectors = flash.flash->num_sectors;
|
||||
|
||||
/* see if flash is in "power of 2" mode */
|
||||
if (status & 0x1)
|
||||
flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1));
|
||||
|
||||
flash.write_length = flash.sector_size;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* the SST parts power up with software protection enabled by default */
|
||||
if (flash.manufacturer_id == JED_MANU_SST)
|
||||
write_status_register(0);
|
||||
|
||||
called_init = 1;
|
||||
return 0;
|
||||
|
||||
unknown:
|
||||
printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n",
|
||||
flash.manufacturer_id, flash.device_id1, flash.device_id2);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_init_f
|
||||
* Description: Init SPI-Controller (ROM part)
|
||||
* return: ---
|
||||
*/
|
||||
void spi_init_f(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_init_r
|
||||
* Description: Init SPI-Controller (RAM part) -
|
||||
* The malloc engine is ready and we can move our buffers to
|
||||
* normal RAM
|
||||
* return: ---
|
||||
*/
|
||||
void spi_init_r(void)
|
||||
{
|
||||
#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI)
|
||||
/* Our testing strategy here is pretty basic:
|
||||
* - fill src memory with an 8-bit pattern
|
||||
* - write the src memory to the SPI flash
|
||||
* - read the SPI flash into the dst memory
|
||||
* - compare src and dst memory regions
|
||||
* - repeat a few times
|
||||
* The variations we test for:
|
||||
* - change the 8-bit pattern a bit
|
||||
* - change the read/write block size so we know:
|
||||
* - writes smaller/equal/larger than the buffer work
|
||||
* - writes smaller/equal/larger than the sector work
|
||||
* - change the SPI offsets so we know:
|
||||
* - writing partial sectors works
|
||||
*/
|
||||
uint8_t *mem_src, *mem_dst;
|
||||
size_t i, c, l, o;
|
||||
size_t test_count, errors;
|
||||
uint8_t pattern;
|
||||
|
||||
SPI_INIT();
|
||||
|
||||
if (spi_detect_part())
|
||||
goto out;
|
||||
eeprom_info();
|
||||
|
||||
ulong lengths[] = {
|
||||
flash.write_length,
|
||||
flash.write_length * 2,
|
||||
flash.write_length / 2,
|
||||
flash.sector_size,
|
||||
flash.sector_size * 2,
|
||||
flash.sector_size / 2
|
||||
};
|
||||
ulong offsets[] = {
|
||||
0,
|
||||
flash.write_length,
|
||||
flash.write_length * 2,
|
||||
flash.write_length / 2,
|
||||
flash.write_length / 4,
|
||||
flash.sector_size,
|
||||
flash.sector_size * 2,
|
||||
flash.sector_size / 2,
|
||||
flash.sector_size / 4,
|
||||
};
|
||||
|
||||
/* the exact addresses are arbitrary ... they just need to not overlap */
|
||||
mem_src = (void *)(0);
|
||||
mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2);
|
||||
|
||||
test_count = 0;
|
||||
errors = 0;
|
||||
pattern = 0x00;
|
||||
|
||||
for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */
|
||||
for (l = 0; l < ARRAY_SIZE(lengths); ++l) {
|
||||
for (o = 0; o < ARRAY_SIZE(offsets); ++o) {
|
||||
ulong len = lengths[l];
|
||||
ulong off = offsets[o];
|
||||
|
||||
printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off);
|
||||
|
||||
/* setup the source memory region */
|
||||
memset(mem_src, pattern, len);
|
||||
|
||||
test_count += 4;
|
||||
for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* make sure background fill pattern != pattern */
|
||||
memset(mem_dst, pattern ^ 0xFF, len);
|
||||
|
||||
/* write out the source memory and then read it back and compare */
|
||||
eeprom_write(0, off, mem_src, len);
|
||||
eeprom_read(0, off, mem_dst, len);
|
||||
|
||||
if (memcmp(mem_src, mem_dst, len)) {
|
||||
for (c = 0; c < len; ++c)
|
||||
if (mem_src[c] != mem_dst[c])
|
||||
break;
|
||||
printf(" FAIL @ offset %u, skipping repeats ", c);
|
||||
++errors;
|
||||
break;
|
||||
}
|
||||
|
||||
/* XXX: should shrink write region here to test with
|
||||
* leading/trailing canaries so we know surrounding
|
||||
* bytes don't get screwed.
|
||||
*/
|
||||
}
|
||||
puts("\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* invert the pattern every other run and shift out bits slowly */
|
||||
pattern ^= 0xFF;
|
||||
if (i % 2)
|
||||
pattern = (pattern | 0x01) << 1;
|
||||
}
|
||||
|
||||
if (errors)
|
||||
printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors);
|
||||
else
|
||||
printf("SPI PASS: %i tests worked!\n", test_count);
|
||||
|
||||
out:
|
||||
SPI_DEINIT();
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static void transmit_address(uint32_t addr)
|
||||
{
|
||||
/* Send the highest byte of the 24 bit address at first */
|
||||
spi_write_read_byte(addr >> 16);
|
||||
/* Send the middle byte of the 24 bit address at second */
|
||||
spi_write_read_byte(addr >> 8);
|
||||
/* Send the lowest byte of the 24 bit address finally */
|
||||
spi_write_read_byte(addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a value from flash for verify purpose
|
||||
* Inputs: unsigned long ulStart - holds the SPI start address
|
||||
* int pnData - pointer to store value read from flash
|
||||
* long lCount - number of elements to read
|
||||
*/
|
||||
#ifdef CONFIG_SPI_READFLASH_NODMA
|
||||
static int read_flash(unsigned long address, long count, uchar *buffer)
|
||||
{
|
||||
size_t i, j;
|
||||
|
||||
/* Send the read command to SPI device */
|
||||
SPI_ON();
|
||||
spi_write_read_byte(flash.ops->read);
|
||||
transmit_address(address);
|
||||
|
||||
#ifndef CONFIG_SPI_FLASH_SLOW_READ
|
||||
/* Send dummy byte when doing SPI fast reads */
|
||||
spi_write_read_byte(0);
|
||||
#endif
|
||||
|
||||
/* After the SPI device address has been placed on the MOSI pin the data can be */
|
||||
/* received on the MISO pin. */
|
||||
j = flash.sector_size << 1;
|
||||
for (i = 1; i <= count; ++i) {
|
||||
*buffer++ = spi_write_read_byte(0);
|
||||
if (!j--) {
|
||||
puts(".");
|
||||
j = flash.sector_size;
|
||||
}
|
||||
}
|
||||
|
||||
SPI_OFF();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
|
||||
#ifdef __ADSPBF54x__
|
||||
#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS
|
||||
#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS
|
||||
#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR
|
||||
#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG
|
||||
#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
|
||||
defined(__ADSPBF538__) || defined(__ADSPBF539__)
|
||||
#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS
|
||||
#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS
|
||||
#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR
|
||||
#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG
|
||||
#elif defined(__ADSPBF561__)
|
||||
#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS
|
||||
#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS
|
||||
#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR
|
||||
#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG
|
||||
#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
|
||||
defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
|
||||
#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS
|
||||
#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS
|
||||
#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR
|
||||
#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG
|
||||
#else
|
||||
#error "Please provide SPI DMA channel defines"
|
||||
#endif
|
||||
|
||||
struct dmadesc_array {
|
||||
unsigned long start_addr;
|
||||
unsigned short cfg;
|
||||
unsigned short x_count;
|
||||
short x_modify;
|
||||
unsigned short y_count;
|
||||
short y_modify;
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Read a value from flash for verify purpose
|
||||
* Inputs: unsigned long ulStart - holds the SPI start address
|
||||
* int pnData - pointer to store value read from flash
|
||||
* long lCount - number of elements to read
|
||||
*/
|
||||
|
||||
static int read_flash(unsigned long address, long count, uchar *buffer)
|
||||
{
|
||||
unsigned int ndsize;
|
||||
struct dmadesc_array dma[2];
|
||||
/* Send the read command to SPI device */
|
||||
|
||||
if (!count)
|
||||
return 0;
|
||||
|
||||
dma[0].start_addr = (unsigned long)buffer;
|
||||
dma[0].x_modify = 1;
|
||||
if (count <= 65536) {
|
||||
blackfin_dcache_flush_invalidate_range(buffer, buffer + count);
|
||||
ndsize = NDSIZE_5;
|
||||
dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
|
||||
dma[0].x_count = count;
|
||||
} else {
|
||||
blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1);
|
||||
ndsize = NDSIZE_7;
|
||||
dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D;
|
||||
dma[0].x_count = 0; /* 2^16 */
|
||||
dma[0].y_count = count >> 16; /* count / 2^16 */
|
||||
dma[0].y_modify = 1;
|
||||
dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF));
|
||||
dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
|
||||
dma[1].x_count = count & 0xFFFF; /* count % 2^16 */
|
||||
dma[1].x_modify = 1;
|
||||
}
|
||||
|
||||
bfin_write_DMA_SPI_CONFIG(0);
|
||||
bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
bfin_write_DMA_SPI_CURR_DESC_PTR(dma);
|
||||
|
||||
SPI_ON();
|
||||
|
||||
spi_write_read_byte(flash.ops->read);
|
||||
transmit_address(address);
|
||||
|
||||
#ifndef CONFIG_SPI_FLASH_SLOW_READ
|
||||
/* Send dummy byte when doing SPI fast reads */
|
||||
spi_write_read_byte(0);
|
||||
#endif
|
||||
|
||||
bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN);
|
||||
*pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ);
|
||||
SSYNC();
|
||||
|
||||
/*
|
||||
* We already invalidated the first 64k,
|
||||
* now while we just wait invalidate the remaining part.
|
||||
* Its not likely that the DMA is going to overtake
|
||||
*/
|
||||
if (count > 65536)
|
||||
blackfin_dcache_flush_invalidate_range(buffer + 65536,
|
||||
buffer + count);
|
||||
|
||||
while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE))
|
||||
if (ctrlc())
|
||||
break;
|
||||
|
||||
SPI_OFF();
|
||||
|
||||
*pSPI_CTL = 0;
|
||||
|
||||
bfin_write_DMA_SPI_CONFIG(0);
|
||||
|
||||
*pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static long address_to_sector(unsigned long address)
|
||||
{
|
||||
if (address > (flash.num_sectors * flash.sector_size) - 1)
|
||||
return -1;
|
||||
return address / flash.sector_size;
|
||||
}
|
||||
|
||||
static int erase_sector(int address)
|
||||
{
|
||||
/* sector gets checked in higher function, so assume it's valid
|
||||
* here and figure out the offset of the sector in flash
|
||||
*/
|
||||
if (enable_writing())
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Send the erase block command to the flash followed by the 24 address
|
||||
* to point to the start of a sector
|
||||
*/
|
||||
SPI_ON();
|
||||
spi_write_read_byte(flash.ops->erase);
|
||||
transmit_address(address);
|
||||
SPI_OFF();
|
||||
|
||||
return wait_for_ready_status();
|
||||
}
|
||||
|
||||
/* Write [count] bytes out of [buffer] into the given SPI [address] */
|
||||
static long write_flash(unsigned long address, long count, uchar *buffer)
|
||||
{
|
||||
long i, write_buffer_size;
|
||||
|
||||
if (enable_writing())
|
||||
return -1;
|
||||
|
||||
/* Send write command followed by the 24 bit address */
|
||||
SPI_ON();
|
||||
spi_write_read_byte(flash.ops->write);
|
||||
transmit_address(address);
|
||||
|
||||
/* Shoot out a single write buffer */
|
||||
write_buffer_size = min(count, flash.write_length);
|
||||
for (i = 0; i < write_buffer_size; ++i)
|
||||
spi_write_read_byte(buffer[i]);
|
||||
|
||||
SPI_OFF();
|
||||
|
||||
/* Wait for the flash to do its thing */
|
||||
if (wait_for_ready_status()) {
|
||||
puts("SPI Program Time out! ");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Write [count] bytes out of [buffer] into the given SPI [address] */
|
||||
static int write_sector(unsigned long address, long count, uchar *buffer)
|
||||
{
|
||||
long write_cnt;
|
||||
|
||||
while (count != 0) {
|
||||
write_cnt = write_flash(address, count, buffer);
|
||||
if (write_cnt == -1)
|
||||
return -1;
|
||||
|
||||
/* Now that we've sent some bytes out to the flash, update
|
||||
* our counters a bit
|
||||
*/
|
||||
count -= write_cnt;
|
||||
address += write_cnt;
|
||||
buffer += write_cnt;
|
||||
}
|
||||
|
||||
/* return the appropriate error code */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_write
|
||||
*/
|
||||
ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
unsigned long offset;
|
||||
int start_sector, end_sector;
|
||||
int start_byte, end_byte;
|
||||
uchar *temp = NULL;
|
||||
int num, ret = 0;
|
||||
|
||||
SPI_INIT();
|
||||
|
||||
if (spi_detect_part())
|
||||
goto out;
|
||||
|
||||
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
|
||||
|
||||
/* Get the start block number */
|
||||
start_sector = address_to_sector(offset);
|
||||
if (start_sector == -1) {
|
||||
puts("Invalid sector! ");
|
||||
goto out;
|
||||
}
|
||||
end_sector = address_to_sector(offset + len - 1);
|
||||
if (end_sector == -1) {
|
||||
puts("Invalid sector! ");
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Since flashes operate in sector units but the eeprom command
|
||||
* operates as a continuous stream of bytes, we need to emulate
|
||||
* the eeprom behavior. So here we read in the sector, overlay
|
||||
* any bytes we're actually modifying, erase the sector, and
|
||||
* then write back out the new sector.
|
||||
*/
|
||||
temp = malloc(flash.sector_size);
|
||||
if (!temp) {
|
||||
puts("Malloc for sector failed! ");
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (num = start_sector; num <= end_sector; num++) {
|
||||
unsigned long address = num * flash.sector_size;
|
||||
|
||||
/* XXX: should add an optimization when spanning sectors:
|
||||
* No point in reading in a sector if we're going to be
|
||||
* clobbering the whole thing. Need to also add a test
|
||||
* case to make sure the optimization is correct.
|
||||
*/
|
||||
if (read_flash(address, flash.sector_size, temp)) {
|
||||
puts("Read sector failed! ");
|
||||
len = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
start_byte = max(address, offset);
|
||||
end_byte = address + flash.sector_size - 1;
|
||||
if (end_byte > (offset + len))
|
||||
end_byte = (offset + len - 1);
|
||||
|
||||
memcpy(temp + start_byte - address,
|
||||
buffer + start_byte - offset,
|
||||
end_byte - start_byte + 1);
|
||||
|
||||
if (erase_sector(address)) {
|
||||
puts("Erase sector failed! ");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (write_sector(address, flash.sector_size, temp)) {
|
||||
puts("Write sector failed! ");
|
||||
goto out;
|
||||
}
|
||||
|
||||
puts(".");
|
||||
}
|
||||
|
||||
ret = len;
|
||||
|
||||
out:
|
||||
free(temp);
|
||||
|
||||
SPI_DEINIT();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function: spi_read
|
||||
*/
|
||||
ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
unsigned long offset;
|
||||
|
||||
SPI_INIT();
|
||||
|
||||
if (spi_detect_part())
|
||||
len = 0;
|
||||
else {
|
||||
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
|
||||
read_flash(offset, len, buffer);
|
||||
}
|
||||
|
||||
SPI_DEINIT();
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/*
|
||||
* Spit out some useful information about the SPI eeprom
|
||||
*/
|
||||
int eeprom_info(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
SPI_INIT();
|
||||
|
||||
if (spi_detect_part())
|
||||
ret = 1;
|
||||
else
|
||||
printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
|
||||
"Parameters: num sectors = %lu, sector size = %lu, write size = %i\n"
|
||||
"Flash Size: %lu mbit (%lu mbyte)\n"
|
||||
"Status: 0x%02X\n",
|
||||
flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
|
||||
flash.device_id1, flash.device_id2, flash.num_sectors,
|
||||
flash.sector_size, flash.write_length,
|
||||
(flash.num_sectors * flash.sector_size) >> 17,
|
||||
(flash.num_sectors * flash.sector_size) >> 20,
|
||||
read_status_register());
|
||||
|
||||
SPI_DEINIT();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue