mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
Merge with git://www.denx.de/git/u-boot.git
This commit is contained in:
commit
72c5e39c83
5 changed files with 29 additions and 15 deletions
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@ -120,10 +120,12 @@ SECTIONS
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_edata = .;
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_edata = .;
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PROVIDE (edata = .);
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PROVIDE (edata = .);
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. = .;
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__u_boot_cmd_start = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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__u_boot_cmd_end = .;
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. = .;
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__start___ex_table = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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__stop___ex_table = .;
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@ -80,6 +80,26 @@ int interrupt_init(void)
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{
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{
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int ret;
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int ret;
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/*
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* The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
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* implement PEX10 errata. As INT is active high, it
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* will cause core to take 0x500 interrupt.
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*
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* Due to the PIC's default pass through mode, as soon
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* as interrupts are enabled (MSR[EE] = 1), an interrupt
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* will be taken and u-boot will hang. This is due to a
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* hardware change (per an errata fix) on new revisions
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* of the board with Rev 2.x parts.
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*
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* Setting the PIC to mixed mode prevents the hang.
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*/
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if ((get_svr() & 0xf0) == 0x20) {
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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immr->im_pic.gcr = MPC86xx_PICGCR_RST;
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while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
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immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
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}
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/* call cpu specific function from $(CPU)/interrupts.c */
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/* call cpu specific function from $(CPU)/interrupts.c */
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ret = interrupt_init_cpu(&decrementer_count);
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ret = interrupt_init_cpu(&decrementer_count);
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@ -284,9 +284,9 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
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}
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}
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/*
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/*
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* Adjust DDR II IO voltage biasing. It just makes it work.
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* Adjust DDR II IO voltage biasing. Rev1 only
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*/
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*/
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if (spd.mem_type == SPD_MEMTYPE_DDR2) {
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if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) {
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gur->ddrioovcr = (0
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gur->ddrioovcr = (0
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| 0x80000000 /* Enable */
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| 0x80000000 /* Enable */
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| 0x10000000 /* VSEL to 1.8V */
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| 0x10000000 /* VSEL to 1.8V */
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@ -721,6 +721,8 @@ typedef struct ccsr_pic {
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uint frr; /* 0x41000 - Feature Reporting Register */
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uint frr; /* 0x41000 - Feature Reporting Register */
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char res10[28];
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char res10[28];
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uint gcr; /* 0x41020 - Global Configuration Register */
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uint gcr; /* 0x41020 - Global Configuration Register */
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#define MPC86xx_PICGCR_RST 0x80000000
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#define MPC86xx_PICGCR_MODE 0x20000000
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char res11[92];
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char res11[92];
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uint vir; /* 0x41080 - Vendor Identification Register */
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uint vir; /* 0x41080 - Vendor Identification Register */
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char res12[12];
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char res12[12];
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@ -212,7 +212,6 @@
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#endif
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#endif
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#if defined(CFG_RAMBOOT)
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#if defined(CFG_RAMBOOT)
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#undef CFG_FLASH_CFI_DRIVER
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#undef CONFIG_SPD_EEPROM
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#undef CONFIG_SPD_EEPROM
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#define CFG_SDRAM_SIZE 256
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#define CFG_SDRAM_SIZE 256
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#endif
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#endif
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@ -468,7 +467,6 @@
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#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CFG_ENV_SIZE 0x2000
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#define CFG_ENV_SIZE 0x2000
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#else
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#else
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#define CFG_NO_FLASH 1 /* Flash is not usable now */
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_SIZE 0x2000
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#define CFG_ENV_SIZE 0x2000
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@ -486,21 +484,13 @@
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| CFG_CMD_SCSI \
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| CFG_CMD_SCSI \
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| CFG_CMD_EXT2) \
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| CFG_CMD_EXT2) \
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& \
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& \
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~(CFG_CMD_ENV \
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~(CFG_CMD_ENV))
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| CFG_CMD_IMLS \
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| CFG_CMD_FLASH \
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| CFG_CMD_LOADS))
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#else
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#else
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
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| CFG_CMD_PING \
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| CFG_CMD_PING \
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| CFG_CMD_I2C \
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| CFG_CMD_I2C) \
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| CFG_CMD_SCSI \
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| CGF_CMD_EXT2) \
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& \
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& \
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~(CFG_CMD_ENV \
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~(CFG_CMD_ENV))
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| CFG_CMD_IMLS \
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| CFG_CMD_FLASH \
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| CFG_CMD_LOADS))
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#endif
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#endif
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#else
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#else
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#if defined(CONFIG_PCI)
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#if defined(CONFIG_PCI)
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