mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
spieval: Remove remainders of dead board
Commit 69434e4c deleted spieval board support
but it missed to clean up include/configs/spieval.h file.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
0e53691529
commit
72b97e4bc9
1 changed files with 0 additions and 494 deletions
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@ -1,494 +0,0 @@
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/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2005
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
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#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
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#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
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#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#ifdef CONFIG_STK52XX
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#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
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#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
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#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
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#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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#define CONFIG_BOARD_EARLY_INIT_R
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#endif /* CONFIG_STK52XX */
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#ifdef CONFIG_STK52XX
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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/* #define CONFIG_PCI_SCAN_SHOW 1 */
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_EEPRO100 1
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_NS8382X 1
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#endif /* CONFIG_STK52XX */
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/*
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* Video console
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*/
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#if 1
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_SM501
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#define CONFIG_VIDEO_SM501_32BPP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/* USB */
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#ifdef CONFIG_STK52XX
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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#endif
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_I2C)
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SNTP
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#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#endif
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#ifdef CONFIG_STK52XX
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_FAT
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#endif
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#endif
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#ifdef CONFIG_POST
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#define CONFIG_CMD_DIAG
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#endif
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#define CONFIG_TIMESTAMP /* display image timestamps */
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#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
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# define CONFIG_SYS_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"bootfile=/tftpboot/tqm5200/uImage\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
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"update=protect off FC000000 FC05FFFF;" \
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"erase FC000000 FC05FFFF;" \
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"cp.b 200000 FC000000 ${filesize};" \
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"protect on FC000000 FC05FFFF\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
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/*
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* PCI Bus clocking configuration
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*
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* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
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* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
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* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
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*/
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#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#ifdef CONFIG_TQM5200_REV100
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#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
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#else
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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#endif
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/*
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* I2C clock frequency
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*
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* Please notice, that the resulting clock frequency could differ from the
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* configured value. This is because the I2C clock is derived from system
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* clock over a frequency divider with only a few divider values. U-boot
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* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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* approximation allways lies below the configured value, never above.
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*/
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
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* also). For other EEPROMs configuration should be verified. On Mini-FAP the
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* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
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* same configuration could be used.
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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/*
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* HW-Monitor configuration on Mini-FAP
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*/
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#if defined (CONFIG_MINIFAP)
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#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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#endif
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/* List of I2C addresses to be verified by POST */
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#if defined (CONFIG_MINIFAP)
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#undef CONFIG_SYS_POST_I2C_ADDRS
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#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
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CONFIG_SYS_I2C_HWMON_ADDR, \
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CONFIG_SYS_I2C_SLAVE}
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#endif
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
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/* use CFI flash driver if no module variant is spezified */
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
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#if !defined(CONFIG_SYS_LOWBOOT)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
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#else /* CONFIG_SYS_LOWBOOT */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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#endif /* CONFIG_SYS_LOWBOOT */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
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(= chip selects) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use ON-Chip SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
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#else
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#endif
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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/*
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* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
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*/
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/* #define CONFIG_FEC_10MBIT 1 */
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#define CONFIG_PHY_ADDR 0x00
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/*
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* GPIO configuration
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*
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* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
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* Bit 0 (mask: 0x80000000): 1
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* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
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* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
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* Use for REV200 STK52XX boards. Do not use with REV100 modules
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* (because, there I2C1 is used as I2C bus)
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* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
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* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
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* 000 -> All PSC2 pins are GIOPs
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* 001 -> CAN1/2 on PSC2 pins
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* Use for REV100 STK52xx boards
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* use PSC6:
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* on STK52xx:
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* use as UART. Pins PSC6_0 to PSC6_3 are used.
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* Bits 9:11 (mask: 0x00700000):
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* 101 -> PSC6 : Extended POST test is not available
|
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* on MINI-FAP and TQM5200_IB:
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* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
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* 000 -> PSC6 could not be used as UART, CODEC or IrDA
|
||||
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
|
||||
* tests.
|
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*/
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||||
#if defined (CONFIG_MINIFAP)
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||||
# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
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||||
#elif defined (CONFIG_STK52XX)
|
||||
# if defined (CONFIG_STK52XX_REV100)
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||||
# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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# else /* STK52xx REV200 and above */
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||||
# if defined (CONFIG_TQM5200_REV100)
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# error TQM5200 REV100 not supported on STK52XX REV200 or above
|
||||
# else/* TQM5200 REV200 and above */
|
||||
# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004
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# endif
|
||||
# endif
|
||||
#else /* TMQ5200 Inbetriebnahme-Board */
|
||||
# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable loopw command.
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
|
||||
#else
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
|
||||
#endif
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
|
||||
/*
|
||||
* SRAM - Do not map below 2 GB in address space, because this area is used
|
||||
* for SDRAM autosizing.
|
||||
*/
|
||||
#define CONFIG_SYS_CS2_START 0xE5000000
|
||||
#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
|
||||
#define CONFIG_SYS_CS2_CFG 0x0004D930
|
||||
|
||||
/*
|
||||
* Grafic controller - Do not map below 2 GB in address space, because this
|
||||
* area is used for SDRAM autosizing.
|
||||
*/
|
||||
#define SM501_FB_BASE 0xE0000000
|
||||
#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
|
||||
#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
|
||||
#define CONFIG_SYS_CS1_CFG 0x8F48FF70
|
||||
#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_USB_CLOCK 0x0001BBBB
|
||||
#define CONFIG_USB_CONFIG 0x00001000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */
|
||||
#define CONFIG_IDE_PREINIT
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
|
||||
|
||||
/* Interval between registers */
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue