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https://github.com/AsahiLinux/u-boot
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Patch by Tom Guilliams, 20 Jun 2003:
added CONFIG_750FX support for IBM 750FX processors
This commit is contained in:
wdenk
parent
0332990b85
commit
72755c7137
7 changed files with 176 additions and 15 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 0.3.1:
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======================================================================
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* Patch by Tom Guilliams, 20 Jun 2003:
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added CONFIG_750FX support for IBM 750FX processors
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* Patch by Devin Crumb, 02 Apr 2003:
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Fix clock divider rounding problem in drivers/serial.c
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1
README
1
README
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@ -301,6 +301,7 @@ The following options need to be configured:
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or CONFIG_405GP
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or CONFIG_440
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or CONFIG_MPC74xx
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or CONFIG_750FX
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ARM based CPUs:
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---------------
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@ -64,7 +64,7 @@ get_cpu_type(void)
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case 0x0008:
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type = CPU_750;
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if (((pvr >> 8) & 0xff) == 0x01) {
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if (((pvr >> 8) & 0xff) == 0x01) {
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type = CPU_750CX; /* old CX (80100 and 8010x?)*/
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} else if (((pvr >> 8) & 0xff) == 0x22) {
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type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
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@ -72,14 +72,18 @@ get_cpu_type(void)
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type = CPU_750CX; /* CXe (83311) */
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} else if (((pvr >> 12) & 0xF) == 0x3) {
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type = CPU_755;
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}
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}
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break;
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case 0x7000:
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type = CPU_750FX;
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break;
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case 0x800C:
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type = CPU_7410;
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break;
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case 0x8000:
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case 0x8000:
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type = CPU_7450;
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break;
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@ -116,6 +120,10 @@ int checkcpu (void)
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str = "750";
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break;
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case CPU_750FX:
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str = "750FX";
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break;
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case CPU_755:
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str = "755";
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break;
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@ -124,16 +132,16 @@ int checkcpu (void)
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str = "MPC7400";
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break;
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case CPU_7410:
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str = "MPC7410";
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case CPU_7410:
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str = "MPC7410";
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break;
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case CPU_7450:
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str = "MPC7450";
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case CPU_7450:
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str = "MPC7450";
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break;
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default:
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printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
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printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
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return -1;
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}
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@ -146,8 +154,8 @@ PR_CLK:
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#endif
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/* these two functions are unimplemented currently [josh] */
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/* ------------------------------------------------------------------------- */
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/* L1 i-cache */
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/* -------------------------------------------------------------------- */
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/* L1 i-cache */
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int
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checkicache(void)
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@ -155,8 +163,8 @@ checkicache(void)
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return 0; /* XXX */
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}
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/* ------------------------------------------------------------------------- */
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/* L1 d-cache */
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/* -------------------------------------------------------------------- */
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/* L1 d-cache */
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int
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checkdcache(void)
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@ -164,7 +172,7 @@ checkdcache(void)
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return 0; /* XXX */
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}
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/* ------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------- */
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static inline void
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soft_restart(unsigned long addr)
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@ -48,6 +48,33 @@ static const int hid1_multipliers_x_10[] = {
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0 /* 1111 - off */
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};
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static const int hid1_fx_multipliers_x_10[] = {
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00, /* 0000 - off */
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00, /* 0001 - off */
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10, /* 0010 - bypass */
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10, /* 0011 - bypass */
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20, /* 0100 - 2x */
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25, /* 0101 - 2.5x */
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30, /* 0110 - 3x */
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35, /* 0111 - 3.5x */
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40, /* 1000 - 4x */
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45, /* 1001 - 4.5x */
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50, /* 1010 - 5x */
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55, /* 1011 - 5.5x */
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60, /* 1100 - 6x */
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65, /* 1101 - 6.5x */
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70, /* 1110 - 7x */
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75, /* 1111 - 7.5 */
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80, /* 10000 - 8x */
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85, /* 10001 - 8.5x */
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90, /* 10010 - 9x */
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95, /* 10011 - 9.5x */
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100, /* 10100 - 10x */
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110, /* 10101 - 11x */
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120, /* 10110 - 12x */
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};
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/* ------------------------------------------------------------------------- */
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/*
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@ -59,9 +86,13 @@ static const int hid1_multipliers_x_10[] = {
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int get_clocks (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_750FX
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ulong clock = CFG_BUS_CLK * \
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hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
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#else
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ulong clock = CFG_BUS_CLK * \
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hid1_multipliers_x_10[get_hid1 () >> 28] / 10;
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#endif
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gd->cpu_clk = clock;
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gd->bus_clk = CFG_BUS_CLK;
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@ -379,11 +379,23 @@ invalidate_bats:
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mtspr IBAT1U, r0
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mtspr IBAT2U, r0
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mtspr IBAT3U, r0
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#ifdef CONFIG_750FX
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mtspr IBAT4U, r0
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mtspr IBAT5U, r0
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mtspr IBAT6U, r0
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mtspr IBAT7U, r0
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#endif
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isync
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mtspr DBAT0U, r0
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mtspr DBAT1U, r0
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mtspr DBAT2U, r0
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mtspr DBAT3U, r0
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#ifdef CONFIG_750FX
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mtspr DBAT4U, r0
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mtspr DBAT5U, r0
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mtspr DBAT6U, r0
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mtspr DBAT7U, r0
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#endif
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isync
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sync
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blr
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@ -465,6 +477,80 @@ setup_bats:
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mtspr DBAT3U, r3
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isync
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#ifdef CONFIG_750FX
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/* IBAT 4 */
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addis r4, r0, CFG_IBAT4L@h
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ori r4, r4, CFG_IBAT4L@l
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addis r3, r0, CFG_IBAT4U@h
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ori r3, r3, CFG_IBAT4U@l
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mtspr IBAT4L, r4
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mtspr IBAT4U, r3
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isync
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/* DBAT 4 */
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addis r4, r0, CFG_DBAT4L@h
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ori r4, r4, CFG_DBAT4L@l
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addis r3, r0, CFG_DBAT4U@h
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ori r3, r3, CFG_DBAT4U@l
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mtspr DBAT4L, r4
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mtspr DBAT4U, r3
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isync
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/* IBAT 5 */
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addis r4, r0, CFG_IBAT5L@h
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ori r4, r4, CFG_IBAT5L@l
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addis r3, r0, CFG_IBAT5U@h
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ori r3, r3, CFG_IBAT5U@l
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mtspr IBAT5L, r4
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mtspr IBAT5U, r3
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isync
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/* DBAT 5 */
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addis r4, r0, CFG_DBAT5L@h
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ori r4, r4, CFG_DBAT5L@l
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addis r3, r0, CFG_DBAT5U@h
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ori r3, r3, CFG_DBAT5U@l
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mtspr DBAT5L, r4
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mtspr DBAT5U, r3
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isync
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/* IBAT 6 */
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addis r4, r0, CFG_IBAT6L@h
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ori r4, r4, CFG_IBAT6L@l
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addis r3, r0, CFG_IBAT6U@h
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ori r3, r3, CFG_IBAT6U@l
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mtspr IBAT6L, r4
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mtspr IBAT6U, r3
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isync
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/* DBAT 6 */
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addis r4, r0, CFG_DBAT6L@h
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ori r4, r4, CFG_DBAT6L@l
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addis r3, r0, CFG_DBAT6U@h
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ori r3, r3, CFG_DBAT6U@l
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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isync
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/* IBAT 7 */
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addis r4, r0, CFG_IBAT7L@h
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ori r4, r4, CFG_IBAT7L@l
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addis r3, r0, CFG_IBAT7U@h
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ori r3, r3, CFG_IBAT7U@l
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mtspr IBAT7L, r4
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mtspr IBAT7U, r3
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isync
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/* DBAT 7 */
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addis r4, r0, CFG_DBAT7L@h
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ori r4, r4, CFG_DBAT7L@l
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addis r3, r0, CFG_DBAT7U@h
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ori r3, r3, CFG_DBAT7U@l
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mtspr DBAT7L, r4
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mtspr DBAT7U, r3
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isync
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#endif
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/* bats are done, now invalidate the TLBs */
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addis r3, 0, 0x0000
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@ -108,7 +108,7 @@ typedef enum __cpu_t {
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CPU_740, CPU_750,
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CPU_740P, CPU_750P,
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CPU_745, CPU_755,
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CPU_750CX,
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CPU_750CX, CPU_750FX,
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CPU_7400,
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CPU_7410,
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CPU_7450,
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@ -95,6 +95,14 @@
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#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
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#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
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#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
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#define SPRN_DBAT4L 0x238 /* Data BAT 4 Lower Register */
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#define SPRN_DBAT4U 0x239 /* Data BAT 4 Upper Register */
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#define SPRN_DBAT5L 0x23A /* Data BAT 5 Lower Register */
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#define SPRN_DBAT5U 0x23B /* Data BAT 5 Upper Register */
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#define SPRN_DBAT6L 0x23C /* Data BAT 6 Lower Register */
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#define SPRN_DBAT6U 0x23D /* Data BAT 6 Upper Register */
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#define SPRN_DBAT7L 0x23E /* Data BAT 7 Lower Register */
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#define SPRN_DBAT7U 0x23F /* Data BAT 7 Lower Register */
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#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
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#define DBCR_EDM 0x80000000
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#define DBCR_IDM 0x40000000
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@ -195,6 +203,14 @@
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#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
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#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
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#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
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#define SPRN_IBAT4L 0x230 /* Instruction BAT 4 Lower Register */
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#define SPRN_IBAT4U 0x231 /* Instruction BAT 4 Upper Register */
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#define SPRN_IBAT5L 0x232 /* Instruction BAT 5 Lower Register */
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#define SPRN_IBAT5U 0x233 /* Instruction BAT 5 Upper Register */
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#define SPRN_IBAT6L 0x234 /* Instruction BAT 6 Lower Register */
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#define SPRN_IBAT6U 0x235 /* Instruction BAT 6 Upper Register */
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#define SPRN_IBAT7L 0x236 /* Instruction BAT 7 Lower Register */
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#define SPRN_IBAT7U 0x237 /* Instruction BAT 7 Lower Register */
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#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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#define ICCR_NOCACHE 0 /* Noncacheable */
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#define ICCR_CACHE 1 /* Cacheable */
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@ -305,6 +321,14 @@
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#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
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#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
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#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
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#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
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#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
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#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
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#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
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#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
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#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
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#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
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#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
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#define DCMP SPRN_DCMP /* Data TLB Compare Register */
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#define DEC SPRN_DEC /* Decrement Register */
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#define DMISS SPRN_DMISS /* Data TLB Miss Register */
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@ -323,6 +347,14 @@
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#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
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#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
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#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
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#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
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#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
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#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
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#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
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#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
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#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
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#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
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#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
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#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
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#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
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#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
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