mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 15:12:04 +00:00
arc: Fine-tune implementation of memory barriers
We improve on 2 things: 1. Only ARC HS family has "dmb" instructions so do compile-time check for automatically defined macro __ARCHS__. Previous check for ARCv2 ISA was not good enough because ARC EM family is v2 ISA as well but still "dmb" instaruction is not supported in EM family. 2. Still if there's no dedicated instruction for memory barrier let's at least insert compile-time barrier to make sure compiler deosn't reorder critical memory operations. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
parent
264d298fda
commit
71621525c3
1 changed files with 4 additions and 4 deletions
|
@ -10,7 +10,7 @@
|
|||
#include <linux/types.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#ifdef __ARCHS__
|
||||
|
||||
/*
|
||||
* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
|
||||
|
@ -42,12 +42,12 @@
|
|||
#define mb() asm volatile("sync\n" : : : "memory")
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
#ifdef __ARCHS__
|
||||
#define __iormb() rmb()
|
||||
#define __iowmb() wmb()
|
||||
#else
|
||||
#define __iormb() do { } while (0)
|
||||
#define __iowmb() do { } while (0)
|
||||
#define __iormb() asm volatile("" : : : "memory")
|
||||
#define __iowmb() asm volatile("" : : : "memory")
|
||||
#endif
|
||||
|
||||
static inline void sync(void)
|
||||
|
|
Loading…
Reference in a new issue