mirror of
https://github.com/AsahiLinux/u-boot
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mtd: spi-nor-core: Rework hwcaps selection
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make sure the build doesn't break for boards not using CONFIG_DM_SPI,
add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm
similar to spi_mem_default_supports_op(). This change is only
compile-tested.
To avoid SPL size problems on the x530 board, the old hwcaps selection
is still kept around. Leaving the code in-place was getting difficult to
read and understand, so the code is restructured to have it all in one
isolated function. As a result of this, the parameter hwcaps to
spi_nor_setup() is no longer needed. Remove it.
Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps
selection for the spi-mem case, 2019-08-06)
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Pratyush Yadav
Jagan Teki
parent
8702188ce5
commit
71025f013c
4 changed files with 280 additions and 52 deletions
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@ -88,6 +88,15 @@ config SPI_FLASH_SFDP_SUPPORT
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SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
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tables as per JESD216 standard.
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config SPI_FLASH_SMART_HWCAPS
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bool "Smart hardware capability detection based on SPI MEM supports_op() hook"
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default y
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help
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Enable support for smart hardware capability detection based on SPI
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MEM supports_op() hook that lets controllers express whether they
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can support a type of operation in a much more refined way compared
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to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
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config SPI_FLASH_BAR
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bool "SPI flash Bank/Extended address register support"
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help
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@ -2299,6 +2299,194 @@ static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
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ARRAY_SIZE(hwcaps_pp2cmd));
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}
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#ifdef CONFIG_SPI_FLASH_SMART_HWCAPS
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/**
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* spi_nor_check_op - check if the operation is supported by controller
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* @nor: pointer to a 'struct spi_nor'
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* @op: pointer to op template to be checked
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*
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* Returns 0 if operation is supported, -ENOTSUPP otherwise.
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*/
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static int spi_nor_check_op(struct spi_nor *nor,
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struct spi_mem_op *op)
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{
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/*
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* First test with 4 address bytes. The opcode itself might be a 3B
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* addressing opcode but we don't care, because SPI controller
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* implementation should not check the opcode, but just the sequence.
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*/
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op->addr.nbytes = 4;
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if (!spi_mem_supports_op(nor->spi, op)) {
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if (nor->mtd.size > SZ_16M)
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return -ENOTSUPP;
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/* If flash size <= 16MB, 3 address bytes are sufficient */
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op->addr.nbytes = 3;
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if (!spi_mem_supports_op(nor->spi, op))
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return -ENOTSUPP;
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}
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return 0;
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}
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/**
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* spi_nor_check_readop - check if the read op is supported by controller
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* @nor: pointer to a 'struct spi_nor'
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* @read: pointer to op template to be checked
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*
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* Returns 0 if operation is supported, -ENOTSUPP otherwise.
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*/
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static int spi_nor_check_readop(struct spi_nor *nor,
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const struct spi_nor_read_command *read)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 1),
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SPI_MEM_OP_ADDR(3, 0, 1),
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SPI_MEM_OP_DUMMY(0, 1),
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SPI_MEM_OP_DATA_IN(0, NULL, 1));
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op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(read->proto);
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op.addr.buswidth = spi_nor_get_protocol_addr_nbits(read->proto);
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op.data.buswidth = spi_nor_get_protocol_data_nbits(read->proto);
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op.dummy.buswidth = op.addr.buswidth;
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op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
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op.dummy.buswidth / 8;
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return spi_nor_check_op(nor, &op);
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}
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/**
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* spi_nor_check_pp - check if the page program op is supported by controller
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* @nor: pointer to a 'struct spi_nor'
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* @pp: pointer to op template to be checked
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*
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* Returns 0 if operation is supported, -ENOTSUPP otherwise.
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*/
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static int spi_nor_check_pp(struct spi_nor *nor,
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const struct spi_nor_pp_command *pp)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 1),
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SPI_MEM_OP_ADDR(3, 0, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(0, NULL, 1));
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op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(pp->proto);
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op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto);
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op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto);
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return spi_nor_check_op(nor, &op);
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}
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/**
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* spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
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* controller capabilities
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* @nor: pointer to a 'struct spi_nor'
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* @params: pointer to the 'struct spi_nor_flash_parameter'
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* representing SPI NOR flash capabilities
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* @hwcaps: pointer to resulting capabilities after adjusting
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* according to controller and flash's capability
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*
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* Discard caps based on what the SPI controller actually supports (using
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* spi_mem_supports_op()).
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*/
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static void
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spi_nor_adjust_hwcaps(struct spi_nor *nor,
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const struct spi_nor_flash_parameter *params,
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u32 *hwcaps)
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{
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unsigned int cap;
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/*
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* Enable all caps by default. We will mask them after checking what's
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* really supported using spi_mem_supports_op().
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*/
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*hwcaps = SNOR_HWCAPS_ALL;
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/* DTR modes are not supported yet, mask them all. */
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*hwcaps &= ~SNOR_HWCAPS_DTR;
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/* X-X-X modes are not supported yet, mask them all. */
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*hwcaps &= ~SNOR_HWCAPS_X_X_X;
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for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
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int rdidx, ppidx;
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if (!(*hwcaps & BIT(cap)))
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continue;
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rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
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if (rdidx >= 0 &&
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spi_nor_check_readop(nor, ¶ms->reads[rdidx]))
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*hwcaps &= ~BIT(cap);
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ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
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if (ppidx < 0)
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continue;
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if (spi_nor_check_pp(nor, ¶ms->page_programs[ppidx]))
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*hwcaps &= ~BIT(cap);
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}
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}
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#else
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/**
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* spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
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* controller capabilities
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* @nor: pointer to a 'struct spi_nor'
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* @params: pointer to the 'struct spi_nor_flash_parameter'
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* representing SPI NOR flash capabilities
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* @hwcaps: pointer to resulting capabilities after adjusting
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* according to controller and flash's capability
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*
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* Select caps based on what the SPI controller and SPI flash both support.
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*/
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static void
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spi_nor_adjust_hwcaps(struct spi_nor *nor,
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const struct spi_nor_flash_parameter *params,
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u32 *hwcaps)
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{
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struct spi_slave *spi = nor->spi;
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u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
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SNOR_HWCAPS_READ_4_4_4 |
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SNOR_HWCAPS_READ_8_8_8 |
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SNOR_HWCAPS_PP_4_4_4 |
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SNOR_HWCAPS_PP_8_8_8);
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u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_PP);
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/* Get the hardware capabilities the SPI controller supports. */
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if (spi->mode & SPI_RX_OCTAL) {
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spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8;
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if (spi->mode & SPI_TX_OCTAL)
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spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 |
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SNOR_HWCAPS_PP_1_1_8 |
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SNOR_HWCAPS_PP_1_8_8);
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} else if (spi->mode & SPI_RX_QUAD) {
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spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4;
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if (spi->mode & SPI_TX_QUAD)
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spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 |
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SNOR_HWCAPS_PP_1_1_4 |
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SNOR_HWCAPS_PP_1_4_4);
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} else if (spi->mode & SPI_RX_DUAL) {
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spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2;
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if (spi->mode & SPI_TX_DUAL)
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spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2;
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}
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/*
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* Keep only the hardware capabilities supported by both the SPI
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* controller and the SPI flash memory.
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*/
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*hwcaps = spi_hwcaps & params->hwcaps.mask;
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if (*hwcaps & ignored_mask) {
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dev_dbg(nor->dev,
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"SPI n-n-n protocols are not supported yet.\n");
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*hwcaps &= ~ignored_mask;
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}
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}
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#endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */
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static int spi_nor_select_read(struct spi_nor *nor,
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const struct spi_nor_flash_parameter *params,
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u32 shared_hwcaps)
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@ -2379,30 +2567,13 @@ static int spi_nor_select_erase(struct spi_nor *nor,
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static int spi_nor_default_setup(struct spi_nor *nor,
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const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps)
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const struct spi_nor_flash_parameter *params)
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{
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u32 ignored_mask, shared_mask;
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u32 shared_mask;
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bool enable_quad_io;
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int err;
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/*
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* Keep only the hardware capabilities supported by both the SPI
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* controller and the SPI flash memory.
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*/
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shared_mask = hwcaps->mask & params->hwcaps.mask;
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/* SPI n-n-n protocols are not supported yet. */
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ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
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SNOR_HWCAPS_READ_4_4_4 |
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SNOR_HWCAPS_READ_8_8_8 |
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SNOR_HWCAPS_PP_4_4_4 |
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SNOR_HWCAPS_PP_8_8_8);
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if (shared_mask & ignored_mask) {
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dev_dbg(nor->dev,
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"SPI n-n-n protocols are not supported yet.\n");
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shared_mask &= ~ignored_mask;
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}
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spi_nor_adjust_hwcaps(nor, params, &shared_mask);
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/* Select the (Fast) Read command. */
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err = spi_nor_select_read(nor, params, shared_mask);
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@ -2440,13 +2611,12 @@ static int spi_nor_default_setup(struct spi_nor *nor,
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}
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static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps)
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const struct spi_nor_flash_parameter *params)
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{
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if (!nor->setup)
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return 0;
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return nor->setup(nor, info, params, hwcaps);
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return nor->setup(nor, info, params);
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}
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static int spi_nor_init(struct spi_nor *nor)
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@ -2502,11 +2672,6 @@ int spi_nor_scan(struct spi_nor *nor)
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struct spi_nor_flash_parameter params;
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const struct flash_info *info = NULL;
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struct mtd_info *mtd = &nor->mtd;
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struct spi_nor_hwcaps hwcaps = {
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.mask = SNOR_HWCAPS_READ |
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SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_PP,
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};
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struct spi_slave *spi = nor->spi;
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int ret;
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@ -2521,27 +2686,6 @@ int spi_nor_scan(struct spi_nor *nor)
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nor->setup = spi_nor_default_setup;
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if (spi->mode & SPI_RX_OCTAL) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
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if (spi->mode & SPI_TX_OCTAL)
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hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
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SNOR_HWCAPS_PP_1_1_8 |
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SNOR_HWCAPS_PP_1_8_8);
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} else if (spi->mode & SPI_RX_QUAD) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
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if (spi->mode & SPI_TX_QUAD)
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hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
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SNOR_HWCAPS_PP_1_1_4 |
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SNOR_HWCAPS_PP_1_4_4);
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} else if (spi->mode & SPI_RX_DUAL) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
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if (spi->mode & SPI_TX_DUAL)
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hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
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}
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info = spi_nor_read_id(nor);
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if (IS_ERR_OR_NULL(info))
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return -ENOENT;
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@ -2616,7 +2760,7 @@ int spi_nor_scan(struct spi_nor *nor)
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* - set the SPI protocols for register and memory accesses.
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* - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
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*/
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ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
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ret = spi_nor_setup(nor, info, ¶ms);
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if (ret)
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return ret;
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@ -105,3 +105,65 @@ int spi_mem_adjust_op_size(struct spi_slave *slave,
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return 0;
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}
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static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx)
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{
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u32 mode = slave->mode;
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switch (buswidth) {
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case 1:
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return 0;
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case 2:
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if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) ||
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(!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD))))
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return 0;
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break;
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case 4:
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if ((tx && (mode & SPI_TX_QUAD)) ||
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(!tx && (mode & SPI_RX_QUAD)))
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return 0;
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break;
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case 8:
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if ((tx && (mode & SPI_TX_OCTAL)) ||
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(!tx && (mode & SPI_RX_OCTAL)))
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return 0;
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break;
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default:
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break;
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}
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return -ENOTSUPP;
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}
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bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op)
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{
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if (spi_check_buswidth_req(slave, op->cmd.buswidth, true))
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return false;
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if (op->addr.nbytes &&
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spi_check_buswidth_req(slave, op->addr.buswidth, true))
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return false;
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if (op->dummy.nbytes &&
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spi_check_buswidth_req(slave, op->dummy.buswidth, true))
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return false;
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if (op->data.nbytes &&
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spi_check_buswidth_req(slave, op->data.buswidth,
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op->data.dir == SPI_MEM_DATA_OUT))
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return false;
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if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
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return false;
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if (op->cmd.nbytes != 1)
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return false;
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return true;
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}
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@ -312,6 +312,20 @@ struct spi_nor_hwcaps {
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#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
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#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
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#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
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SNOR_HWCAPS_READ_4_4_4 | \
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SNOR_HWCAPS_READ_8_8_8 | \
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SNOR_HWCAPS_PP_4_4_4 | \
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SNOR_HWCAPS_PP_8_8_8)
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#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
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SNOR_HWCAPS_READ_1_2_2_DTR | \
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SNOR_HWCAPS_READ_1_4_4_DTR | \
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SNOR_HWCAPS_READ_1_8_8_DTR)
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#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
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SNOR_HWCAPS_PP_MASK)
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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@ -461,8 +475,7 @@ struct spi_nor {
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struct spi_nor_fixups *fixups;
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int (*setup)(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps);
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const struct spi_nor_flash_parameter *params);
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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