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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
ColdFire: Update for M54451EVB
Update serial boot DRAM's Internal RAM, vector table and DRAM in start.S, serial flash's read status command over SPI and NOR flash. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
This commit is contained in:
TsiChung Liew
TsiChung Liew
parent
bbf6bbffca
commit
709b384b64
5 changed files with 82 additions and 66 deletions
9
Makefile
9
Makefile
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@ -2108,18 +2108,15 @@ M5373EVB_config : unconfig
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@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
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M54451EVB_config \
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M54451EVB_spansion_config \
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M54451EVB_stmicro_config : unconfig
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@case "$@" in \
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M54451EVB_config) FLASH=SPANSION;; \
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M54451EVB_spansion_config) FLASH=SPANSION;; \
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M54451EVB_config) FLASH=NOR;; \
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M54451EVB_stmicro_config) FLASH=STMICRO;; \
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esac; \
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if [ "$${FLASH}" = "SPANSION" ] ; then \
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echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
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if [ "$${FLASH}" = "NOR" ] ; then \
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echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
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cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
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$(XECHO) "... with SPANSION boot..." ; \
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$(XECHO) "... with NOR boot..." ; \
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fi; \
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if [ "$${FLASH}" = "STMICRO" ] ; then \
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echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
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@ -56,10 +56,13 @@ SECTIONS
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mcf5445x/start.o (.text)
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lib_m68k/traps.o (.text)
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lib_m68k/interrupts.o (.text)
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cpu/mcf5445x/libmcf5445x.a (.text)
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lib_m68k/libm68k.a (.text)
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common/cmd_flash.o (.text)
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common/dlmalloc.o (.text)
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lib_generic/zlib.o (.text)
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common/main.o (.text)
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common/image.o (.text)
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lib_generic/libgeneric.a (.text)
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. = DEFINED(env_offset) ? env_offset : .;
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common/env_embedded.o (.text)
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@ -159,9 +159,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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dspi_rx();
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return 0;
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case 0x05: /* Read Status */
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if (len == 4)
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if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
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&& (spi_wr[3] == 0xFF)) {
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if (len == 1) {
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dspi_tx(slave->cs, 0x80, *spi_wr);
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dspi_rx();
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}
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@ -149,9 +149,35 @@ asm_sbf_img_hdr:
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.long 0x00030000 /* image length */
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.long TEXT_BASE /* image to be relocated at */
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asm_dram_init:
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move.w #0x2700,%sr /* Mask off Interrupt */
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move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
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movec %d0, %VBR
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move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
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movec %d0, %RAMBAR1 /* init Rambar */
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movec %d0, %RAMBAR1
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/* initialize general use internal ram */
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move.l #0, %d0
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move.l #(CACR_STATUS), %a1 /* CACR */
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move.l #(ICACHE_STATUS), %a2 /* icache */
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move.l #(DCACHE_STATUS), %a3 /* dcache */
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move.l %d0, (%a1)
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move.l %d0, (%a2)
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move.l %d0, (%a3)
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/* invalidate and disable cache */
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move.l #0x01004100, %d0 /* Invalidate cache cmd */
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movec %d0, %CACR /* Invalidate cache */
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move.l #0, %d0
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movec %d0, %ACR0
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movec %d0, %ACR1
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movec %d0, %ACR2
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movec %d0, %ACR3
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move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
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clr.l %sp@-
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@ -163,10 +189,7 @@ asm_dram_init:
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move.l #0xFC008004, %a1
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move.l #(CONFIG_SYS_CS0_MASK), (%a1)
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/*
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* Dram Initialization
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* a1, a2, and d0
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*/
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/* Dram Initialization a1, a2, and d0 */
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/* mscr sdram */
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move.l #0xFC0A4074, %a1
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move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
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@ -209,24 +232,21 @@ dramsz_loop:
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move.l #0xFC0B8000, %a1 /* Mode */
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move.l #0xFC0B8004, %a2 /* Ctrl */
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#ifdef CONFIG_M54455EVB
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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#ifdef CONFIG_M54455EVB
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/* Issue LEMR */
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move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
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nop
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move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
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nop
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move.l #1000, %d0
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wait1000:
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nop
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subq.l #1, %d0
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bne wait1000
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#endif
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move.l #1000, %d1
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jsr asm_delay
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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@ -246,25 +266,24 @@ wait1000:
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move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
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nop
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move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
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nop
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#endif
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move.l #500, %d0
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wait500:
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nop
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subq.l #1, %d0
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bne wait500
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move.l #500, %d1
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jsr asm_delay
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move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
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and.l #0x7FFFFFFF, %d0
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move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
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and.l #0x7FFFFFFF, %d1
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#ifdef CONFIG_M54455EVB
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or.l #0x10000c00, %d0
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or.l #0x10000C00, %d1
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#elif defined(CONFIG_M54451EVB)
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or.l #0x10000000, %d0
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or.l #0x10000C00, %d1
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#endif
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move.l %d0, (%a2)
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move.l %d1, (%a2)
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nop
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move.l #2000, %d1
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jsr asm_delay
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/*
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* DSPI Initialization
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* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
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@ -274,6 +293,7 @@ wait500:
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* a4 - Dst addr
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*/
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/* Enable pins for DSPI mode - chip-selects are enabled later */
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asm_dspi_init:
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move.l #0xFC0A4063, %a0
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move.b #0x7F, (%a0)
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@ -367,27 +387,29 @@ asm_dspi_rd_status:
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move.b (%a3), %d1
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rts
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asm_delay:
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nop
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subq.l #1, %d1
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bne asm_delay
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rts
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#endif /* CONFIG_CF_SBF */
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.text
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. = 0x400
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.globl _start
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_start:
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#if !defined(CONFIG_CF_SBF)
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nop
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nop
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move.w #0x2700,%sr /* Mask off Interrupt */
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/* Set vector base register at the beginning of the Flash */
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#if defined(CONFIG_CF_SBF)
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move.l #TEXT_BASE, %d0
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movec %d0, %VBR
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#else
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move.l #CONFIG_SYS_FLASH_BASE, %d0
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movec %d0, %VBR
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move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
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movec %d0, %RAMBAR1
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#endif
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/* initialize general use internal ram */
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move.l #0, %d0
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@ -411,6 +433,7 @@ _start:
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the first c-code */
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move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
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clr.l %sp@-
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#endif
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move.l #__got_start, %a5 /* put relocation table address to a5 */
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@ -532,7 +555,7 @@ icache_enable:
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move.l #0x00040100, %d0 /* Invalidate icache */
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movec %d0, %CACR
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move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
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move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */
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movec %d0, %ACR2
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move.l #0x04088020, %d0 /* Enable bcache and icache */
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@ -70,6 +70,7 @@
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SPI
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@ -265,7 +266,7 @@
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#if defined(CONFIG_CF_SBF)
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#if defined(CONFIG_SYS_STMICRO_BOOT)
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# define CONFIG_ENV_IS_IN_SPI_FLASH 1
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# define CONFIG_ENV_SPI_CS 1
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# define CONFIG_ENV_OFFSET 0x20000
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@ -273,8 +274,9 @@
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# define CONFIG_ENV_SECT_SIZE 0x10000
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#else
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# define CONFIG_ENV_IS_IN_FLASH 1
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
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# define CONFIG_ENV_SECT_SIZE 0x2000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
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# define CONFIG_ENV_SIZE 0x2000
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# define CONFIG_ENV_SECT_SIZE 0x8000
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#endif
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#undef CONFIG_ENV_OVERWRITE
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#undef CONFIG_ENV_IS_EMBEDDED
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@ -286,8 +288,7 @@
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# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
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# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
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# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
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#endif
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#ifdef CONFIG_SYS_SPANSION_BOOT
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#else
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# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
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# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_SER_FLASH_BASE
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@ -297,6 +298,7 @@
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#ifdef CONFIG_SYS_FLASH_CFI
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# define CONFIG_FLASH_CFI_DRIVER 1
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# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
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# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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@ -311,27 +313,20 @@
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* This is setting for JFFS2 support in u-boot.
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* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
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*/
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#ifdef CONFIG_SYS_SPANSION_BOOT
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# define CONFIG_JFFS2_DEV "nor0"
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# define CONFIG_JFFS2_PART_SIZE 0x01000000
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# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
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#endif
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#ifdef CONFIG_SYS_STMICRO_BOOT
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#ifdef CONFIG_CMD_JFFS2
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# define CONFIG_JFFS2_DEV "nor0"
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# define CONFIG_JFFS2_PART_SIZE 0x01000000
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# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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/*
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* CS0 - NOR Flash 8MB
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* CS0 - NOR Flash 16MB
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* CS1 - Available
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* CS2 - Available
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* CS3 - Available
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@ -339,10 +334,10 @@
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* CS5 - Available
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*/
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/* SPANSION Flash */
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/* Flash */
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#define CONFIG_SYS_CS0_BASE 0x00000000
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#define CONFIG_SYS_CS0_MASK 0x007F0001
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#define CONFIG_SYS_CS0_CTRL 0x00001180
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#define CONFIG_SYS_CS0_MASK 0x00FF0001
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#define CONFIG_SYS_CS0_CTRL 0x00004D80
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#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
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