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ppc4xx: Add basic support for AMCC 460EX/460GT (4/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
999ecd5aca
commit
6f2eb3f3d8
3 changed files with 33 additions and 12 deletions
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@ -273,7 +273,9 @@ void pciinfo (int, int);
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void pci_master_init (struct pci_controller *);
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# endif
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int is_pci_host (struct pci_controller *);
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#if defined(CONFIG_440SPE) || defined(CONFIG_405EX)
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#if defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX)
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void pcie_setup_hoses(int busno);
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#endif
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#endif
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@ -118,7 +118,17 @@
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/******************************************************************************
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* Universal interrupt controller
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******************************************************************************/
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#define UIC_SR 0x0 /* UIC status */
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#define UIC_ER 0x2 /* UIC enable */
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#define UIC_CR 0x3 /* UIC critical */
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#define UIC_PR 0x4 /* UIC polarity */
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#define UIC_TR 0x5 /* UIC triggering */
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#define UIC_MSR 0x6 /* UIC masked status */
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#define UIC_VR 0x7 /* UIC vector */
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#define UIC_VCR 0x8 /* UIC vector configuration */
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#define UIC_DCR_BASE 0xc0
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#define UIC0_DCR_BASE UIC_DCR_BASE
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#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
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#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
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#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
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@ -141,6 +151,7 @@
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#define uic0vcr uicvcr /* UIC vector configuration*/
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#define UIC_DCR_BASE1 0xd0
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#define UIC1_DCR_BASE 0xd0
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#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
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#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
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#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
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@ -152,6 +163,7 @@
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#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
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#define UIC_DCR_BASE2 0xe0
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#define UIC2_DCR_BASE 0xe0
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#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
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#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
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#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
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@ -237,10 +249,13 @@
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#define UIC_ENET1 0x00000040 /* */
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#define UIC_PCIEMSI2 0x00000020 /* */
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#define UIC_EIRQ4 0x00000010 /**/
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#define UIC_UIC2NC 0x00000008 /* */
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#define UIC_UIC2C 0x00000004 /* */
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#define UIC_UIC1NC 0x00000002 /* */
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#define UIC_UIC1C 0x00000001 /* */
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#define UICB0_UIC2NCI 0x00000008 /* */
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#define UICB0_UIC2CI 0x00000004 /* */
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#define UICB0_UIC1NCI 0x00000002 /* */
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#define UICB0_UIC1CI 0x00000001 /* */
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#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
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UICB0_UIC1CI | UICB0_UIC2NCI)
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#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
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#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
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@ -131,7 +131,7 @@ typedef struct emac_4xx_hw_st {
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} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
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#if defined(CONFIG_440GX)
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#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
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#define EMAC_NUM_DEV 4
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#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
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defined(CONFIG_NET_MULTI) && \
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@ -155,7 +155,8 @@ typedef struct emac_4xx_hw_st {
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/* ZMII Bridge Register addresses */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
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#else
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#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
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@ -164,9 +165,6 @@ typedef struct emac_4xx_hw_st {
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#define ZMII_SSR (ZMII_BASE + 4)
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#define ZMII_SMIISR (ZMII_BASE + 8)
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#define ZMII_RMII 0x22000000
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#define ZMII_MDI0 0x80000000
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/* ZMII FER Register Bit Definitions */
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#define ZMII_FER_DIS (0x0)
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#define ZMII_FER_MDI (0x8)
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@ -205,6 +203,8 @@ typedef struct emac_4xx_hw_st {
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/* RGMII Register Addresses */
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
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#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1500)
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#elif defined(CONFIG_405EX)
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#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00)
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#else
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@ -223,19 +223,21 @@ typedef struct emac_4xx_hw_st {
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#define RGMII_FER_V(__x) ((__x - 2) * 4)
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#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
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/* RGMII Speed Selection Register Bit Definitions */
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#define RGMII_SSR_SP_10MBPS (0x00)
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#define RGMII_SSR_SP_100MBPS (0x02)
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#define RGMII_SSR_SP_1000MBPS (0x04)
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX)
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#define RGMII_SSR_V(__x) ((__x) * 8)
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#else
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#define RGMII_SSR_V(__x) ((__x -2) * 8)
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#endif
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/*---------------------------------------------------------------------------+
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| TCP/IP Acceleration Hardware (TAH) 440GX Only
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+---------------------------------------------------------------------------*/
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@ -304,7 +306,8 @@ typedef struct emac_4xx_hw_st {
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/* Ethernet MAC Regsiter Addresses */
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#if defined(CONFIG_440)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
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#else
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#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
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@ -345,6 +348,7 @@ typedef struct emac_4xx_hw_st {
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#if defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX)
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/* MODE Reg 1 */
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#define EMAC_M1_FDE (0x80000000)
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