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Merge git://git.denx.de/u-boot-sunxi

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This commit is contained in:
Tom Rini 2017-04-25 16:12:42 -04:00
commit 6f008a2e16
99 changed files with 1793 additions and 404 deletions
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35
arch/arm/cpu/armv7/sunxi/psci.c
View file

@ -27,6 +27,17 @@
#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
/*
* R40 is different from other single cluster SoCs.
*
* The power clamps are located in the unused space after the per-core
* reset controls for core 3. The secondary core entry address register
* is in the SRAM controller address range.
*/
#define SUN8I_R40_PWROFF (0x110)
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@ -68,7 +79,8 @@ static void __secure __mdelay(u32 ms)
static void __secure clamp_release(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3)
defined(CONFIG_MACH_SUN8I_H3) || \
defined(CONFIG_MACH_SUN8I_R40)
u32 tmp = 0x1ff;
do {
tmp >>= 1;
@ -82,7 +94,8 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
static void __secure clamp_set(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3)
defined(CONFIG_MACH_SUN8I_H3) || \
defined(CONFIG_MACH_SUN8I_R40)
writel(0xff, clamp);
#endif
}
@ -115,7 +128,17 @@ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
on, 0);
}
#else /* ! CONFIG_MACH_SUN7I */
#elif defined CONFIG_MACH_SUN8I_R40
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
(void *)cpucfg + SUN8I_R40_PWROFF,
on, 0);
}
#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_prcm_reg *prcm =
@ -213,7 +236,13 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
psci_save_target_pc(cpu, pc);
/* Set secondary core power on PC */
#ifdef CONFIG_MACH_SUN8I_R40
/* secondary core entry address is programmed differently */
writel((u32)&psci_cpu_entry,
SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
#else
writel((u32)&psci_cpu_entry, &cpucfg->priv0);
#endif
/* Assert reset on target CPU */
writel(0, &cpucfg->cpu[cpu].rst);

4
arch/arm/dts/Makefile
View file

@ -305,6 +305,10 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \

69
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts Normal file
View file

@ -0,0 +1,69 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-r40.dtsi"
/ {
model = "Banana Pi BPI-M2-Ultra";
compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

183
arch/arm/dts/sun8i-r40.dtsi Normal file
View file

@ -0,0 +1,183 @@
/*
* Copyright 2016 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
};
chosen {
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
/* apb should be replaced once CCU is implemented */
clocks = <&osc24M>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
i2c0_pins: i2c0_pins {
pins = "PB0", "PB1";
function = "i2c0";
bias-pull-up;
};
uart0_pb_pins: uart0_pb_pins {
pins = "PB22", "PB23";
function = "uart0";
bias-pull-up;
};
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
status = "disabled";
};
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
arm,cpu-registers-not-fw-configured;
};
};

83
arch/arm/dts/sun8i-v3s-licheepi-zero.dts Normal file
View file

@ -0,0 +1,83 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-v3s.dtsi"
#include "sunxi-common-regulators.dtsi"
/ {
model = "Lichee Pi Zero";
compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&mmc0 {
pinctrl-0 = <&mmc0_pins_a>;
pinctrl-names = "default";
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};

284
arch/arm/dts/sun8i-v3s.dtsi Normal file
View file

@ -0,0 +1,284 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_CPU>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
<&ccu CLK_MMC0>,
<&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@01c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
<&ccu CLK_MMC1>,
<&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@01c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>,
<&ccu CLK_MMC2>,
<&ccu CLK_MMC2_OUTPUT>,
<&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-v3s-usb-phy";
reg = <0x01c19400 0x2c>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu0";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
status = "disabled";
#phy-cells = <1>;
};
ccu: clock@01c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@01c20400 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01c20400 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-v3s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
bias-pull-up;
};
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
};
timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt0: watchdog@01c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@01c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

56
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
View file

@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
u32 dram_clk_gate; /* 0x100 DRAM module gating */
#ifdef CONFIG_SUNXI_DE2
u32 de_clk_cfg; /* 0x104 DE module clock */
#else
u32 be0_clk_cfg; /* 0x104 BE0 module clock */
#endif
u32 be1_clk_cfg; /* 0x108 BE1 module clock */
u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
u32 mp_clk_cfg; /* 0x114 MP module clock */
#ifdef CONFIG_SUNXI_DE2
u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */
u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */
#else
u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
#endif
u32 reserved14[3];
u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
u32 reserved15;
u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
#ifdef CONFIG_SUNXI_DE2
u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */
#else
u32 ps_clk_cfg; /* 0x154 PS module clock */
#endif
u32 mtc_clk_cfg; /* 0x158 MTC module clock */
u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
@ -142,6 +155,8 @@ struct sunxi_ccm_reg {
u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
u32 reserved25[5];
u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
u32 reserved26[11];
u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
};
/* apb2 bit field */
@ -191,6 +206,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT)
#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
#define CCM_PLL3_CTRL_LOCK (0x1 << 28)
#define CCM_PLL3_CTRL_EN (0x1 << 31)
#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
@ -220,6 +236,16 @@ struct sunxi_ccm_reg {
#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22)
#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31)
#define CCM_PLL10_CTRL_M_SHIFT 0
#define CCM_PLL10_CTRL_M_MASK (0xf << CCM_PLL10_CTRL_M_SHIFT)
#define CCM_PLL10_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_PLL10_CTRL_N_SHIFT 8
#define CCM_PLL10_CTRL_N_MASK (0x7f << CCM_PLL10_CTRL_N_SHIFT)
#define CCM_PLL10_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
#define CCM_PLL10_CTRL_INTEGER_MODE (0x1 << 24)
#define CCM_PLL10_CTRL_LOCK (0x1 << 28)
#define CCM_PLL10_CTRL_EN (0x1 << 31)
#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8)
#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
@ -271,9 +297,15 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_DRC0 25
#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_DE 12
#define AHB_GATE_OFFSET_HDMI 11
#ifndef CONFIG_SUNXI_DE2
#define AHB_GATE_OFFSET_LCD1 5
#define AHB_GATE_OFFSET_LCD0 4
#else
#define AHB_GATE_OFFSET_LCD1 4
#define AHB_GATE_OFFSET_LCD0 3
#endif
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
@ -355,6 +387,12 @@ struct sunxi_ccm_reg {
#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
#define CCM_LCD0_CTRL_GATE (0x1 << 31)
#define CCM_LCD0_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_LCD1_CTRL_GATE (0x1 << 31)
#define CCM_LCD1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
#define CCM_HDMI_CTRL_PLL3 (0 << 24)
@ -364,6 +402,8 @@ struct sunxi_ccm_reg {
#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
#define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31)
#if defined(CONFIG_MACH_SUN50I)
#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
#elif defined(CONFIG_MACH_SUN8I)
@ -391,9 +431,16 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_DRC0 25
#define AHB_RESET_OFFSET_DE_FE0 14
#define AHB_RESET_OFFSET_DE_BE0 12
#define AHB_RESET_OFFSET_DE 12
#define AHB_RESET_OFFSET_HDMI 11
#define AHB_RESET_OFFSET_HDMI2 10
#ifndef CONFIG_SUNXI_DE2
#define AHB_RESET_OFFSET_LCD1 5
#define AHB_RESET_OFFSET_LCD0 4
#else
#define AHB_RESET_OFFSET_LCD1 4
#define AHB_RESET_OFFSET_LCD0 3
#endif
/* ahb_reset2 offsets */
#define AHB_RESET_OFFSET_EPHY 2
@ -416,6 +463,13 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
#define CCM_DE2_CTRL_PLL6_2X (0 << 24)
#define CCM_DE2_CTRL_PLL10 (1 << 24)
#define CCM_DE2_CTRL_GATE (0x1 << 31)
/* CCU security switch, H3 only */
#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
@ -424,7 +478,9 @@ struct sunxi_ccm_reg {
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
void clock_set_pll3_factors(int m, int n);
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
void clock_set_pll10(unsigned int hz);
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
void clock_set_mipi_pll(unsigned int hz);
unsigned int clock_get_pll3(void);

1
arch/arm/include/asm/arch-sunxi/cpu.h
View file

@ -16,5 +16,6 @@
#define SOCID_A64 0x1689
#define SOCID_H3 0x1680
#define SOCID_H5 0x1718
#define SOCID_R40 0x1701
#endif /* _SUNXI_CPU_H */

6
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
View file

@ -108,7 +108,7 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
#ifdef CONFIG_MACH_SUN7I
#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
@ -167,7 +167,9 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T
#if defined CONFIG_SUNXI_GEN_SUN6I && \
!defined CONFIG_MACH_SUN8I_A83T && \
!defined CONFIG_MACH_SUN8I_R40
#define SUNXI_CPUCFG_BASE 0x01f01c00
#endif

103
arch/arm/include/asm/arch-sunxi/display.h
View file

@ -157,52 +157,6 @@ struct sunxi_de_be_reg {
u32 output_color_coef[12]; /* 0x9d0 */
};
struct sunxi_lcdc_reg {
u32 ctrl; /* 0x00 */
u32 int0; /* 0x04 */
u32 int1; /* 0x08 */
u8 res0[0x04]; /* 0x0c */
u32 tcon0_frm_ctrl; /* 0x10 */
u32 tcon0_frm_seed[6]; /* 0x14 */
u32 tcon0_frm_table[4]; /* 0x2c */
u8 res1[4]; /* 0x3c */
u32 tcon0_ctrl; /* 0x40 */
u32 tcon0_dclk; /* 0x44 */
u32 tcon0_timing_active; /* 0x48 */
u32 tcon0_timing_h; /* 0x4c */
u32 tcon0_timing_v; /* 0x50 */
u32 tcon0_timing_sync; /* 0x54 */
u32 tcon0_hv_intf; /* 0x58 */
u8 res2[0x04]; /* 0x5c */
u32 tcon0_cpu_intf; /* 0x60 */
u32 tcon0_cpu_wr_dat; /* 0x64 */
u32 tcon0_cpu_rd_dat0; /* 0x68 */
u32 tcon0_cpu_rd_dat1; /* 0x6c */
u32 tcon0_ttl_timing0; /* 0x70 */
u32 tcon0_ttl_timing1; /* 0x74 */
u32 tcon0_ttl_timing2; /* 0x78 */
u32 tcon0_ttl_timing3; /* 0x7c */
u32 tcon0_ttl_timing4; /* 0x80 */
u32 tcon0_lvds_intf; /* 0x84 */
u32 tcon0_io_polarity; /* 0x88 */
u32 tcon0_io_tristate; /* 0x8c */
u32 tcon1_ctrl; /* 0x90 */
u32 tcon1_timing_source; /* 0x94 */
u32 tcon1_timing_scale; /* 0x98 */
u32 tcon1_timing_out; /* 0x9c */
u32 tcon1_timing_h; /* 0xa0 */
u32 tcon1_timing_v; /* 0xa4 */
u32 tcon1_timing_sync; /* 0xa8 */
u8 res3[0x44]; /* 0xac */
u32 tcon1_io_polarity; /* 0xf0 */
u32 tcon1_io_tristate; /* 0xf4 */
u8 res4[0x108]; /* 0xf8 */
u32 mux_ctrl; /* 0x200 */
u8 res5[0x1c]; /* 0x204 */
u32 lvds_ana0; /* 0x220 */
u32 lvds_ana1; /* 0x224 */
};
struct sunxi_hdmi_reg {
u32 version_id; /* 0x000 */
u32 ctrl; /* 0x004 */
@ -346,63 +300,6 @@ struct sunxi_tve_reg {
#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1
/*
* LCDC register constants.
*/
#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
#ifdef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20)
#else
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */
#endif
#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20)
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16)
#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0)
#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0)
#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4)
#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4)
#ifdef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_LCDC_LVDS_ANA0 0x40040320
#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31)
#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24)
#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20)
#else
#define SUNXI_LCDC_LVDS_ANA0 0x3f310000
#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
#endif
#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
/*
* HDMI register constants.
*/

4
arch/arm/include/asm/arch-sunxi/dram.h
View file

@ -24,7 +24,9 @@
#include <asm/arch/dram_sun8i_a33.h>
#elif defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/dram_sun8i_a83t.h>
#elif defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \
defined(CONFIG_MACH_SUN8I_R40) || \
defined(CONFIG_MACH_SUN50I)
#include <asm/arch/dram_sun8i_h3.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/dram_sun9i.h>

20
arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
View file

@ -15,7 +15,8 @@
struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
u8 res0[0x8]; /* 0x04 */
u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
u8 res0[0x4]; /* 0x08 */
u32 tmr; /* 0x0c (unused on H3) */
u32 mcr[16][2]; /* 0x10 */
u32 bwcr; /* 0x90 bandwidth control register */
@ -63,6 +64,17 @@ struct sunxi_mctl_com_reg {
#define MCTL_CR_DUAL_RANK (0x1 << 0)
#define MCTL_CR_SINGLE_RANK (0x0 << 0)
/*
* CR_R1 is a register found in the R40's DRAM controller. It sets various
* parameters for rank 1. Bits [11:0] have the same meaning as the bits in
* MCTL_CR, but they apply to rank 1 only. This implies we can have
* different chips for rank 1 than rank 0.
*
* As address line A15 and CS1 chip select for rank 1 are muxed on the same
* pin, if single rank is used, A15 must be muxed in.
*/
#define MCTL_CR_R1_MUX_A15 (0x1 << 21)
#define PROTECT_MAGIC (0x94be6fa3)
struct sunxi_mctl_ctl_reg {
@ -72,7 +84,8 @@ struct sunxi_mctl_ctl_reg {
u32 clken; /* 0x0c */
u32 pgsr[2]; /* 0x10 PHY general status registers */
u32 statr; /* 0x18 */
u8 res1[0x14]; /* 0x1c */
u8 res1[0x10]; /* 0x1c */
u32 lp3mr11; /* 0x2c */
u32 mr[4]; /* 0x30 mode registers */
u32 pllgcr; /* 0x40 */
u32 ptr[5]; /* 0x44 PHY timing registers */
@ -120,7 +133,8 @@ struct sunxi_mctl_ctl_reg {
struct { /* 0x300 DATX8 modules*/
u32 mdlr; /* 0x00 master delay line register */
u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
u32 bdlr[12]; /* 0x10 bit delay line registers */
u32 bdlr[11]; /* 0x10 bit delay line registers */
u32 sdlr; /* 0x3c output enable bit delay registers */
u32 gtr; /* 0x40 general timing register */
u32 gcr; /* 0x44 general configuration register */
u32 gsr[3]; /* 0x48 general status registers */

1
arch/arm/include/asm/arch-sunxi/gpio.h
View file

@ -161,6 +161,7 @@ enum sunxi_gpio_number {
#define SUN8I_GPB_UART2 2
#define SUN8I_A33_GPB_UART0 3
#define SUN8I_A83T_GPB_UART0 2
#define SUN8I_V3S_GPB_UART0 3
#define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2

128
arch/arm/include/asm/arch-sunxi/lcdc.h Normal file
View file

@ -0,0 +1,128 @@
/*
* Sunxi platform timing controller register and constant defines
*
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _LCDC_H
#define _LCDC_H
#include <fdtdec.h>
struct sunxi_lcdc_reg {
u32 ctrl; /* 0x00 */
u32 int0; /* 0x04 */
u32 int1; /* 0x08 */
u8 res0[0x04]; /* 0x0c */
u32 tcon0_frm_ctrl; /* 0x10 */
u32 tcon0_frm_seed[6]; /* 0x14 */
u32 tcon0_frm_table[4]; /* 0x2c */
u8 res1[4]; /* 0x3c */
u32 tcon0_ctrl; /* 0x40 */
u32 tcon0_dclk; /* 0x44 */
u32 tcon0_timing_active; /* 0x48 */
u32 tcon0_timing_h; /* 0x4c */
u32 tcon0_timing_v; /* 0x50 */
u32 tcon0_timing_sync; /* 0x54 */
u32 tcon0_hv_intf; /* 0x58 */
u8 res2[0x04]; /* 0x5c */
u32 tcon0_cpu_intf; /* 0x60 */
u32 tcon0_cpu_wr_dat; /* 0x64 */
u32 tcon0_cpu_rd_dat0; /* 0x68 */
u32 tcon0_cpu_rd_dat1; /* 0x6c */
u32 tcon0_ttl_timing0; /* 0x70 */
u32 tcon0_ttl_timing1; /* 0x74 */
u32 tcon0_ttl_timing2; /* 0x78 */
u32 tcon0_ttl_timing3; /* 0x7c */
u32 tcon0_ttl_timing4; /* 0x80 */
u32 tcon0_lvds_intf; /* 0x84 */
u32 tcon0_io_polarity; /* 0x88 */
u32 tcon0_io_tristate; /* 0x8c */
u32 tcon1_ctrl; /* 0x90 */
u32 tcon1_timing_source; /* 0x94 */
u32 tcon1_timing_scale; /* 0x98 */
u32 tcon1_timing_out; /* 0x9c */
u32 tcon1_timing_h; /* 0xa0 */
u32 tcon1_timing_v; /* 0xa4 */
u32 tcon1_timing_sync; /* 0xa8 */
u8 res3[0x44]; /* 0xac */
u32 tcon1_io_polarity; /* 0xf0 */
u32 tcon1_io_tristate; /* 0xf4 */
u8 res4[0x108]; /* 0xf8 */
u32 mux_ctrl; /* 0x200 */
u8 res5[0x1c]; /* 0x204 */
u32 lvds_ana0; /* 0x220 */
u32 lvds_ana1; /* 0x224 */
};
/*
* LCDC register constants.
*/
#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
#ifdef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20)
#else
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */
#endif
#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20)
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16)
#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0)
#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0)
#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4)
#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4)
#ifdef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_LCDC_LVDS_ANA0 0x40040320
#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31)
#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24)
#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20)
#else
#define SUNXI_LCDC_LVDS_ANA0 0x3f310000
#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
#endif
#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
int clk_div, bool for_ext_vga_dac,
int depth, int dclk_phase);
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
bool ext_hvsync, bool is_composite);
#endif /* _LCDC_H */

5
arch/arm/include/asm/arch-sunxi/timer.h
View file

@ -67,7 +67,7 @@ struct sunxi_timer_reg {
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
#ifdef CONFIG_SUNXI_GEN_SUN4I
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
struct sunxi_wdog wdog; /* 0x90 */
/* XXX the following is not accurate for sun5i/sun7i */
struct sunxi_64cnt cnt64; /* 0xa0 */
@ -77,8 +77,7 @@ struct sunxi_timer_reg {
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
#elif defined(CONFIG_SUNXI_GEN_SUN6I)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif

5
arch/arm/include/asm/arch-sunxi/watchdog.h
View file

@ -13,7 +13,10 @@
#define WDT_CTRL_RESTART (0x1 << 0)
#define WDT_CTRL_KEY (0x0a57 << 1)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN5I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
#define WDT_MODE_EN (0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)

1
arch/arm/mach-sunxi/Makefile
View file

@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o
obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o
obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o
endif

19
arch/arm/mach-sunxi/board.c
View file

@ -69,12 +69,14 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I)
#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
@ -82,7 +84,9 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
@ -110,6 +114,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
@ -266,7 +274,7 @@ void board_init_f(ulong dummy)
void reset_cpu(ulong addr)
{
#ifdef CONFIG_SUNXI_GEN_SUN4I
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
@ -278,8 +286,7 @@ void reset_cpu(ulong addr)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
#elif defined(CONFIG_SUNXI_GEN_SUN6I)
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

47
arch/arm/mach-sunxi/clock_sun6i.c
View file

@ -35,6 +35,11 @@ void clock_init_safe(void)
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
#endif
#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
/* Set PLL lock enable bits and switch to old lock mode */
writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
#endif
clock_set_pll1(408000000);
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
@ -145,6 +150,22 @@ void clock_set_pll3(unsigned int clk)
&ccm->pll3_cfg);
}
#ifdef CONFIG_SUNXI_DE2
void clock_set_pll3_factors(int m, int n)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* PLL3 rate = 24000000 * n / m */
writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
&ccm->pll3_cfg);
while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
;
}
#endif
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
{
struct sunxi_ccm_reg * const ccm =
@ -217,7 +238,31 @@ done:
}
#endif
#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
#ifdef CONFIG_SUNXI_DE2
void clock_set_pll10(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int m = 2; /* 12 MHz steps */
if (clk == 0) {
clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
return;
}
/* PLL10 rate = 24000000 * n / m */
writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
&ccm->pll10_cfg);
while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
;
}
#endif
#if defined(CONFIG_MACH_SUN8I_A33) || \
defined(CONFIG_MACH_SUN8I_R40) || \
defined(CONFIG_MACH_SUN50I)
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
{
struct sunxi_ccm_reg * const ccm =

4
arch/arm/mach-sunxi/cpu_info.c
View file

@ -87,6 +87,10 @@ int print_cpuinfo(void)
printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_H3
printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_R40
printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_V3S
printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#elif defined CONFIG_MACH_SUN50I

121
arch/arm/mach-sunxi/dram_sun8i_h3.c
View file

@ -70,6 +70,12 @@ static void mctl_set_bit_delays(struct dram_para *para)
writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
&mctl_ctl->acbdlr[i]);
#ifdef CONFIG_MACH_SUN8I_R40
/* DQSn, DMn, DQn output enable bit delay */
for (i = 0; i < 4; i++)
writel(0x6 << 24, &mctl_ctl->dx[i].sdlr);
#endif
setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
}
@ -86,6 +92,9 @@ enum {
MBUS_PORT_DI = 9,
MBUS_PORT_DE = 10,
MBUS_PORT_DE_CFD = 11,
MBUS_PORT_UNKNOWN1 = 12,
MBUS_PORT_UNKNOWN2 = 13,
MBUS_PORT_UNKNOWN3 = 14,
};
enum {
@ -205,6 +214,42 @@ static void mctl_set_master_priority_h5(void)
MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200);
}
static void mctl_set_master_priority_r40(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
/* enable bandwidth limit windows and set windows size 1us */
writel(399, &mctl_com->tmr);
writel((1 << 16), &mctl_com->bwcr);
/* set cpu high priority */
writel(0x00000001, &mctl_com->mapr);
/* Port 2 is reserved per Allwinner's linux-3.10 source, yet
* they initialise it */
MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
MBUS_CONF( UNUSED, true, HIGHEST, 0, 512, 256, 96);
MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
/*
* The port names are probably wrong, but no correct sources
* are available.
*/
MBUS_CONF( DE, true, HIGH, 0, 128, 48, 0);
MBUS_CONF( DE_CFD, true, HIGH, 0, 384, 256, 0);
MBUS_CONF(UNKNOWN1, true, HIGHEST, 0, 512, 384, 256);
MBUS_CONF(UNKNOWN2, true, HIGHEST, 2, 8192, 6144, 1024);
MBUS_CONF(UNKNOWN3, true, HIGH, 0, 1280, 144, 64);
}
static void mctl_set_master_priority(uint16_t socid)
{
switch (socid) {
@ -217,6 +262,9 @@ static void mctl_set_master_priority(uint16_t socid)
case SOCID_H5:
mctl_set_master_priority_h5();
return;
case SOCID_R40:
mctl_set_master_priority_r40();
return;
}
}
@ -268,6 +316,9 @@ static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
writel(0x0, &mctl_ctl->mr[3]);
if (socid == SOCID_R40)
writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
/* set DRAM timing */
writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
@ -383,7 +434,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
}
}
static void mctl_set_cr(struct dram_para *para)
static void mctl_set_cr(uint16_t socid, struct dram_para *para)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@ -393,6 +444,14 @@ static void mctl_set_cr(struct dram_para *para)
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
MCTL_CR_PAGE_SIZE(para->page_size) |
MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
if (socid == SOCID_R40) {
if (para->dual_rank)
panic("Dual rank memory not supported\n");
/* Mux pin to A15 address line for single rank memory. */
setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
}
}
static void mctl_sys_init(uint16_t socid, struct dram_para *para)
@ -407,14 +466,14 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
if (socid == SOCID_A64)
if (socid == SOCID_A64 || socid == SOCID_R40)
clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
udelay(10);
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
udelay(1000);
if (socid == SOCID_A64) {
if (socid == SOCID_A64 || socid == SOCID_R40) {
clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
clrsetbits_le32(&ccm->dram_clk_cfg,
CCM_DRAMCLK_CFG_DIV_MASK |
@ -459,7 +518,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
unsigned int i;
mctl_set_cr(para);
mctl_set_cr(socid, para);
mctl_set_timing_params(socid, para);
mctl_set_master_priority(socid);
@ -506,6 +565,13 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
(0x1 << 10) | (0x2 << 8));
} else if (socid == SOCID_A64 || socid == SOCID_H5) {
/* dphy & aphy phase select ? */
clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
(0x0 << 10) | (0x3 << 8));
} else if (socid == SOCID_R40) {
/* dx ddr_clk & hdr_clk dynamic mode (tpr13[9] == 0) */
clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
/* dphy & aphy phase select ? */
clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
(0x0 << 10) | (0x3 << 8));
@ -535,6 +601,11 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
/* no PIR_QSGATE for H5 ???? */
} else if (socid == SOCID_R40) {
clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
PIR_DRAMRST | PIR_DRAMINIT);
}
/* detect ranks and bus width */
@ -554,7 +625,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
para->bus_width = 16;
}
mctl_set_cr(para);
mctl_set_cr(socid, para);
udelay(20);
/* re-train */
@ -575,7 +646,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
/* set PGCR3, CKE polarity */
if (socid == SOCID_H3)
writel(0x00aa0060, &mctl_ctl->pgcr[3]);
else if (socid == SOCID_A64 || socid == SOCID_H5)
else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
/* power down zq calibration module for power save */
@ -587,12 +658,12 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
return 0;
}
static void mctl_auto_detect_dram_size(struct dram_para *para)
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
{
/* detect row address bits */
para->page_size = 512;
para->row_bits = 16;
mctl_set_cr(para);
mctl_set_cr(socid, para);
for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
@ -600,7 +671,7 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
/* detect page size */
para->page_size = 8192;
mctl_set_cr(para);
mctl_set_cr(socid, para);
for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
if (mctl_mem_matches(para->page_size))
@ -630,6 +701,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 }
#define SUN8I_R40_DX_READ_DELAYS \
{{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 } }
#define SUN8I_R40_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 } }
#define SUN8I_R40_AC_DELAYS \
{ 0, 0, 3, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0 }
#define SUN50I_A64_DX_READ_DELAYS \
{{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
{ 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
@ -679,6 +766,10 @@ unsigned long sunxi_dram_init(void)
.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
.ac_delays = SUN8I_H3_AC_DELAYS,
#elif defined(CONFIG_MACH_SUN8I_R40)
.dx_read_delays = SUN8I_R40_DX_READ_DELAYS,
.dx_write_delays = SUN8I_R40_DX_WRITE_DELAYS,
.ac_delays = SUN8I_R40_AC_DELAYS,
#elif defined(CONFIG_MACH_SUN50I)
.dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
.dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
@ -696,6 +787,8 @@ unsigned long sunxi_dram_init(void)
*/
#if defined(CONFIG_MACH_SUN8I_H3)
uint16_t socid = SOCID_H3;
#elif defined(CONFIG_MACH_SUN8I_R40)
uint16_t socid = SOCID_R40;
#elif defined(CONFIG_MACH_SUN50I)
uint16_t socid = SOCID_A64;
#elif defined(CONFIG_MACH_SUN50I_H5)
@ -716,9 +809,11 @@ unsigned long sunxi_dram_init(void)
if (socid == SOCID_H3)
writel(0x0c000400, &mctl_ctl->odtcfg);
if (socid == SOCID_A64 || socid == SOCID_H5) {
if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40) {
/* VTF enable (tpr13[8] == 1) */
setbits_le32(&mctl_ctl->vtfcr,
(socid == SOCID_H5 ? 3 : 2) << 8);
(socid != SOCID_A64 ? 3 : 2) << 8);
/* DQ hold disable (tpr13[26] == 1) */
clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
}
@ -726,8 +821,8 @@ unsigned long sunxi_dram_init(void)
setbits_le32(&mctl_com->cccr, 1 << 31);
udelay(10);
mctl_auto_detect_dram_size(&para);
mctl_set_cr(&para);
mctl_auto_detect_dram_size(socid, &para);
mctl_set_cr(socid, &para);
return (1UL << (para.row_bits + 3)) * para.page_size *
(para.dual_rank ? 2 : 1);

7
arch/arm/mach-sunxi/pmic_bus.c
View file

@ -41,6 +41,9 @@ int pmic_bus_init(void)
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
AXP221_INIT_DATA);
# elif defined CONFIG_MACH_SUN8I_R40
/* Nothing. R40 uses the AXP221s in I2C mode */
ret = 0;
# else
ret = rsb_init();
if (ret)
@ -65,6 +68,8 @@ int pmic_bus_read(u8 reg, u8 *data)
#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
# elif defined CONFIG_MACH_SUN8I_R40
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
# else
return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
# endif
@ -80,6 +85,8 @@ int pmic_bus_write(u8 reg, u8 data)
#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
# ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
# elif defined CONFIG_MACH_SUN8I_R40
return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
# else
return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
# endif

72
board/sunxi/Kconfig
View file

@ -58,6 +58,7 @@ config SUNXI_GEN_SUN6I
config MACH_SUNXI_H3_H5
bool
select SUNXI_DE2
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
@ -134,6 +135,24 @@ config MACH_SUN8I_H3
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3s)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@ -144,6 +163,7 @@ config MACH_SUN9I
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SUNXI_DE2
select SUNXI_GEN_SUN6I
select SUNXI_HIGH_SRAM
select SUPPORT_SPL
@ -159,7 +179,12 @@ endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
default y if MACH_SUN8I_A83T
default y if MACH_SUNXI_H3_H5
default y if MACH_SUN8I_R40
default y if MACH_SUN8I_V3S
config RESERVE_ALLWINNER_BOOT0_HEADER
bool "reserve space for Allwinner boot0 header"
@ -194,6 +219,7 @@ config DRAM_TYPE
config DRAM_CLK
int "sunxi dram clock speed"
default 792 if MACH_SUN9I
default 648 if MACH_SUN8I_R40
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default 672 if MACH_SUN50I
@ -215,6 +241,7 @@ config DRAM_ZQ
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 3881979 if MACH_SUN8I_R40
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
---help---
@ -224,6 +251,7 @@ config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_R40
default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
@ -308,9 +336,13 @@ config DRAM_ODT_CORRECTION
endif
config SYS_CLK_FREQ
default 816000000 if MACH_SUN50I
default 1008000000 if MACH_SUN4I
default 1008000000 if MACH_SUN5I
default 1008000000 if MACH_SUN6I
default 912000000 if MACH_SUN7I
default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
default 1008000000 if MACH_SUN8I
default 1008000000 if MACH_SUN9I
default 816000000 if MACH_SUN50I
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
@ -345,6 +377,13 @@ config OLD_SUNXI_KERNEL_COMPAT
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
config MACPWR
string "MAC power pin"
default ""
help
Set the pin used to power the MAC. This takes a string in the format
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config MMC0_CD_PIN
string "Card detect pin for mmc0"
default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
@ -453,7 +492,7 @@ config USB3_VBUS_PIN
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
default n if MACH_SUN6I || MACH_SUN8I
select CMD_I2C
---help---
@ -512,7 +551,12 @@ config AXP_GPIO
config VIDEO
bool "Enable graphical uboot console on HDMI, LCD or VGA"
depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
depends on !MACH_SUN8I_A83T
depends on !MACH_SUNXI_H3_H5
depends on !MACH_SUN8I_R40
depends on !MACH_SUN8I_V3S
depends on !MACH_SUN9I
depends on !MACH_SUN50I
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
@ -658,6 +702,10 @@ config VIDEO_LCD_IF_PARALLEL
config VIDEO_LCD_IF_LVDS
bool
config SUNXI_DE2
bool
default n
choice
prompt "LCD panel support"
@ -706,6 +754,13 @@ config VIDEO_LCD_TL059WV5C0
endchoice
config SATAPWR
string "SATA power pin"
default ""
help
Set the pins used to power the SATA. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
port H.
config GMAC_TX_DELAY
int "GMAC Transmit Clock Delay Chain"
@ -714,7 +769,12 @@ config GMAC_TX_DELAY
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
default 0x4fe00000 if MACH_SUN4I
default 0x4fe00000 if MACH_SUN5I
default 0x4fe00000 if MACH_SUN6I
default 0x4fe00000 if MACH_SUN7I
default 0x4fe00000 if MACH_SUN8I
default 0x2fe00000 if MACH_SUN9I
default 0x4fe00000 if MACH_SUN50I
endif

16
board/sunxi/MAINTAINERS
View file

@ -109,6 +109,12 @@ M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/Ampe_A76_defconfig
BANANAPI M2 ULTRA BOARD
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
F: configs/Bananapi_M2_Ultra_defconfig
F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@free-electrons.com>
S: Maintained
@ -182,6 +188,11 @@ M: Jelle de Jong <jelledejong@powercraft.nl>
S: Maintained
F: configs/Lamobo_R1_defconfig
LICHEEPI-ZERO BOARD
M: Icenowy Zheng <icenowy@aosc.xyz>
S: Maintained
F: configs/LicheePi_Zero_defconfig
LINKSPRITE-PCDUINO BOARD
M: Zoltan Herpai <wigyori@uid0.hu>
S: Maintained
@ -232,6 +243,11 @@ M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
F: configs/nanopi_neo_defconfig
NANOPI-NEO-AIR BOARD
M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
F: configs/nanopi_neo_air_defconfig
NINTENDO NES CLASSIC EDITION BOARD
M: FUKAUMI Naoki <naobsd@gmail.com>
S: Maintained

48
board/sunxi/board.c
View file

@ -80,7 +80,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* add board specific code here */
int board_init(void)
{
__maybe_unused int id_pfr1, ret;
__maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
@ -118,12 +118,14 @@ int board_init(void)
return ret;
#ifdef CONFIG_SATAPWR
gpio_request(CONFIG_SATAPWR, "satapwr");
gpio_direction_output(CONFIG_SATAPWR, 1);
satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
gpio_request(satapwr_pin, "satapwr");
gpio_direction_output(satapwr_pin, 1);
#endif
#ifdef CONFIG_MACPWR
gpio_request(CONFIG_MACPWR, "macpwr");
gpio_direction_output(CONFIG_MACPWR, 1);
macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
gpio_request(macpwr_pin, "macpwr");
gpio_direction_output(macpwr_pin, 1);
#endif
/* Uses dm gpio code so do this here and not in i2c_init_board() */
@ -199,7 +201,8 @@ static void mmc_pinmux_setup(int sdc)
case 1:
pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
if (pins == SUNXI_GPIO_H) {
/* SDC1: PH22-PH-27 */
for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
@ -294,6 +297,17 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
}
#elif defined(CONFIG_MACH_SUN8I_R40)
/* SDC2: PC6-PC15, PC24 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
/* SDC2: PC5-PC6, PC8-PC16 */
for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
@ -320,7 +334,8 @@ static void mmc_pinmux_setup(int sdc)
case 3:
pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
/* SDC3: PI4-PI9 */
for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
@ -394,7 +409,10 @@ int board_mmc_init(bd_t *bis)
void i2c_init_board(void)
{
#ifdef CONFIG_I2C0_ENABLE
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN5I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
clock_twi_onoff(0, 1);
@ -410,7 +428,9 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_I2C1_ENABLE
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
clock_twi_onoff(1, 1);
@ -430,7 +450,9 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_I2C2_ENABLE
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
clock_twi_onoff(2, 1);
@ -454,7 +476,8 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
clock_twi_onoff(3, 1);
#elif defined(CONFIG_MACH_SUN7I)
#elif defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
clock_twi_onoff(3, 1);
@ -462,7 +485,8 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_I2C4_ENABLE
#if defined(CONFIG_MACH_SUN7I)
#if defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
clock_twi_onoff(4, 1);

3
configs/A10-OLinuXino-Lime_defconfig
View file

@ -5,10 +5,10 @@ CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
CONFIG_SYS_CLK_FREQ=912000000
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PC3"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -21,6 +21,7 @@ CONFIG_I2C1_ENABLE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y

2
configs/A10s-OLinuXino-M_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -17,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_AXP152_POWER=y
CONFIG_USB_EHCI_HCD=y

1
configs/A13-OLinuXinoM_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/A13-OLinuXino_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

4
configs/A20-OLinuXino-Lime2_defconfig
View file

@ -5,10 +5,10 @@ CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -25,6 +25,8 @@ CONFIG_NET_ETHADDR_EEPROM=y
CONFIG_NET_ETHADDR_EEPROM_I2C=y
CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
CONFIG_I2C1_ENABLE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y

3
configs/A20-OLinuXino-Lime_defconfig
View file

@ -3,10 +3,10 @@ CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PC3"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -20,6 +20,7 @@ CONFIG_NET_ETHADDR_EEPROM=y
CONFIG_NET_ETHADDR_EEPROM_I2C=y
CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
CONFIG_I2C1_ENABLE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y

3
configs/A20-OLinuXino_MICRO_defconfig
View file

@ -6,10 +6,10 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH11"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -23,6 +23,7 @@ CONFIG_NET_ETHADDR_EEPROM=y
CONFIG_NET_ETHADDR_EEPROM_I2C=y
CONFIG_NET_ETHADDR_EEPROM_I2C_BUS=1
CONFIG_I2C1_ENABLE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y

4
configs/A20-Olimex-SOM-EVB_defconfig
View file

@ -8,10 +8,10 @@ CONFIG_MMC3_PINS="PH"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -21,6 +21,8 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_USB_EHCI_HCD=y

1
configs/Ampe_A76_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

15
configs/Bananapi_M2_Ultra_defconfig Normal file
View file

@ -0,0 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set

4
configs/Bananapi_defconfig
View file

@ -2,12 +2,12 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -18,4 +18,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

4
configs/Bananapro_defconfig
View file

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
@ -9,7 +10,6 @@ CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -20,5 +20,7 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO4_VOLT=2500
CONFIG_USB_EHCI_HCD=y

1
configs/CHIP_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

2
configs/CHIP_pro_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
CONFIG_ENV_IS_IN_UBI=y
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot-env"

2
configs/CSQ_CS908_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -15,6 +14,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y

3
configs/Colombus_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -25,5 +24,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y

3
configs/Cubieboard2_defconfig
View file

@ -3,10 +3,10 @@ CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -16,4 +16,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

3
configs/Cubieboard_defconfig
View file

@ -3,10 +3,10 @@ CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -15,4 +15,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y

4
configs/Cubietruck_defconfig
View file

@ -7,11 +7,11 @@ CONFIG_USB0_VBUS_PIN="PH17"
CONFIG_USB0_VBUS_DET="PH22"
CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PH12"
CONFIG_GMAC_TX_DELAY=1
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPH(12)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -24,6 +24,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y

1
configs/Empire_electronix_d709_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

1
configs/Empire_electronix_m712_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

3
configs/Hummingbird_A31_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -17,5 +16,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y

3
configs/Itead_Ibox_A20_defconfig
View file

@ -3,10 +3,10 @@ CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -16,4 +16,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

5
configs/Lamobo_R1_defconfig
View file

@ -2,12 +2,13 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_SATAPWR="PB3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),SATAPWR=SUNXI_GPB(3)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -17,4 +18,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

12
configs/LicheePi_Zero_defconfig Normal file
View file

@ -0,0 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_NETDEVICES is not set

4
configs/Linksprite_pcDuino3_Nano_defconfig
View file

@ -4,11 +4,11 @@ CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_SATAPWR="PH2"
CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPH(2)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -18,4 +18,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

3
configs/Linksprite_pcDuino3_defconfig
View file

@ -3,10 +3,10 @@ CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
CONFIG_SATAPWR="PH2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPH(2)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -16,4 +16,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Linksprite_pcDuino_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -14,4 +13,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Marsboard_A10_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -12,5 +11,6 @@ CONFIG_SPL=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Mele_A1000G_quad_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -16,6 +15,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300

3
configs/Mele_A1000_defconfig
View file

@ -1,12 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_MACPWR="PH15"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -15,4 +15,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Mele_I7_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -15,6 +14,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300

2
configs/Mele_M3_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -18,4 +17,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Mele_M5_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -18,4 +17,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Mele_M9_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -15,6 +14,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300

4
configs/Orangepi_defconfig
View file

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y
@ -10,7 +11,6 @@ CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -20,4 +20,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

4
configs/Orangepi_mini_defconfig
View file

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_MMC3_CD_PIN="PH11"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
@ -12,7 +13,6 @@ CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -22,4 +22,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/Sinlinx_SinA31s_defconfig
View file

@ -10,7 +10,6 @@ CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -19,5 +18,6 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y

3
configs/Sinovoip_BPI_M2_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -15,6 +14,8 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_ALDO2_VOLT=1800
CONFIG_AXP_DLDO1_VOLT=3000

2
configs/Sinovoip_BPI_M3_defconfig
View file

@ -11,9 +11,9 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_USB0_ID_DET="PH11"
CONFIG_USB1_VBUS_PIN="PD24"
CONFIG_AXP_GPIO=y
CONFIG_SATAPWR="PD25"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set

3
configs/Wits_Pro_A20_DKT_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -21,4 +20,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

2
configs/ba10_tv_box_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -17,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y

1
configs/difrnce_dit4350_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

1
configs/ga10h_v1_1_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/gt90h_v4_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

3
configs/i12-tvbox_defconfig
View file

@ -2,10 +2,10 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -15,4 +15,5 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

1
configs/iNet_D978_rev2_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

2
configs/icnova-a20-swac_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_POWER="PH22"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -23,4 +22,5 @@ CONFIG_CMD_UNZIP=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_SUN7I_GMAC=y
CONFIG_USB_EHCI_HCD=y

1
configs/inet86dz_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/inet98v_rev2_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

3
configs/jesurun_q5_defconfig
View file

@ -2,11 +2,11 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_MACPWR="PH19"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN4I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y

4
configs/mixtile_loftq_defconfig
View file

@ -2,12 +2,12 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MACPWR="PA21"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@ -16,5 +16,7 @@ CONFIG_SPL=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y

1
configs/mk802_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

2
configs/orangepi_plus2e_defconfig
View file

@ -4,10 +4,10 @@ CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="MACPWR=SUNXI_GPD(6)"
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y

3
configs/orangepi_plus_defconfig
View file

@ -4,11 +4,12 @@ CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SATAPWR="PG11"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11),MACPWR=SUNXI_GPD(6)"
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y

1
configs/polaroid_mid2407pxe03_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/polaroid_mid2809pxe04_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/q8_a13_tablet_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set

1
configs/q8_a23_tablet_800x480_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/q8_a33_tablet_1024x600_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/q8_a33_tablet_800x480_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
configs/sun8i_a23_evb_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_USB0_VBUS_DET="axp_vbus_detect"
CONFIG_USB1_VBUS_PIN="PH7"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set

1
drivers/gpio/sunxi_gpio.c
View file

@ -352,6 +352,7 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun8i-a33-pinctrl", a_all),
ID("allwinner,sun8i-a83t-pinctrl", a_all),
ID("allwinner,sun8i-h3-pinctrl", a_all),
ID("allwinner,sun8i-r40-pinctrl", a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
ID("allwinner,sun6i-a31-r-pinctrl", l_2),
ID("allwinner,sun8i-a23-r-pinctrl", l_1),

17
drivers/net/Kconfig
View file

@ -149,6 +149,12 @@ config PCH_GBE
This MAC is present in Intel Platform Controller Hub EG20T. It
supports 10/100/1000 Mbps operation.
config RGMII
bool "Enable RGMII"
help
Enable the support of the Reduced Gigabit Media-Independent
Interface (RGMII).
config RTL8139
bool "Realtek 8139 series Ethernet controller driver"
help
@ -161,6 +167,17 @@ config RTL8169
This driver supports Realtek 8169 series gigabit ethernet family of
PCI/PCIe chipsets/adapters.
config SUN7I_GMAC
bool "Enable Allwinner GMAC Ethernet support"
help
Enable the support for Sun7i GMAC Ethernet controller
config SUN4I_EMAC
bool "Allwinner Sun4i Ethernet MAC support"
depends on DM_ETH
help
This driver supports the Allwinner based SUN4I Ethernet MAC.
config SUN8I_EMAC
bool "Allwinner Sun8i Ethernet MAC support"
depends on DM_ETH

16
drivers/power/Kconfig
View file

@ -10,7 +10,7 @@ choice
prompt "Select Sunxi PMIC Variant"
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
default AXP818_POWER if MACH_SUN8I_A83T
default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
@ -37,7 +37,7 @@ config AXP209_POWER
config AXP221_POWER
bool "axp221 / axp223 pmic support"
depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
select CMD_POWEROFF
---help---
Select this to enable support for the axp221/axp223 pmic found on most
@ -70,7 +70,7 @@ endchoice
config AXP_DCDC1_VOLT
int "axp pmic dcdc1 voltage"
depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 3300 if AXP818_POWER
default 3300 if AXP818_POWER || MACH_SUN8I_R40
default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
@ -97,6 +97,7 @@ config AXP_DCDC2_VOLT
On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
On A80 boards dcdc2 powers the GPU and can be left off.
On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On R40 boards dcdc2 is VDD-CPU and should be 1.1V
config AXP_DCDC3_VOLT
int "axp pmic dcdc3 voltage"
@ -104,6 +105,7 @@ config AXP_DCDC3_VOLT
default 900 if AXP809_POWER || AXP818_POWER
default 1500 if AXP152_POWER
default 1250 if AXP209_POWER
default 1100 if MACH_SUN8I_R40
default 1200 if MACH_SUN6I || MACH_SUN8I
---help---
Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to
@ -114,6 +116,7 @@ config AXP_DCDC3_VOLT
On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
config AXP_DCDC4_VOLT
int "axp pmic dcdc4 voltage"
@ -138,13 +141,13 @@ config AXP_DCDC5_VOLT
---help---
Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
disable dcdc5.
On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and
On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and
should be 1.5V, 1.35V if DDR3L is used.
config AXP_ALDO1_VOLT
int "axp pmic (a)ldo1 voltage"
depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
default 0 if MACH_SUN6I
default 0 if MACH_SUN6I || MACH_SUN8I_R40
default 1800 if MACH_SUN8I_A83T
default 3000 if MACH_SUN8I || MACH_SUN9I
---help---
@ -183,7 +186,8 @@ config AXP_ALDO3_VOLT
Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
disable aldo3.
On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should
be 3.0V.
On A80 boards aldo3 is normally not used.
On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
3.0V.

11
drivers/serial/Kconfig
View file

@ -44,6 +44,17 @@ config SPL_SERIAL_PRESENT
This option enables the full UART in SPL, so if is it disabled,
the full UART driver will be omitted, thus saving space.
config CONS_INDEX
int "UART used for console"
depends on ARCH_SUNXI
default 2 if MACH_SUN5I
default 5 if MACH_SUN8I_A23 || MACH_SUN8I_A33
default 1
help
Configures the console index.
For Allwinner SoC., default values are 2 for SUN5I and 5 for A23/A33.
Otherwise, the index equals 1.
config DM_SERIAL
bool "Enable Driver Model for serial drivers"
depends on DM

2
drivers/video/Makefile
View file

@ -51,7 +51,6 @@ obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_VIDEO_VESA) += vesa.o
@ -64,3 +63,4 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-y += bridge/
obj-y += sunxi/

8
drivers/video/sunxi/Makefile Normal file
View file

@ -0,0 +1,8 @@
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o

209
drivers/video/sunxi/lcdc.c Normal file
View file

@ -0,0 +1,209 @@
/*
* Timing controller driver for Allwinner SoCs.
*
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/lcdc.h>
#include <asm/io.h>
static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
{
int delay;
delay = mode->vfront_porch.typ + mode->vsync_len.typ +
mode->vback_porch.typ;
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
delay /= 2;
if (tcon == 1)
delay -= 2;
return (delay > 30) ? 30 : delay;
}
void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
{
/* Init lcdc */
writel(0, &lcdc->ctrl); /* Disable tcon */
writel(0, &lcdc->int0); /* Disable all interrupts */
/* Disable tcon0 dot clock */
clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
/* Set all io lines to tristate */
writel(0xffffffff, &lcdc->tcon0_io_tristate);
writel(0xffffffff, &lcdc->tcon1_io_tristate);
}
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
{
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
if (depth == 18)
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
#else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
udelay(1); /* delay at least 120 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
#endif
#endif
}
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
int clk_div, bool for_ext_vga_dac,
int depth, int dclk_phase)
{
int bp, clk_delay, total, val;
#ifndef CONFIG_SUNXI_DE2
/* Use tcon0 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
#endif
clk_delay = lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
writel(SUNXI_LCDC_X(mode->hactive.typ) |
SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);
bp = mode->hsync_len.typ + mode->hback_porch.typ;
total = mode->hactive.typ + mode->hfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
bp = mode->vsync_len.typ + mode->vback_porch.typ;
total = mode->vactive.typ + mode->vfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);
writel(0, &lcdc->tcon0_hv_intf);
writel(0, &lcdc->tcon0_cpu_intf);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (depth == 18) ? 1 : 0;
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif
if (depth == 18 || depth == 16) {
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
writel(((depth == 18) ?
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
&lcdc->tcon0_frm_ctrl);
}
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
if (for_ext_vga_dac)
val = 0;
#endif
writel(val, &lcdc->tcon0_io_polarity);
writel(0, &lcdc->tcon0_io_tristate);
}
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
const struct display_timing *mode,
bool ext_hvsync, bool is_composite)
{
int bp, clk_delay, total, val, yres;
#ifndef CONFIG_SUNXI_DE2
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
#endif
clk_delay = lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
((mode->flags & DISPLAY_FLAGS_INTERLACED) ?
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
yres = mode->vactive.typ;
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
yres /= 2;
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_source);
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_scale);
writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_out);
bp = mode->hsync_len.typ + mode->hback_porch.typ;
total = mode->hactive.typ + mode->hfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
bp = mode->vsync_len.typ + mode->vback_porch.typ;
total = mode->vactive.typ + mode->vfront_porch.typ + bp;
if (!(mode->flags & DISPLAY_FLAGS_INTERLACED))
total *= 2;
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);
if (ext_hvsync) {
val = 0;
if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
writel(val, &lcdc->tcon1_io_polarity);
clrbits_le32(&lcdc->tcon1_io_tristate,
SUNXI_LCDC_TCON_VSYNC_MASK |
SUNXI_LCDC_TCON_HSYNC_MASK);
}
#ifdef CONFIG_MACH_SUN5I
if (is_composite)
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
SUNXI_LCDC_MUX_CTRL_SRC0(1));
#endif
}

220
drivers/video/sunxi_display.c → drivers/video/sunxi/sunxi_display.c
View file

@ -12,6 +12,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
#include <asm/arch/gpio.h>
#include <asm/arch/lcdc.h>
#include <asm/arch/pwm.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
@ -23,10 +24,10 @@
#include <i2c.h>
#include <malloc.h>
#include <video_fb.h>
#include "videomodes.h"
#include "anx9804.h"
#include "hitachi_tx18d42vm_lcd.h"
#include "ssd2828.h"
#include "../videomodes.h"
#include "../anx9804.h"
#include "../hitachi_tx18d42vm_lcd.h"
#include "../ssd2828.h"
#ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
#define PWM_ON 0
@ -650,45 +651,7 @@ static void sunxi_lcdc_init(void)
#endif
#endif
/* Init lcdc */
writel(0, &lcdc->ctrl); /* Disable tcon */
writel(0, &lcdc->int0); /* Disable all interrupts */
/* Disable tcon0 dot clock */
clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
/* Set all io lines to tristate */
writel(0xffffffff, &lcdc->tcon0_io_tristate);
writel(0xffffffff, &lcdc->tcon1_io_tristate);
}
static void sunxi_lcdc_enable(void)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
if (sunxi_display.depth == 18)
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
#else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
udelay(1); /* delay at least 120 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
#endif
#endif
lcdc_init(lcdc);
}
static void sunxi_lcdc_panel_enable(void)
@ -758,17 +721,31 @@ static void sunxi_lcdc_backlight_enable(void)
gpio_direction_output(pin, PWM_ON);
}
static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
static void sunxi_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
struct display_timing *timing)
{
int delay;
timing->pixelclock.typ = mode->pixclock_khz * 1000;
delay = mode->lower_margin + mode->vsync_len + mode->upper_margin;
timing->hactive.typ = mode->xres;
timing->hfront_porch.typ = mode->right_margin;
timing->hback_porch.typ = mode->left_margin;
timing->hsync_len.typ = mode->hsync_len;
timing->vactive.typ = mode->yres;
timing->vfront_porch.typ = mode->lower_margin;
timing->vback_porch.typ = mode->upper_margin;
timing->vsync_len.typ = mode->vsync_len;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else
timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
else
timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
if (mode->vmode == FB_VMODE_INTERLACED)
delay /= 2;
if (tcon == 1)
delay -= 2;
return (delay > 30) ? 30 : delay;
timing->flags |= DISPLAY_FLAGS_INTERLACED;
}
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
@ -776,7 +753,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;
int clk_div, clk_double, pin;
struct display_timing timing;
#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
@ -796,73 +774,9 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
/* Use tcon0 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
clk_delay = sunxi_lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
&lcdc->tcon0_timing_active);
bp = mode->hsync_len + mode->left_margin;
total = mode->xres + mode->right_margin + bp;
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon0_timing_sync);
writel(0, &lcdc->tcon0_hv_intf);
writel(0, &lcdc->tcon0_cpu_intf);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (sunxi_display.depth == 18) ? 1 : 0;
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif
if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
writel(((sunxi_display.depth == 18) ?
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
&lcdc->tcon0_frm_ctrl);
}
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
if (for_ext_vga_dac)
val = 0;
#endif
writel(val, &lcdc->tcon0_io_polarity);
writel(0, &lcdc->tcon0_io_tristate);
sunxi_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
}
#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
@ -872,65 +786,17 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, total, val, yres;
struct display_timing timing;
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
((mode->vmode == FB_VMODE_INTERLACED) ?
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
yres = mode->yres;
if (mode->vmode == FB_VMODE_INTERLACED)
yres /= 2;
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_source);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_scale);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_out);
bp = mode->hsync_len + mode->left_margin;
total = mode->xres + mode->right_margin + bp;
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
if (mode->vmode == FB_VMODE_NONINTERLACED)
total *= 2;
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon1_timing_sync);
sunxi_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
sunxi_is_composite());
if (use_portd_hvsync) {
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
val = 0;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
writel(val, &lcdc->tcon1_io_polarity);
clrbits_le32(&lcdc->tcon1_io_tristate,
SUNXI_LCDC_TCON_VSYNC_MASK |
SUNXI_LCDC_TCON_HSYNC_MASK);
}
#ifdef CONFIG_MACH_SUN5I
if (sunxi_is_composite())
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
SUNXI_LCDC_MUX_CTRL_SRC0(1));
#endif
sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
}
#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
@ -1212,6 +1078,8 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
unsigned int address)
{
int __maybe_unused clk_div, clk_double;
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
switch (sunxi_display.monitor) {
case sunxi_monitor_none:
@ -1223,7 +1091,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
sunxi_hdmi_mode_set(mode, clk_div, clk_double);
sunxi_composer_enable();
sunxi_lcdc_enable();
lcdc_enable(lcdc, sunxi_display.depth);
sunxi_hdmi_enable();
#endif
break;
@ -1253,7 +1121,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon0_mode_set(mode, false);
sunxi_composer_enable();
sunxi_lcdc_enable();
lcdc_enable(lcdc, sunxi_display.depth);
#ifdef CONFIG_VIDEO_LCD_SSD2828
sunxi_ssd2828_init(mode);
#endif
@ -1265,13 +1133,13 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
sunxi_tvencoder_mode_set();
sunxi_composer_enable();
sunxi_lcdc_enable();
lcdc_enable(lcdc, sunxi_display.depth);
sunxi_tvencoder_enable();
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon0_mode_set(mode, true);
sunxi_composer_enable();
sunxi_lcdc_enable();
lcdc_enable(lcdc, sunxi_display.depth);
sunxi_vga_external_dac_enable();
#endif
break;
@ -1284,7 +1152,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
sunxi_tvencoder_mode_set();
sunxi_composer_enable();
sunxi_lcdc_enable();
lcdc_enable(lcdc, sunxi_display.depth);
sunxi_tvencoder_enable();
#endif
break;

2
include/configs/sun8i.h
View file

@ -21,6 +21,8 @@
#define CONFIG_SUNXI_USB_PHYS 4
#elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS 3
#elif defined CONFIG_MACH_SUN8I_V3S
#define CONFIG_SUNXI_USB_PHYS 1
#else
#define CONFIG_SUNXI_USB_PHYS 2
#endif

41
include/configs/sunxi-common.h
View file

@ -69,7 +69,12 @@
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
/* V3s do not have enough memory to place code at 0x4a000000 */
#ifndef CONFIG_MACH_SUN8I_V3S
#define CONFIG_SYS_TEXT_BASE 0x4a000000
#else
#define CONFIG_SYS_TEXT_BASE 0x42e00000
#endif
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
@ -146,8 +151,13 @@
#define CONFIG_ENV_SIZE (128 << 10)
#endif
#ifndef CONFIG_MACH_SUN8I_V3S
/* 64MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
#else
/* 2MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
#endif
/*
* Miscellaneous configurable options
@ -231,10 +241,6 @@ extern int soft_i2c_gpio_scl;
defined CONFIG_SY8106A_POWER
#endif
#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 1 /* UART0 */
#endif
#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
#if CONFIG_CONS_INDEX == 1
#ifdef CONFIG_MACH_SUN9I
@ -344,6 +350,7 @@ extern int soft_i2c_gpio_scl;
* Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
* Align the initrd to a 2MB page.
*/
#define BOOTM_SIZE __stringify(0xa000000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000))
#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000))
@ -356,16 +363,30 @@ extern int soft_i2c_gpio_scl;
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
#ifndef CONFIG_MACH_SUN8I_V3S
#define BOOTM_SIZE __stringify(0xa000000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
#else
/*
* 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
* 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
#define BOOTM_SIZE __stringify(0x2e00000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
#endif
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0xa000000\0" \
"bootm_size=" BOOTM_SIZE "\0" \
"kernel_addr_r=" KERNEL_ADDR_R "\0" \
"fdt_addr_r=" FDT_ADDR_R "\0" \
"scriptaddr=" SCRIPT_ADDR_R "\0" \
@ -476,11 +497,17 @@ extern int soft_i2c_gpio_scl;
CONSOLE_STDIN_SETTINGS \
CONSOLE_STDOUT_SETTINGS
#ifdef CONFIG_ARM64
#define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#else
#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
DFU_ALT_INFO_RAM \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"fdtfile=" FDTFILE "\0" \
"console=ttyS0,115200\0" \
SUNXI_MTDIDS_DEFAULT \
SUNXI_MTDPARTS_DEFAULT \

107
include/dt-bindings/clock/sun8i-v3s-ccu.h Normal file
View file

@ -0,0 +1,107 @@
/*
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun8i-h3-ccu.h, which is:
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
#define CLK_CPU 14
#define CLK_BUS_CE 20
#define CLK_BUS_DMA 21
#define CLK_BUS_MMC0 22
#define CLK_BUS_MMC1 23
#define CLK_BUS_MMC2 24
#define CLK_BUS_DRAM 25
#define CLK_BUS_EMAC 26
#define CLK_BUS_HSTIMER 27
#define CLK_BUS_SPI0 28
#define CLK_BUS_OTG 29
#define CLK_BUS_EHCI0 30
#define CLK_BUS_OHCI0 31
#define CLK_BUS_VE 32
#define CLK_BUS_TCON0 33
#define CLK_BUS_CSI 34
#define CLK_BUS_DE 35
#define CLK_BUS_CODEC 36
#define CLK_BUS_PIO 37
#define CLK_BUS_I2C0 38
#define CLK_BUS_I2C1 39
#define CLK_BUS_UART0 40
#define CLK_BUS_UART1 41
#define CLK_BUS_UART2 42
#define CLK_BUS_EPHY 43
#define CLK_BUS_DBG 44
#define CLK_MMC0 45
#define CLK_MMC0_SAMPLE 46
#define CLK_MMC0_OUTPUT 47
#define CLK_MMC1 48
#define CLK_MMC1_SAMPLE 49
#define CLK_MMC1_OUTPUT 50
#define CLK_MMC2 51
#define CLK_MMC2_SAMPLE 52
#define CLK_MMC2_OUTPUT 53
#define CLK_CE 54
#define CLK_SPI0 55
#define CLK_USB_PHY0 56
#define CLK_USB_OHCI0 57
#define CLK_DRAM_VE 59
#define CLK_DRAM_CSI 60
#define CLK_DRAM_EHCI 61
#define CLK_DRAM_OHCI 62
#define CLK_DE 63
#define CLK_TCON0 64
#define CLK_CSI_MISC 65
#define CLK_CSI0_MCLK 66
#define CLK_CSI1_SCLK 67
#define CLK_CSI1_MCLK 68
#define CLK_VE 69
#define CLK_AC_DIG 70
#define CLK_AVS 71
#define CLK_MIPI_CSI 73
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */

78
include/dt-bindings/reset/sun8i-v3s-ccu.h Normal file
View file

@ -0,0 +1,78 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun8i-v3s-ccu.h, which is
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_
#define _DT_BINDINGS_RST_SUN8I_V3S_H_
#define RST_USB_PHY0 0
#define RST_MBUS 1
#define RST_BUS_CE 5
#define RST_BUS_DMA 6
#define RST_BUS_MMC0 7
#define RST_BUS_MMC1 8
#define RST_BUS_MMC2 9
#define RST_BUS_DRAM 11
#define RST_BUS_EMAC 12
#define RST_BUS_HSTIMER 14
#define RST_BUS_SPI0 15
#define RST_BUS_OTG 17
#define RST_BUS_EHCI0 18
#define RST_BUS_OHCI0 22
#define RST_BUS_VE 26
#define RST_BUS_TCON0 27
#define RST_BUS_CSI 30
#define RST_BUS_DE 34
#define RST_BUS_DBG 38
#define RST_BUS_EPHY 39
#define RST_BUS_CODEC 40
#define RST_BUS_I2C0 46
#define RST_BUS_I2C1 47
#define RST_BUS_UART0 49
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */