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at91sam9/at91cap: fix CONFIG_SYS_HZ to 1000
The timer has been rewrote with a precision at ~0,18% Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Tested-by: Sergey Lapin <slapin@ossfans.org> Tested-by: Eric BENARD <ebenard@free.fr>
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f0a2c7b4b6
commit
6ebff365eb
8 changed files with 51 additions and 45 deletions
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@ -27,7 +27,9 @@
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#include <asm/arch/at91_pit.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/io.h>
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#include <div64.h>
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/*
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* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
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@ -36,11 +38,26 @@
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#define TIMER_LOAD_VAL 0xfffff
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#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
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#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
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#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
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#define TICKS_TO_USEC(ticks) ((ticks) / 6)
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ulong get_timer_masked(void);
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ulong resettime;
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static ulong timestamp;
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static ulong lastinc;
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static ulong timer_freq;
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, timer_freq);
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return tick;
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}
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static inline unsigned long long usec_to_tick(unsigned long long usec)
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{
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usec *= timer_freq;
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do_div(usec, 1000000);
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return usec;
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}
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/* nothing really to do with interrupts, just starts up a counter. */
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int timer_init(void)
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@ -56,41 +73,49 @@ int timer_init(void)
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reset_timer_masked();
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timer_freq = get_mck_clk_rate() >> 4;
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return 0;
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}
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/*
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* timer without interrupts
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*/
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static inline ulong get_timer_raw(void)
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unsigned long long get_ticks(void)
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{
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ulong now = READ_TIMER;
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if (now >= resettime)
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return now - resettime;
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else
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return 0xFFFFFFFFUL - (resettime - now) ;
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if (now >= lastinc) /* normal mode (non roll) */
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/* move stamp forward with absolut diff ticks */
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timestamp += (now - lastinc);
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else /* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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lastinc = now;
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return timestamp;
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}
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void reset_timer_masked(void)
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{
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resettime = READ_TIMER;
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/* reset time */
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lastinc = READ_TIMER; /* capture current incrementer value time */
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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ulong get_timer_masked(void)
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{
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return TICKS_TO_USEC(get_timer_raw());
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return tick_to_time(get_ticks());
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}
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void udelay_masked(unsigned long usec)
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void udelay(unsigned long usec)
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{
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ulong tmp;
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unsigned long long tmp;
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ulong tmo;
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tmp = get_timer(0);
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while (get_timer(tmp) < usec) /* our timer works in usecs */
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; /* NOP */
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tmo = usec_to_tick(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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}
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void reset_timer(void)
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@ -100,26 +125,7 @@ void reset_timer(void)
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ulong get_timer(ulong base)
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{
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ulong now = get_timer_masked();
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if (now >= base)
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return now - base;
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else
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return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ;
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}
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void udelay(unsigned long usec)
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{
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udelay_masked(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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return get_timer_masked () - base;
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}
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/*
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@ -28,7 +28,7 @@
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
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#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */
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@ -30,7 +30,7 @@
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/* ARM asynchronous clock */
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#define AT91_CPU_NAME "AT91CAP9"
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#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */
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@ -29,7 +29,7 @@
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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@ -30,7 +30,7 @@
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/* ARM asynchronous clock */
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#define AT91_CPU_NAME "AT91SAM9261"
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#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
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@ -30,7 +30,7 @@
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/* ARM asynchronous clock */
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#define AT91_CPU_NAME "AT91SAM9263"
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#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
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#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
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@ -30,7 +30,7 @@
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/* ARM asynchronous clock */
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#define AT91_CPU_NAME "AT91SAM9RL"
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#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
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@ -38,7 +38,7 @@
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#define MAIN_PLL_DIV 2 /* 2 or 4 */
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#define AT91_MAIN_CLOCK 18432000
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#define CONFIG_SYS_HZ 1000000
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
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