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https://github.com/AsahiLinux/u-boot
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Add PPC4xx-HCU4 and HCU5 boards: HCU4 files
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
This commit is contained in:
Niklaus Giger
Stefan Roese
parent
e8397fc78c
commit
6e5de26c6e
1 changed files with 393 additions and 0 deletions
393
board/netstal/hcu4/hcu4.c
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393
board/netstal/hcu4/hcu4.c
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/*
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*(C) Copyright 2005-2007 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm-ppc/u-boot.h>
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#include "../common/nm_bsp.c"
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DECLARE_GLOBAL_DATA_PTR;
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void sysLedSet(u32 value);
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long int spd_sdram(int(read_spd)(uint addr))
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#ifdef CONFIG_SPD_EEPROM
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#define DEBUG
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#endif
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#if defined(DEBUG)
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void show_sdram_registers(void);
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#endif
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/*
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* This function is run very early, out of flash, and before devices are
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* initialized. It is called by lib_ppc/board.c:board_init_f by virtue
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* of being in the init_sequence array.
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*
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* The SDRAM has been initialized already -- start.S:start called
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* init.S:init_sdram early on -- but it is not yet being used for
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* anything, not even stack. So be careful.
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*/
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#define CPC0_CR0 0xb1 /* Chip control register 0 */
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#define CPC0_CR1 0xb2 /* Chip control register 1 */
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/* Attention: If you want 1 microsecs times from the external oscillator
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* use 0x00804051. But this causes problems with u-boot and linux!
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*/
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#define CPC0_CR1_VALUE 0x00004051
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#define CPC0_ECR 0xaa /* Edge condition register */
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#define EBC0_CFG 0x23 /* External Peripheral Control Register */
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#define CPC0_EIRR 0xb6 /* External Interrupt Register */
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------+
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| Interrupt controller setup for the HCU4 board.
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| Note: IRQ 0-15 405GP internally generated; high; level sensitive
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| IRQ 16 405GP internally generated; low; level sensitive
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| IRQ 17-24 RESERVED/UNUSED
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| IRQ 31 (EXT IRQ 6) (unused)
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+-------------------------------------------------------------------*/
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
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mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
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mtdcr (uictr, 0x10000000); /* set int trigger levels */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
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mtdcr(CPC0_ECR, 0x60606000);
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mtdcr(CPC0_EIRR, 0x7c000000);
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return 0;
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}
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#ifdef CONFIG_BOARD_PRE_INIT
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int board_pre_init (void)
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{
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return board_early_init_f ();
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}
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#endif
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enum {
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/* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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int checkboard (void)
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{
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#define HCU_MACH_VERSIONS_REGISTER ( 0x7C000000 + 0xF00000 )
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unsigned j;
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uint16_t *boardVersReg = (uint16_t *) HCU_MACH_VERSIONS_REGISTER;
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uint16_t generation = *boardVersReg & 0xf0;
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uint16_t index = *boardVersReg & 0x0f;
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/* Force /RTS to active. The board it not wired quite
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correctly to use cts/rtc flow control, so just force the
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/RST active and forget about it. */
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writeb (readb (0xef600404) | 0x03, 0xef600404);
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printf ("\nNetstal Maschinen AG ");
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if (generation == HW_GENERATION_HCU3)
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printf ("HCU3: index %d\n\n", index);
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else if (generation == HW_GENERATION_HCU4)
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printf ("HCU4: index %d\n\n", index);
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/* GPIO here noch nicht richtig initialisert !!! */
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sysLedSet(0);
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for (j=0; j < 7;j++) {
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sysLedSet(1 << j);
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udelay(50*1000);
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}
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return 0;
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}
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u32 sysLedGet(void)
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{
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return( ~( (*(u32 *)GPIO0_OR)) >> 23) & 0xff;
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}
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void sysLedSet(u32 value /* value to place in LEDs */)
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{
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u32 tmp = ~value;
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u32 *ledReg;
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tmp = (tmp << 23) | 0x7FFFFF;
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ledReg = (u32 *)GPIO0_OR;
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*ledReg = tmp;
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}
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/*
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* sdram_init - Dummy implementation for start.S, spd_sdram or initdram
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* used for HCUx
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*/
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void sdram_init(void)
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{
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return;
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}
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#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
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#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); }
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#if defined(DEBUG)
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void show_sdram_registers(void)
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{
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u32 value;
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printf ("SDRAM Controller Registers --\n");
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mfsdram(value, mem_mcopt1);
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printf (" SDRAM0_CFG : 0x%08x\n", value);
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mfsdram(value, mem_status);
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printf (" SDRAM0_STATUS: 0x%08x\n", value);
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mfsdram(value, mem_mb0cf);
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printf (" SDRAM0_B0CR : 0x%08x\n", value);
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mfsdram(value, mem_mb1cf);
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printf (" SDRAM0_B1CR : 0x%08x\n", value);
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mfsdram(value, mem_sdtr1);
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printf (" SDRAM0_TR : 0x%08x\n", value);
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mfsdram(value, mem_rtr);
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printf (" SDRAM0_RTR : 0x%08x\n", value);
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}
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#endif
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#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
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/*
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* this is even after checkboard. It returns the size of the SDRAM
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* that we have installed. This function is called by board_init_f
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* in lib_ppc/board.c to initialize the memory and return what I
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* found. These are default value, which will be overridden later.
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*/
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long int fixed_hcu4_sdram (int board_type)
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{
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#ifdef DEBUG
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printf (__FUNCTION__);
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#endif
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/* disable memory controller */
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mtdcr (memcfga, mem_mcopt1);
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mtdcr (memcfgd, 0x00000000);
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udelay (500);
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/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
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mtdcr (memcfga, mem_besra);
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mtdcr (memcfgd, 0xffffffff);
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/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
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mtdcr (memcfga, mem_besrb);
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mtdcr (memcfgd, 0xffffffff);
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/* Clear SDRAM0_ECCCFG (disable ECC) */
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mtdcr (memcfga, mem_ecccf);
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mtdcr (memcfgd, 0x00000000);
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/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
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mtdcr (memcfga, mem_eccerr);
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mtdcr (memcfgd, 0xffffffff);
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/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
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* TODO ngngng
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*/
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mtdcr (memcfga, mem_sdtr1);
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mtdcr (memcfgd, 0x008a4015);
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/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
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* TODO ngngng
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*/
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mtdcr (memcfga, mem_mb0cf);
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mtdcr (memcfgd, 0x00062001);
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/* refresh timer = 0x400 */
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mtdcr (memcfga, mem_rtr);
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mtdcr (memcfgd, 0x04000000);
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/* Power management idle timer set to the default. */
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mtdcr (memcfga, mem_pmit);
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mtdcr (memcfgd, 0x07c00000);
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udelay (500);
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/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
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mtdcr (memcfga, mem_mcopt1);
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mtdcr (memcfgd, 0x90800000);
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#ifdef DEBUG
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printf ("%s: done\n", __FUNCTION__);
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#endif
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return SDRAM_LEN;
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}
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/*---------------------------------------------------------------------------+
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* getSerialNr
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*---------------------------------------------------------------------------*/
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static u32 getSerialNr(void)
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{
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u32 *serial = (u32 *)CFG_FLASH_BASE;
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if (*serial == 0xffffffff) {
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return get_ticks();
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}
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return *serial;
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}
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/*---------------------------------------------------------------------------+
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* misc_init_r.
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*---------------------------------------------------------------------------*/
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int misc_init_r(void)
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{
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char *s = getenv("ethaddr");
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char *e;
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int i;
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u32 serial = getSerialNr();
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for (i = 0; i < 6; ++i) {
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gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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if (gd->bd->bi_enetaddr[3] == 0 &&
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gd->bd->bi_enetaddr[4] == 0 &&
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gd->bd->bi_enetaddr[5] == 0) {
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char ethaddr[22];
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/* [0..3] Must be in sync with CONFIG_ETHADDR */
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gd->bd->bi_enetaddr[0] = 0x00;
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gd->bd->bi_enetaddr[1] = 0x60;
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gd->bd->bi_enetaddr[2] = 0x13;
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gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
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gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
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gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff;
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sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
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gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
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gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
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gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
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printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
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ethaddr, serial);
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setenv ("ethaddr", ethaddr);
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}
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return 0;
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}
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#define DO_UGLY_SDRAM_WORKAROUND
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#ifdef DO_UGLY_SDRAM_WORKAROUND
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#include "i2c.h"
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void set_spd_default_value(unsigned int spd_addr,uchar def_val)
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{
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uchar value;
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int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
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if (res == 0 && value == 0xff) {
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res = i2c_write(SPD_EEPROM_ADDRESS,
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spd_addr, 1, &def_val, 1) ;
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#ifdef DEBUG
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printf("%s: Setting spd offset %3d to %3d res %d\n",
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__FUNCTION__, spd_addr, def_val, res);
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#endif
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}
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}
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#endif
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long int initdram(int board_type)
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{
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long dram_size = 0;
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#if !defined(CONFIG_SPD_EEPROM)
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dram_size = fixed_hcu4_sdram();
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#else
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#ifdef DO_UGLY_SDRAM_WORKAROUND
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/* Workaround if you have no working I2C-EEPROM-SPD-configuration */
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i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
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set_spd_default_value(2, 4); /* SDRAM Type */
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set_spd_default_value(7, 0); /* module width, high byte */
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set_spd_default_value(12, 1); /* Refresh or 0x81 */
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/* Only correct for HCU3 with 32 MB RAM*/
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/* Number of bytes used by module manufacturer */
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set_spd_default_value( 0, 128);
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set_spd_default_value( 1, 11 ); /* Total SPD memory size */
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set_spd_default_value( 2, 4 ); /* Memory type */
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set_spd_default_value( 3, 12 ); /* Number of row address bits */
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set_spd_default_value( 4, 9 ); /* Number of column address bits */
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set_spd_default_value( 5, 1 ); /* Number of module rows */
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set_spd_default_value( 6, 32 ); /* Module data width, LSB */
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set_spd_default_value( 7, 0 ); /* Module data width, MSB */
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set_spd_default_value( 8, 1 ); /* Module interface signal levels */
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/* SDRAM cycle time for highest CL (Tclk) */
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set_spd_default_value( 9, 112);
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/* SDRAM access time from clock for highest CL (Tac) */
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set_spd_default_value(10, 84 );
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set_spd_default_value(11, 2 ); /* Module configuration type */
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set_spd_default_value(12, 128); /* Refresh rate/type */
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set_spd_default_value(13, 16 ); /* Primary SDRAM width */
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set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
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/* SDRAM device attributes, min clock delay for back to back */
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/*random column addresses (Tccd) */
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set_spd_default_value(15, 1 );
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/* SDRAM device attributes, burst lengths supported */
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set_spd_default_value(16, 143);
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/* SDRAM device attributes, number of banks on SDRAM device */
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set_spd_default_value(17, 4 );
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/* SDRAM device attributes, CAS latency */
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set_spd_default_value(18, 6 );
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/* SDRAM device attributes, CS latency */
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set_spd_default_value(19, 1 );
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/* SDRAM device attributes, WE latency */
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set_spd_default_value(20, 1 );
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set_spd_default_value(21, 0 ); /* SDRAM module attributes */
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/* SDRAM device attributes, general */
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set_spd_default_value(22, 14 );
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/* SDRAM cycle time for 2nd highest CL (Tclk) */
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set_spd_default_value(23, 117);
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/* SDRAM access time from clock for2nd highest CL (Tac) */
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set_spd_default_value(24, 84 );
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/* SDRAM cycle time for 3rd highest CL (Tclk) */
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set_spd_default_value(25, 0 );
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/* SDRAM access time from clock for3rd highest CL (Tac) */
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set_spd_default_value(26, 0 );
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set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
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/* Minimum row active to row active delay (Trrd) */
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set_spd_default_value(28, 14 );
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set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
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set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
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set_spd_default_value(31, 8 ); /* Module bank density */
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/* Command and Address signal input setup time */
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set_spd_default_value(32, 21 );
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/* Command and Address signal input hold time */
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set_spd_default_value(33, 8 );
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set_spd_default_value(34, 21 ); /* Data signal input setup time */
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set_spd_default_value(35, 8 ); /* Data signal input hold time */
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#endif /* DO_UGLY_SDRAM_WORKAROUND */
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dram_size = spd_sdram(0);
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#endif
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#ifdef DEBUG
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show_sdram_registers();
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#endif
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#if defined(CFG_DRAM_TEST)
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bcu4_testdram(dram_size);
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printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));
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#endif
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return dram_size;
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}
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