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Merge branch '2023-08-24-further-ufs-updates' into next
- Cleanup and improve the UFS subsystem slightly, in preparation for supporting more platforms.
This commit is contained in:
Tom Rini
commit
6de1a3eb80
2 changed files with 97 additions and 11 deletions
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@ -8,6 +8,7 @@
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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*/
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#include <bouncebuf.h>
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#include <charset.h>
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#include <common.h>
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#include <dm.h>
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@ -691,14 +692,30 @@ static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
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return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
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}
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/**
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* ufshcd_cache_flush_and_invalidate - Flush and invalidate cache
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*
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* Flush and invalidate cache in aligned address..address+size range.
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* The invalidation is in place to avoid stale data in cache.
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*/
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static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size)
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{
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uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1);
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unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN);
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flush_dcache_range(aaddr, aaddr + asize);
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invalidate_dcache_range(aaddr, aaddr + asize);
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}
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/**
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* ufshcd_prepare_req_desc_hdr() - Fills the requests header
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* descriptor according to request
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*/
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static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
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static void ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba,
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u32 *upiu_flags,
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enum dma_data_direction cmd_dir)
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{
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struct utp_transfer_req_desc *req_desc = hba->utrdl;
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u32 data_direction;
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u32 dword_0;
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@ -733,6 +750,8 @@ static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
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req_desc->header.dword_3 = 0;
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req_desc->prd_table_length = 0;
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ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
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}
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static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
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@ -761,10 +780,15 @@ static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
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memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
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/* Copy the Descriptor */
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if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
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if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) {
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memcpy(ucd_req_ptr + 1, query->descriptor, len);
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ufshcd_cache_flush_and_invalidate(ucd_req_ptr, 2 * sizeof(*ucd_req_ptr));
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} else {
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ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
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}
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memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
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ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
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}
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static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
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@ -781,6 +805,9 @@ static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
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ucd_req_ptr->header.dword_2 = 0;
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memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
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ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
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ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
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}
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/**
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@ -792,11 +819,10 @@ static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
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{
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u32 upiu_flags;
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int ret = 0;
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struct utp_transfer_req_desc *req_desc = hba->utrdl;
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hba->dev_cmd.type = cmd_type;
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ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
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ufshcd_prepare_req_desc_hdr(hba, &upiu_flags, DMA_NONE);
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switch (cmd_type) {
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case DEV_CMD_TYPE_QUERY:
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ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
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@ -857,7 +883,9 @@ static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
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*/
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static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
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{
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return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
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struct utp_transfer_req_desc *req_desc = hba->utrdl;
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return le32_to_cpu(req_desc->header.dword_2) & MASK_OCS;
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}
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static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
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@ -1406,6 +1434,8 @@ void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
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memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
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memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
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ufshcd_cache_flush_and_invalidate(ucd_req_ptr, sizeof(*ucd_req_ptr));
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ufshcd_cache_flush_and_invalidate(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr));
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}
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static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
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@ -1420,6 +1450,7 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
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{
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struct utp_transfer_req_desc *req_desc = hba->utrdl;
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struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
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uintptr_t aaddr = (uintptr_t)(pccb->pdata) & ~(ARCH_DMA_MINALIGN - 1);
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ulong datalen = pccb->datalen;
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int table_length;
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u8 *buf;
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@ -1427,9 +1458,19 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
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if (!datalen) {
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req_desc->prd_table_length = 0;
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ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
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return;
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}
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if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */
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flush_dcache_range(aaddr, aaddr +
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ALIGN(datalen, ARCH_DMA_MINALIGN));
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}
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/* In any case, invalidate cache to avoid stale data in it. */
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invalidate_dcache_range(aaddr, aaddr +
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ALIGN(datalen, ARCH_DMA_MINALIGN));
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table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
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buf = pccb->pdata;
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i = table_length;
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@ -1443,17 +1484,18 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
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prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
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req_desc->prd_table_length = table_length;
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ufshcd_cache_flush_and_invalidate(prd_table, sizeof(*prd_table) * table_length);
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ufshcd_cache_flush_and_invalidate(req_desc, sizeof(*req_desc));
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}
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static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
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{
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struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
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struct utp_transfer_req_desc *req_desc = hba->utrdl;
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u32 upiu_flags;
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int ocs, result = 0;
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u8 scsi_status;
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ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
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ufshcd_prepare_req_desc_hdr(hba, &upiu_flags, pccb->dma_dir);
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ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
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prepare_prdt_table(hba, pccb);
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@ -1630,8 +1672,13 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
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if (hba->max_pwr_info.is_valid)
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return 0;
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pwr_info->pwr_tx = FAST_MODE;
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pwr_info->pwr_rx = FAST_MODE;
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if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
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pwr_info->pwr_tx = FASTAUTO_MODE;
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pwr_info->pwr_rx = FASTAUTO_MODE;
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} else {
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pwr_info->pwr_tx = FAST_MODE;
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pwr_info->pwr_rx = FAST_MODE;
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}
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pwr_info->hs_rate = PA_HS_MODE_B;
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/* Get the connected lane count */
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@ -1889,13 +1936,16 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
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/* Read capabilties registers */
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hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
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if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
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hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
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/* Get UFS version supported by the controller */
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hba->version = ufshcd_get_ufs_version(hba);
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if (hba->version != UFSHCI_VERSION_10 &&
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hba->version != UFSHCI_VERSION_11 &&
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hba->version != UFSHCI_VERSION_20 &&
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hba->version != UFSHCI_VERSION_21)
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hba->version != UFSHCI_VERSION_21 &&
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hba->version != UFSHCI_VERSION_30)
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dev_err(hba->dev, "invalid UFS version 0x%x\n",
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hba->version);
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@ -1942,8 +1992,31 @@ int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
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return ret;
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}
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#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
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static int ufs_scsi_buffer_aligned(struct udevice *scsi_dev, struct bounce_buffer *state)
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{
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#ifdef CONFIG_PHYS_64BIT
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struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
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uintptr_t ubuf = (uintptr_t)state->user_buffer;
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size_t len = state->len_aligned;
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/* Check if below 32bit boundary */
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if ((hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) &&
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((ubuf >> 32) || (ubuf + len) >> 32)) {
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dev_dbg(scsi_dev, "Buffer above 32bit boundary %lx-%lx\n",
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ubuf, ubuf + len);
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return 0;
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}
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#endif
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return 1;
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}
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#endif /* CONFIG_BOUNCE_BUFFER */
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static struct scsi_ops ufs_ops = {
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.exec = ufs_scsi_exec,
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#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
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.buffer_aligned = ufs_scsi_buffer_aligned,
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#endif /* CONFIG_BOUNCE_BUFFER */
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};
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int ufs_probe_dev(int index)
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@ -717,7 +717,19 @@ struct ufs_hba {
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* the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
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* attribute of device to 0).
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*/
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#define UFSHCD_QUIRK_BROKEN_LCC 0x1
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#define UFSHCD_QUIRK_BROKEN_LCC BIT(0)
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/*
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* This quirk needs to be enabled if the host controller has
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* 64-bit addressing supported capability but it doesn't work.
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*/
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#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1)
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/*
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* This quirk needs to be enabled if the host controller has
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* auto-hibernate capability but it's FASTAUTO only.
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*/
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#define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2)
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/* Virtual memory reference */
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struct utp_transfer_cmd_desc *ucdl;
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@ -769,6 +781,7 @@ enum {
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UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
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UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
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UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
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UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
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};
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/* Interrupt disable masks */
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