mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
ls1021aqds/ls1021aiot: Remove legacy non-DM_ETH code
Now that we are about to enable DM_ETH by default, remove legacy code. Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
c39d789f49
commit
6dcca22f77
6 changed files with 0 additions and 364 deletions
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@ -41,7 +41,6 @@ obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
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endif
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obj-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
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ifndef CONFIG_RAMBOOT_PBL
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obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
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endif
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@ -1,130 +0,0 @@
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/*
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* Freescale SGMII Riser Card
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*
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* This driver supports the SGMII Riser card found on the
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* "DS" style of development board from Freescale.
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <log.h>
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#include <net.h>
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#include <linux/libfdt.h>
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#include <tsec.h>
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#include <fdt_support.h>
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void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
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{
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int i;
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for (i = 0; i < num; i++)
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if (tsec_info[i].flags & TSEC_SGMII)
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tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
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}
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void fsl_sgmii_riser_fdt_fixup(void *fdt)
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{
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struct eth_device *dev;
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int node;
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int mdio_node;
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int i = -1;
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int etsec_num = 0;
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node = fdt_path_offset(fdt, "/aliases");
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if (node < 0)
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return;
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while ((dev = eth_get_dev_by_index(++i)) != NULL) {
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struct tsec_private *priv;
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int phy_node;
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int enet_node;
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uint32_t ph;
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char sgmii_phy[16];
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char enet[16];
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const u32 *phyh;
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const char *model;
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const char *path;
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if (!strstr(dev->name, "eTSEC"))
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continue;
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priv = dev->priv;
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if (!(priv->flags & TSEC_SGMII)) {
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etsec_num++;
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continue;
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}
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mdio_node = fdt_node_offset_by_compatible(fdt, -1,
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"fsl,gianfar-mdio");
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if (mdio_node < 0)
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return;
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sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num);
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phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy);
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if (phy_node > 0) {
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fdt_increase_size(fdt, 32);
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ph = fdt_create_phandle(fdt, phy_node);
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if (!ph)
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continue;
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}
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sprintf(enet, "ethernet%d", etsec_num++);
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path = fdt_getprop(fdt, node, enet, NULL);
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if (!path) {
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debug("No alias for %s\n", enet);
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continue;
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}
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enet_node = fdt_path_offset(fdt, path);
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if (enet_node < 0)
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continue;
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model = fdt_getprop(fdt, enet_node, "model", NULL);
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/*
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* We only want to do this to eTSECs. On some platforms
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* there are more than one type of gianfar-style ethernet
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* controller, and as we are creating an implicit connection
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* between ethernet nodes and eTSEC devices, it is best to
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* make the connection use as much explicit information
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* as exists.
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*/
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if (!strstr(model, "TSEC"))
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continue;
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if (phy_node < 0) {
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/*
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* This part is only for old device tree without
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* sgmii_phy nodes. It's kept just for compatible
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* reason. Soon to be deprecated if all device tree
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* get updated.
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*/
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phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
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if (!phyh)
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continue;
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phy_node = fdt_node_offset_by_phandle(fdt,
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fdt32_to_cpu(*phyh));
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priv = dev->priv;
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if (priv->flags & TSEC_SGMII)
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fdt_setprop_cell(fdt, phy_node, "reg",
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priv->phyaddr);
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} else {
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fdt_setprop(fdt, enet_node, "phy-handle", &ph,
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sizeof(ph));
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fdt_setprop_string(fdt, enet_node,
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"phy-connection-type",
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phy_string_for_interface(
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PHY_INTERFACE_MODE_SGMII));
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}
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}
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}
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@ -109,44 +109,6 @@ int dram_init(void)
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(struct bd_info *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if (is_serdes_configured(SGMII_TSEC1)) {
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puts("eTSEC1 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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puts("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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@ -6,5 +6,4 @@
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obj-y += ls1021aqds.o
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obj-y += ddr.o
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obj-y += eth.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o
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@ -1,186 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* This file handles the board muxing between the RGMII/SGMII PHYs on
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* Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb
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* ports. The SGMII PHYs are provided by the standard Freescale four-port
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* SGMII riser card.
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*
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* Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control
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* muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends
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* on which port is used. The value for SGMII depends on which slot the riser
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* is inserted in.
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*/
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#include <common.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <malloc.h>
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#include "../common/sgmii_riser.h"
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#include "../common/qixis.h"
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#define EMI1_MASK 0x1f
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#define EMI1_RGMII0 1
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#define EMI1_RGMII1 2
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#define EMI1_RGMII2 3
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#define EMI1_SGMII1 0x1c
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#define EMI1_SGMII2 0x1d
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struct ls1021a_mdio {
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struct mii_dev *realbus;
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};
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static void ls1021a_mux_mdio(int addr)
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{
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u8 brdcfg4;
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= EMI1_MASK;
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switch (addr) {
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case EMI1_RGMII0:
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brdcfg4 |= 0;
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break;
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case EMI1_RGMII1:
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brdcfg4 |= 0x20;
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break;
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case EMI1_RGMII2:
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brdcfg4 |= 0x40;
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break;
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case EMI1_SGMII1:
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brdcfg4 |= 0x60;
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break;
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case EMI1_SGMII2:
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brdcfg4 |= 0x80;
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break;
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default:
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brdcfg4 |= 0xa0;
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break;
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}
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct ls1021a_mdio *priv = bus->priv;
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ls1021a_mux_mdio(addr);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct ls1021a_mdio *priv = bus->priv;
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ls1021a_mux_mdio(addr);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int ls1021a_mdio_reset(struct mii_dev *bus)
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{
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struct ls1021a_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int ls1021a_mdio_init(char *realbusname, char *fakebusname)
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{
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struct ls1021a_mdio *lsmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate LS102xA MDIO bus\n");
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return -1;
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}
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lsmdio = malloc(sizeof(*lsmdio));
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if (!lsmdio) {
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printf("Failed to allocate LS102xA private data\n");
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free(bus);
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return -1;
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}
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bus->read = ls1021a_mdio_read;
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bus->write = ls1021a_mdio_write;
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bus->reset = ls1021a_mdio_reset;
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strcpy(bus->name, fakebusname);
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lsmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!lsmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(lsmdio);
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return -1;
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}
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bus->priv = lsmdio;
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return mdio_register(bus);
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}
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int board_eth_init(struct bd_info *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[3];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if (is_serdes_configured(SGMII_TSEC1)) {
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puts("eTSEC1 is in sgmii mode\n");
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tsec_info[num].flags |= TSEC_SGMII;
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tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
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} else {
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tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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puts("eTSEC2 is in sgmii mode\n");
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tsec_info[num].flags |= TSEC_SGMII;
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tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
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} else {
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tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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#ifdef CONFIG_FSL_SGMII_RISER
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fsl_sgmii_riser_init(tsec_info, num);
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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/* Register the virtual MDIO front-ends */
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ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO");
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ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO");
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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@ -285,14 +285,6 @@
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_FSL_SGMII_RISER 1
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#define SGMII_RISER_PHY_OFFSET 0x1b
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#ifdef CONFIG_FSL_SGMII_RISER
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#define CONFIG_SYS_TBIPA_VALUE 8
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#endif
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#endif
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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