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Merge git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2018-04-15 08:42:08 -04:00
commit 6d0409f256
28 changed files with 1035 additions and 662 deletions
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4
arch/arm/dts/r8a7790-stout-u-boot.dts
View file

@ -8,3 +8,7 @@
#include "r8a7790-stout.dts"
#include "r8a7790-u-boot.dtsi"
&scifa0 {
u-boot,dm-pre-reloc;
};

7
arch/arm/mach-rmobile/Kconfig.32
View file

@ -70,14 +70,17 @@ config TARGET_PORTER
bool "Porter board"
select DM
select DM_SERIAL
select SUPPORT_TPL
select SUPPORT_SPL
select SPL_DM if SPL
select USE_TINY_PRINTF
select SPL_TINY_MEMSET
config TARGET_STOUT
bool "Stout board"
select DM
select DM_SERIAL
select SUPPORT_SPL
select USE_TINY_PRINTF
select SPL_TINY_MEMSET
endchoice

4
arch/arm/mach-rmobile/include/mach/boot0.h
View file

@ -1,5 +1,5 @@
/*
* Specialty padding for the RCar Gen2 TPL JTAG loading
* Specialty padding for the RCar Gen2 SPL JTAG loading
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -10,7 +10,7 @@
_start:
ARM_VECTORS
#ifdef CONFIG_TPL_BUILD
#ifdef CONFIG_SPL_BUILD
.word 0x0badc0d3;
.word 0x0badc0d3;
.word 0x0badc0d3;

2
arch/arm/mach-rmobile/lowlevel_init_ca15.S
View file

@ -11,7 +11,7 @@
#include <linux/linkage.h>
ENTRY(lowlevel_init)
#ifndef CONFIG_TPL_BUILD
#ifndef CONFIG_SPL_BUILD
mrc p15, 0, r4, c0, c0, 5 /* mpidr */
orr r4, r4, r4, lsr #6
and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */

38
board/renesas/porter/porter_spl.c
View file

@ -27,7 +27,6 @@
#define SD2CKCR 0xE615026C
#define SD_97500KHZ 0x7
#ifdef CONFIG_TPL_BUILD
struct reg_config {
u16 off;
u32 val;
@ -45,7 +44,7 @@ static void dbsc_wait(u16 reg)
;
}
static void tpl_init_sys(void)
static void spl_init_sys(void)
{
u32 r0 = 0;
@ -65,7 +64,7 @@ static void tpl_init_sys(void)
:"=r"(r0));
}
static void tpl_init_pfc(void)
static void spl_init_pfc(void)
{
static const struct reg_config pfc_with_unlock[] = {
{ 0x0090, 0x60000000 },
@ -125,7 +124,7 @@ static void tpl_init_pfc(void)
pfc_base | pfc_without_unlock[i].off);
}
static void tpl_init_gpio(void)
static void spl_init_gpio(void)
{
static const u16 gpio_offs[] = {
0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
@ -164,13 +163,13 @@ static void tpl_init_gpio(void)
writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
}
static void tpl_init_lbsc(void)
static void spl_init_lbsc(void)
{
static const struct reg_config lbsc_config[] = {
{ 0x00, 0x00000020 },
{ 0x08, 0x00002020 },
{ 0x10, 0x2a103320 },
{ 0x18, 0xff70ff70 },
{ 0x30, 0x2a103320 },
{ 0x38, 0xff70ff70 },
};
static const u16 lbsc_offs[] = {
@ -192,7 +191,7 @@ static void tpl_init_lbsc(void)
writel(0, lbsc_base | lbsc_offs[i]);
}
static void tpl_init_dbsc(void)
static void spl_init_dbsc(void)
{
static const struct reg_config dbsc_config1[] = {
{ 0x0280, 0x0000a55a },
@ -412,7 +411,7 @@ static void tpl_init_dbsc(void)
}
static void tpl_init_qspi(void)
static void spl_init_qspi(void)
{
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
@ -446,14 +445,13 @@ void board_init_f(ulong dummy)
*/
writel(SD_97500KHZ, SD2CKCR);
tpl_init_sys();
tpl_init_pfc();
tpl_init_gpio();
tpl_init_lbsc();
tpl_init_dbsc();
tpl_init_qspi();
spl_init_sys();
spl_init_pfc();
spl_init_gpio();
spl_init_lbsc();
spl_init_dbsc();
spl_init_qspi();
}
#endif
void spl_board_init(void)
{
@ -463,18 +461,17 @@ void spl_board_init(void)
void board_boot_order(u32 *spl_boot_list)
{
#ifdef CONFIG_TPL_BUILD
const u32 jtag_magic = 0x1337c0de;
const u32 load_magic = 0xb33fc0de;
/*
* If JTAG probe sets special word at 0xe6300020, then it must
* put U-Boot into RAM and TPL will start it from RAM.
* put U-Boot into RAM and SPL will start it from RAM.
*/
if (readl(CONFIG_TPL_TEXT_BASE + 0x20) == jtag_magic) {
if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
printf("JTAG boot detected!\n");
while (readl(CONFIG_TPL_TEXT_BASE + 0x24) != load_magic)
while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
;
spl_boot_list[0] = BOOT_DEVICE_RAM;
@ -482,7 +479,6 @@ void board_boot_order(u32 *spl_boot_list)
return;
}
#endif
/* Boot from SPI NOR with YMODEM UART fallback. */
spl_boot_list[0] = BOOT_DEVICE_SPI;

6
board/renesas/stout/Makefile
View file

@ -8,4 +8,8 @@
# SPDX-License-Identifier: GPL-2.0
#
obj-y := stout.o cpld.o qos.o ../rcar-common/common.o
ifdef CONFIG_SPL_BUILD
obj-y := stout_spl.o
else
obj-y := stout.o cpld.o qos.o
endif

16
board/renesas/stout/cpld.c
View file

@ -13,10 +13,10 @@
#include <asm/gpio.h>
#include "cpld.h"
#define SCLK GPIO_GP_3_24
#define SSTBZ GPIO_GP_3_25
#define MOSI GPIO_GP_3_26
#define MISO GPIO_GP_3_27
#define SCLK (92 + 24)
#define SSTBZ (92 + 25)
#define MOSI (92 + 26)
#define MISO (92 + 27)
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x01 /* RW */
@ -91,10 +91,10 @@ void cpld_init(void)
val |= PUPR3_SD3_DAT1;
writel(val, PUPR3);
gpio_request(SCLK, NULL);
gpio_request(SSTBZ, NULL);
gpio_request(MOSI, NULL);
gpio_request(MISO, NULL);
gpio_request(SCLK, "SCLK");
gpio_request(SSTBZ, "SSTBZ");
gpio_request(MOSI, "MOSI");
gpio_request(MISO, "MISO");
gpio_direction_output(SCLK, 0);
gpio_direction_output(SSTBZ, 1);

135
board/renesas/stout/stout.c
View file

@ -59,14 +59,7 @@ void s_init(void)
qos_init();
}
#define TMU0_MSTP125 (1 << 25)
#define SCIFA0_MSTP204 (1 << 4)
#define SDHI0_MSTP314 (1 << 14)
#define SDHI2_MSTP312 (1 << 12)
#define ETHER_MSTP813 (1 << 13)
#define MSTPSR3 0xE6150048
#define SMSTPCR3 0xE615013C
#define TMU0_MSTP125 BIT(25)
#define SD2CKCR 0xE6150078
#define SD2_97500KHZ 0x7
@ -75,12 +68,6 @@ int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
/* SCIFA0 */
mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
/* SDHI0,2 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
/*
* SD0 clock is set to 97.5MHz by default.
@ -91,66 +78,37 @@ int board_early_init_f(void)
return 0;
}
#define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7790_pinmux_init();
cpld_init();
#ifdef CONFIG_SH_ETHER
/* ETHER Enable */
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
gpio_request(GPIO_FN_ETH_RXD1, NULL);
gpio_request(GPIO_FN_ETH_LINK, NULL);
gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
gpio_request(GPIO_FN_ETH_MDIO, NULL);
gpio_request(GPIO_FN_ETH_TXD1, NULL);
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
gpio_request(GPIO_FN_IRQ1, NULL);
gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */
gpio_direction_output(GPIO_GP_3_31, 0);
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
gpio_direction_output(ETHERNET_PHY_RESET, 0);
mdelay(20);
gpio_set_value(GPIO_GP_3_31, 1);
udelay(1);
#endif
gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
int dram_init(void)
{
int ret = -ENODEV;
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
#ifdef CONFIG_SH_ETHER
u32 val;
unsigned char enetaddr[6];
return 0;
}
ret = sh_eth_initialize(bis);
if (!eth_env_get_enetaddr("ethaddr", enetaddr))
return ret;
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
/* Set Mac address */
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
enetaddr[2] << 8 | enetaddr[3];
writel(val, CXR24);
val = enetaddr[4] << 8 | enetaddr[5];
writel(val, CXR25);
#endif
return ret;
return 0;
}
/* Stout has KSZ8041NL/RNL */
@ -167,67 +125,6 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
int board_mmc_init(bd_t *bis)
{
int ret = -ENODEV;
#ifdef CONFIG_SH_SDHI
gpio_request(GPIO_FN_SD0_DAT0, NULL);
gpio_request(GPIO_FN_SD0_DAT1, NULL);
gpio_request(GPIO_FN_SD0_DAT2, NULL);
gpio_request(GPIO_FN_SD0_DAT3, NULL);
gpio_request(GPIO_FN_SD0_CLK, NULL);
gpio_request(GPIO_FN_SD0_CMD, NULL);
gpio_request(GPIO_FN_SD0_CD, NULL);
gpio_request(GPIO_FN_SD2_DAT0, NULL);
gpio_request(GPIO_FN_SD2_DAT1, NULL);
gpio_request(GPIO_FN_SD2_DAT2, NULL);
gpio_request(GPIO_FN_SD2_DAT3, NULL);
gpio_request(GPIO_FN_SD2_CLK, NULL);
gpio_request(GPIO_FN_SD2_CMD, NULL);
gpio_request(GPIO_FN_SD2_CD, NULL);
/* SDHI0 - needs CPLD mux setup */
gpio_request(GPIO_GP_3_30, NULL);
gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */
gpio_request(GPIO_GP_5_24, NULL);
gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
SH_SDHI_QUIRK_16BIT_BUF);
if (ret)
return ret;
/* SDHI2 - needs CPLD mux setup */
gpio_request(GPIO_GP_3_29, NULL);
gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */
gpio_request(GPIO_GP_5_25, NULL);
gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
#endif
return ret;
}
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
static const struct sh_serial_platdata serial_platdata = {
.base = SCIFA0_BASE,
.type = PORT_SCIFA,
.clk = CONFIG_MP_CLK_FREQ,
};
U_BOOT_DEVICE(stout_serials) = {
.name = "serial_sh",
.platdata = &serial_platdata,
};

477
board/renesas/stout/stout_spl.c Normal file
View file

@ -0,0 +1,477 @@
/*
* board/renesas/stout/stout_spl.c
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <malloc.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>
#define TMU0_MSTP125 BIT(25)
#define SCIFA0_MSTP204 BIT(4)
#define QSPI_MSTP917 BIT(17)
#define SD2CKCR 0xE615026C
#define SD_97500KHZ 0x7
struct reg_config {
u16 off;
u32 val;
};
static void dbsc_wait(u16 reg)
{
static const u32 dbsc3_0_base = DBSC3_0_BASE;
static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
while (!(readl(dbsc3_0_base + reg) & BIT(0)))
;
while (!(readl(dbsc3_1_base + reg) & BIT(0)))
;
}
static void spl_init_sys(void)
{
u32 r0 = 0;
writel(0xa5a5a500, 0xe6020004);
writel(0xa5a5a500, 0xe6030004);
asm volatile(
/* ICIALLU - Invalidate I$ to PoU */
"mcr 15, 0, %0, cr7, cr5, 0 \n"
/* BPIALL - Invalidate branch predictors */
"mcr 15, 0, %0, cr7, cr5, 6 \n"
/* Set SCTLR[IZ] */
"mrc 15, 0, %0, cr1, cr0, 0 \n"
"orr %0, #0x1800 \n"
"mcr 15, 0, %0, cr1, cr0, 0 \n"
"isb sy \n"
:"=r"(r0));
}
static void spl_init_pfc(void)
{
static const struct reg_config pfc_with_unlock[] = {
{ 0x0090, 0x00140300 },
{ 0x0094, 0x09500000 },
{ 0x0098, 0xc0000084 },
{ 0x0020, 0x01a33492 },
{ 0x0024, 0x10000000 },
{ 0x0028, 0x08449252 },
{ 0x002c, 0x2925b322 },
{ 0x0030, 0x0c311249 },
{ 0x0034, 0x10124000 },
{ 0x0038, 0x00001295 },
{ 0x003c, 0x50890000 },
{ 0x0040, 0x0eaa56aa },
{ 0x0044, 0x55550000 },
{ 0x0048, 0x00000005 },
{ 0x004c, 0x54800000 },
{ 0x0050, 0x3736db55 },
{ 0x0054, 0x29148da3 },
{ 0x0058, 0x48c446e1 },
{ 0x005c, 0x2a3a54dc },
{ 0x0160, 0x00000023 },
{ 0x0004, 0xfca0ffff },
{ 0x0008, 0x3fbffbf0 },
{ 0x000c, 0x3ffdffff },
{ 0x0010, 0x00ffffff },
{ 0x0014, 0xfc3ffff3 },
{ 0x0018, 0xe4fdfff7 },
};
static const struct reg_config pfc_without_unlock[] = {
{ 0x0104, 0xffffbfff },
{ 0x0108, 0xb1ffffe1 },
{ 0x010c, 0xffffffff },
{ 0x0110, 0xffffffff },
{ 0x0114, 0xe047beab },
{ 0x0118, 0x00000203 },
};
static const u32 pfc_base = 0xe6060000;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
writel(~pfc_with_unlock[i].val, pfc_base);
writel(pfc_with_unlock[i].val,
pfc_base | pfc_with_unlock[i].off);
}
for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
writel(pfc_without_unlock[i].val,
pfc_base | pfc_without_unlock[i].off);
}
static void spl_init_gpio(void)
{
static const u16 gpio_offs[] = {
0x1000, 0x3000, 0x4000, 0x5000
};
static const struct reg_config gpio_set[] = {
{ 0x4000, 0x00c00000 },
{ 0x5000, 0x63020000 },
};
static const struct reg_config gpio_clr[] = {
{ 0x1000, 0x00000000 },
{ 0x3000, 0x00000000 },
{ 0x4000, 0x00c00000 },
{ 0x5000, 0xe3020000 },
};
static const u32 gpio_base = 0xe6050000;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
writel(0, gpio_base | 0x20 | gpio_offs[i]);
for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
writel(0, gpio_base | 0x00 | gpio_offs[i]);
for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
}
static void spl_init_lbsc(void)
{
static const struct reg_config lbsc_config[] = {
{ 0x00, 0x00000020 },
{ 0x08, 0x00002020 },
{ 0x30, 0x02150326 },
{ 0x38, 0x077f077f },
};
static const u16 lbsc_offs[] = {
0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
};
static const u32 lbsc_base = 0xfec00200;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
writel(lbsc_config[i].val,
lbsc_base | lbsc_config[i].off);
writel(lbsc_config[i].val,
lbsc_base | (lbsc_config[i].off + 4));
}
for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
writel(0, lbsc_base | lbsc_offs[i]);
}
static void spl_init_dbsc(void)
{
static const struct reg_config dbsc_config1[] = {
{ 0x0280, 0x0000a55a },
{ 0x0018, 0x21000000 },
{ 0x0018, 0x11000000 },
{ 0x0018, 0x10000000 },
{ 0x0290, 0x00000001 },
{ 0x02a0, 0x80000000 },
{ 0x0290, 0x00000004 },
};
static const struct reg_config dbsc_config2[] = {
{ 0x0290, 0x00000006 },
{ 0x02a0, 0x0001c000 },
};
static const struct reg_config dbsc_config3r0d0[] = {
{ 0x0290, 0x0000000f },
{ 0x02a0, 0x00181885 },
{ 0x0290, 0x00000070 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x00000080 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x00000090 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x000000a0 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x000000b0 },
{ 0x02a0, 0x7c000880 },
{ 0x0290, 0x000000c0 },
{ 0x02a0, 0x7c000880 },
{ 0x0290, 0x000000d0 },
{ 0x02a0, 0x7c000880 },
{ 0x0290, 0x000000e0 },
{ 0x02a0, 0x7c000880 },
};
static const struct reg_config dbsc_config3r0d1[] = {
{ 0x0290, 0x0000000f },
{ 0x02a0, 0x00181885 },
{ 0x0290, 0x00000070 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x00000080 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x00000090 },
{ 0x02a0, 0x7c000887 },
{ 0x0290, 0x000000a0 },
{ 0x02a0, 0x7c000887 },
};
static const struct reg_config dbsc_config3r2[] = {
{ 0x0290, 0x0000000f },
{ 0x02a0, 0x00181224 },
};
static const struct reg_config dbsc_config4[] = {
{ 0x0290, 0x00000010 },
{ 0x02a0, 0xf004649b },
{ 0x0290, 0x00000061 },
{ 0x02a0, 0x0000006d },
{ 0x0290, 0x00000001 },
{ 0x02a0, 0x00000073 },
{ 0x0020, 0x00000007 },
{ 0x0024, 0x0f030a02 },
{ 0x0030, 0x00000001 },
{ 0x00b0, 0x00000000 },
{ 0x0040, 0x0000000b },
{ 0x0044, 0x00000008 },
{ 0x0048, 0x00000000 },
{ 0x0050, 0x0000000b },
{ 0x0054, 0x000c000b },
{ 0x0058, 0x00000027 },
{ 0x005c, 0x0000001c },
{ 0x0060, 0x00000006 },
{ 0x0064, 0x00000020 },
{ 0x0068, 0x00000008 },
{ 0x006c, 0x0000000c },
{ 0x0070, 0x00000009 },
{ 0x0074, 0x00000012 },
{ 0x0078, 0x000000d0 },
{ 0x007c, 0x00140005 },
{ 0x0080, 0x00050004 },
{ 0x0084, 0x70233005 },
{ 0x0088, 0x000c0000 },
{ 0x008c, 0x00000200 },
{ 0x0090, 0x00000040 },
{ 0x0100, 0x00000001 },
{ 0x00c0, 0x00020001 },
{ 0x00c8, 0x20042004 },
{ 0x0380, 0x00020002 },
{ 0x0390, 0x0000001f },
};
static const struct reg_config dbsc_config5[] = {
{ 0x0244, 0x00000011 },
{ 0x0290, 0x00000003 },
{ 0x02a0, 0x0300c4e1 },
{ 0x0290, 0x00000023 },
{ 0x02a0, 0x00fcdb60 },
{ 0x0290, 0x00000011 },
{ 0x02a0, 0x1000040b },
{ 0x0290, 0x00000012 },
{ 0x02a0, 0x9d9cbb66 },
{ 0x0290, 0x00000013 },
{ 0x02a0, 0x1a868400 },
{ 0x0290, 0x00000014 },
{ 0x02a0, 0x300214d8 },
{ 0x0290, 0x00000015 },
{ 0x02a0, 0x00000d70 },
{ 0x0290, 0x00000016 },
{ 0x02a0, 0x00000006 },
{ 0x0290, 0x00000017 },
{ 0x02a0, 0x00000018 },
{ 0x0290, 0x0000001a },
{ 0x02a0, 0x910035c7 },
{ 0x0290, 0x00000004 },
};
static const struct reg_config dbsc_config6[] = {
{ 0x0290, 0x00000001 },
{ 0x02a0, 0x00000181 },
{ 0x0018, 0x11000000 },
{ 0x0290, 0x00000004 },
};
static const struct reg_config dbsc_config7[] = {
{ 0x0290, 0x00000001 },
{ 0x02a0, 0x0000fe01 },
{ 0x0304, 0x00000000 },
{ 0x00f4, 0x01004c20 },
{ 0x00f8, 0x014000aa },
{ 0x00e0, 0x00000140 },
{ 0x00e4, 0x00081860 },
{ 0x00e8, 0x00010000 },
{ 0x0290, 0x00000004 },
};
static const struct reg_config dbsc_config8[] = {
{ 0x0014, 0x00000001 },
{ 0x0010, 0x00000001 },
{ 0x0280, 0x00000000 },
};
static const u32 dbsc3_0_base = DBSC3_0_BASE;
static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
static const u32 prr_base = 0xff000044;
const u16 prr_rev = readl(prr_base) & 0x7fff;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
}
dbsc_wait(0x2a0);
for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
}
if (prr_rev == 0x4500) {
for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
writel(dbsc_config3r0d0[i].val,
dbsc3_0_base | dbsc_config3r0d0[i].off);
}
for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
writel(dbsc_config3r0d1[i].val,
dbsc3_1_base | dbsc_config3r0d1[i].off);
}
} else if (prr_rev != 0x4510) {
for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
writel(dbsc_config3r2[i].val,
dbsc3_0_base | dbsc_config3r2[i].off);
writel(dbsc_config3r2[i].val,
dbsc3_1_base | dbsc_config3r2[i].off);
}
}
for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
}
dbsc_wait(0x240);
for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
}
dbsc_wait(0x2a0);
for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
}
dbsc_wait(0x2a0);
for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
}
dbsc_wait(0x2a0);
for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
}
}
static void spl_init_qspi(void)
{
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
static const u32 qspi_base = 0xe6b10000;
writeb(0x08, qspi_base + 0x00);
writeb(0x00, qspi_base + 0x01);
writeb(0x06, qspi_base + 0x02);
writeb(0x01, qspi_base + 0x0a);
writeb(0x00, qspi_base + 0x0b);
writeb(0x00, qspi_base + 0x0c);
writeb(0x00, qspi_base + 0x0d);
writeb(0x00, qspi_base + 0x0e);
writew(0xe080, qspi_base + 0x10);
writeb(0xc0, qspi_base + 0x18);
writeb(0x00, qspi_base + 0x18);
writeb(0x00, qspi_base + 0x08);
writeb(0x48, qspi_base + 0x00);
}
void board_init_f(ulong dummy)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
/*
* SD0 clock is set to 97.5MHz by default.
* Set SD2 to the 97.5MHz as well.
*/
writel(SD_97500KHZ, SD2CKCR);
spl_init_sys();
spl_init_pfc();
spl_init_gpio();
spl_init_lbsc();
spl_init_dbsc();
spl_init_qspi();
}
void spl_board_init(void)
{
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
}
void board_boot_order(u32 *spl_boot_list)
{
const u32 jtag_magic = 0x1337c0de;
const u32 load_magic = 0xb33fc0de;
/*
* If JTAG probe sets special word at 0xe6300020, then it must
* put U-Boot into RAM and SPL will start it from RAM.
*/
if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
printf("JTAG boot detected!\n");
while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
;
spl_boot_list[0] = BOOT_DEVICE_RAM;
spl_boot_list[1] = BOOT_DEVICE_NONE;
return;
}
/* Boot from SPI NOR with YMODEM UART fallback. */
spl_boot_list[0] = BOOT_DEVICE_SPI;
spl_boot_list[1] = BOOT_DEVICE_UART;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
void reset_cpu(ulong addr)
{
}

31
configs/porter_defconfig
View file

@ -1,42 +1,29 @@
CONFIG_ARM=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7791=y
CONFIG_TARGET_PORTER=y
CONFIG_TPL_TEXT_BASE=0xe6300000
CONFIG_TPL_MAX_SIZE=16384
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot"
CONFIG_TPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_BOARD_INIT=y
CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
CONFIG_TPL_RAM_SUPPORT=y
CONFIG_TPL_RAM_DEVICE=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_TPL_SPI_FLASH_SUPPORT=y
CONFIG_TPL_SPI_LOAD=y
CONFIG_TPL_SPI_SUPPORT=y
CONFIG_TPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@ -59,14 +46,9 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas power-domains"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
@ -85,12 +67,10 @@ CONFIG_DM_PCI=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_TPL_DM_SERIAL is not set
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
@ -98,4 +78,3 @@ CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_TPL_TINY_MEMSET=y

1
configs/r8a7795_salvator-x_defconfig
View file

@ -41,7 +41,6 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MMC_RENESAS_TUNING=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

1
configs/r8a7795_ulcb_defconfig
View file

@ -41,7 +41,6 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MMC_RENESAS_TUNING=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

1
configs/r8a7796_salvator-x_defconfig
View file

@ -42,7 +42,6 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MMC_RENESAS_TUNING=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

1
configs/r8a7796_ulcb_defconfig
View file

@ -42,7 +42,6 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MMC_RENESAS_TUNING=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

1
configs/r8a77970_eagle_defconfig
View file

@ -41,7 +41,6 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MMC_RENESAS_TUNING=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

1
configs/r8a77995_draak_defconfig
View file

@ -42,7 +42,6 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MMC_RENESAS_TUNING=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y

49
configs/stout_defconfig
View file

@ -1,17 +1,37 @@
CONFIG_ARM=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0xE8080000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7790=y
CONFIG_TARGET_STOUT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
@ -19,21 +39,42 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
CONFIG_NETDEVICES=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_BAUDRATE=38400
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y

10
drivers/clk/renesas/r8a7790-cpg-mssr.c
View file

@ -40,7 +40,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
static const struct cpg_core_clk r8a7790_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@ -90,7 +90,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
static const struct mssr_mod_clk r8a7790_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
@ -209,10 +209,6 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
@ -235,7 +231,7 @@ static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};

4
drivers/mmc/Makefile
View file

@ -62,6 +62,6 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += matsushita-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += matsushita-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o

151
drivers/mmc/matsushita-common.h
View file

@ -1,151 +0,0 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MATSUSHITA_COMMON_H__
#define __MATSUSHITA_COMMON_H__
#define MATSU_SD_CMD 0x000 /* command */
#define MATSU_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
#define MATSU_SD_CMD_MULTI BIT(13) /* multiple block transfer */
#define MATSU_SD_CMD_RD BIT(12) /* 1: read, 0: write */
#define MATSU_SD_CMD_DATA BIT(11) /* data transfer */
#define MATSU_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
#define MATSU_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
#define MATSU_SD_CMD_RSP_NONE (3 << 8)/* response: none */
#define MATSU_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
#define MATSU_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
#define MATSU_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
#define MATSU_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
#define MATSU_SD_ARG 0x008 /* command argument */
#define MATSU_SD_STOP 0x010 /* stop action control */
#define MATSU_SD_STOP_SEC BIT(8) /* use sector count */
#define MATSU_SD_STOP_STP BIT(0) /* issue CMD12 */
#define MATSU_SD_SECCNT 0x014 /* sector counter */
#define MATSU_SD_RSP10 0x018 /* response[39:8] */
#define MATSU_SD_RSP32 0x020 /* response[71:40] */
#define MATSU_SD_RSP54 0x028 /* response[103:72] */
#define MATSU_SD_RSP76 0x030 /* response[127:104] */
#define MATSU_SD_INFO1 0x038 /* IRQ status 1 */
#define MATSU_SD_INFO1_CD BIT(5) /* state of card detect */
#define MATSU_SD_INFO1_INSERT BIT(4) /* card inserted */
#define MATSU_SD_INFO1_REMOVE BIT(3) /* card removed */
#define MATSU_SD_INFO1_CMP BIT(2) /* data complete */
#define MATSU_SD_INFO1_RSP BIT(0) /* response complete */
#define MATSU_SD_INFO2 0x03c /* IRQ status 2 */
#define MATSU_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
#define MATSU_SD_INFO2_CBSY BIT(14) /* command busy */
#define MATSU_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
#define MATSU_SD_INFO2_BWE BIT(9) /* write buffer ready */
#define MATSU_SD_INFO2_BRE BIT(8) /* read buffer ready */
#define MATSU_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
#define MATSU_SD_INFO2_ERR_RTO BIT(6) /* response time out */
#define MATSU_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
#define MATSU_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
#define MATSU_SD_INFO2_ERR_TO BIT(3) /* time out error */
#define MATSU_SD_INFO2_ERR_END BIT(2) /* END bit error */
#define MATSU_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
#define MATSU_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
#define MATSU_SD_INFO1_MASK 0x040
#define MATSU_SD_INFO2_MASK 0x044
#define MATSU_SD_CLKCTL 0x048 /* clock divisor */
#define MATSU_SD_CLKCTL_DIV_MASK 0x104ff
#define MATSU_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
#define MATSU_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
#define MATSU_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
#define MATSU_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
#define MATSU_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
#define MATSU_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
#define MATSU_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
#define MATSU_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
#define MATSU_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
#define MATSU_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
#define MATSU_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
#define MATSU_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
#define MATSU_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
#define MATSU_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
#define MATSU_SD_SIZE 0x04c /* block size */
#define MATSU_SD_OPTION 0x050
#define MATSU_SD_OPTION_WIDTH_MASK (5 << 13)
#define MATSU_SD_OPTION_WIDTH_1 (4 << 13)
#define MATSU_SD_OPTION_WIDTH_4 (0 << 13)
#define MATSU_SD_OPTION_WIDTH_8 (1 << 13)
#define MATSU_SD_BUF 0x060 /* read/write buffer */
#define MATSU_SD_EXTMODE 0x1b0
#define MATSU_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
#define MATSU_SD_SOFT_RST 0x1c0
#define MATSU_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
#define MATSU_SD_VERSION 0x1c4 /* version register */
#define MATSU_SD_VERSION_IP 0xff /* IP version */
#define MATSU_SD_HOST_MODE 0x1c8
#define MATSU_SD_IF_MODE 0x1cc
#define MATSU_SD_IF_MODE_DDR BIT(0) /* DDR mode */
#define MATSU_SD_VOLT 0x1e4 /* voltage switch */
#define MATSU_SD_VOLT_MASK (3 << 0)
#define MATSU_SD_VOLT_OFF (0 << 0)
#define MATSU_SD_VOLT_330 (1 << 0)/* 3.3V signal */
#define MATSU_SD_VOLT_180 (2 << 0)/* 1.8V signal */
#define MATSU_SD_DMA_MODE 0x410
#define MATSU_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
#define MATSU_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
#define MATSU_SD_DMA_CTL 0x414
#define MATSU_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
#define MATSU_SD_DMA_RST 0x418
#define MATSU_SD_DMA_RST_RD BIT(9)
#define MATSU_SD_DMA_RST_WR BIT(8)
#define MATSU_SD_DMA_INFO1 0x420
#define MATSU_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
#define MATSU_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
#define MATSU_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
#define MATSU_SD_DMA_INFO1_MASK 0x424
#define MATSU_SD_DMA_INFO2 0x428
#define MATSU_SD_DMA_INFO2_ERR_RD BIT(17)
#define MATSU_SD_DMA_INFO2_ERR_WR BIT(16)
#define MATSU_SD_DMA_INFO2_MASK 0x42c
#define MATSU_SD_DMA_ADDR_L 0x440
#define MATSU_SD_DMA_ADDR_H 0x444
/* alignment required by the DMA engine of this controller */
#define MATSU_SD_DMA_MINALIGN 0x10
struct matsu_sd_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct matsu_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
u32 caps;
#define MATSU_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define MATSU_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define MATSU_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
#define MATSU_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
#define MATSU_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
#define MATSU_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
#define MATSU_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
#define MATSU_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
#define MATSU_SD_CAP_RCAR \
(MATSU_SD_CAP_RCAR_GEN2 | MATSU_SD_CAP_RCAR_GEN3)
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
};
int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data);
int matsu_sd_set_ios(struct udevice *dev);
int matsu_sd_get_cd(struct udevice *dev);
int matsu_sd_bind(struct udevice *dev);
int matsu_sd_probe(struct udevice *dev, u32 quirks);
u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg);
void matsu_sd_writel(struct matsu_sd_priv *priv,
u32 val, unsigned int reg);
#endif /* __MATSUSHITA_COMMON_H__ */

108
drivers/mmc/renesas-sdhi.c
View file

@ -16,7 +16,7 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
#include "matsushita-common.h"
#include "tmio-common.h"
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
@ -38,86 +38,86 @@
#define RENESAS_SDHI_MAX_TAP 3
static unsigned int renesas_sdhi_init_tuning(struct matsu_sd_priv *priv)
static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
/* Initialize SCC */
matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg &= ~MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg &= ~TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Set sampling clock selection range */
matsu_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
RENESAS_SDHI_SCC_DTCNTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
matsu_sd_writel(priv, 0x300 /* scc_tappos */,
tmio_sd_writel(priv, 0x300 /* scc_tappos */,
RENESAS_SDHI_SCC_DT2FF);
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg |= MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Read TAPNUM */
return (matsu_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}
static void renesas_sdhi_reset_tuning(struct matsu_sd_priv *priv)
static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
/* Reset SCC */
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg &= ~MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg &= ~TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
reg |= MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
}
static void renesas_sdhi_prepare_tuning(struct matsu_sd_priv *priv,
static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
unsigned long tap)
{
/* Set sampling clock position */
matsu_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
}
static unsigned int renesas_sdhi_compare_scc_data(struct matsu_sd_priv *priv)
static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
{
/* Get comparison of sampling data */
return matsu_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
}
static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
unsigned int tap_num, unsigned int taps,
unsigned int smpcmp)
{
@ -132,7 +132,7 @@ static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
u32 reg;
/* Clear SCC_RVSREQ */
matsu_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
/* Merge the results */
for (i = 0; i < tap_num * 2; i++) {
@ -211,19 +211,19 @@ static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
return -EIO;
/* Set SCC */
matsu_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
/* Enable auto re-tuning */
reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
return 0;
}
int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
unsigned int tap_num;
@ -232,7 +232,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
u32 caps;
/* Only supported on Renesas RCar */
if (!(priv->caps & MATSU_SD_CAP_RCAR_UHS))
if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
return -EINVAL;
/* clock tuning is not needed for upto 52MHz */
@ -258,7 +258,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
/* Force PIO for the tuning */
caps = priv->caps;
priv->caps &= ~MATSU_SD_CAP_DMA_INTERNAL;
priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
ret = mmc_send_tuning(mmc, opcode, NULL);
@ -288,12 +288,12 @@ out:
static int renesas_sdhi_set_ios(struct udevice *dev)
{
int ret = matsu_sd_set_ios(dev);
int ret = tmio_sd_set_ios(dev);
mdelay(10);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
renesas_sdhi_reset_tuning(priv);
#endif
@ -302,17 +302,17 @@ static int renesas_sdhi_set_ios(struct udevice *dev)
}
static const struct dm_mmc_ops renesas_sdhi_ops = {
.send_cmd = matsu_sd_send_cmd,
.send_cmd = tmio_sd_send_cmd,
.set_ios = renesas_sdhi_set_ios,
.get_cd = matsu_sd_get_cd,
.get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
.execute_tuning = renesas_sdhi_execute_tuning,
#endif
};
#define RENESAS_GEN2_QUIRKS MATSU_SD_CAP_RCAR_GEN2
#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
#define RENESAS_GEN3_QUIRKS \
MATSU_SD_CAP_64BIT | MATSU_SD_CAP_RCAR_GEN3 | MATSU_SD_CAP_RCAR_UHS
TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
@ -345,10 +345,10 @@ static int renesas_sdhi_probe(struct udevice *dev)
}
if (fdt_resource_size(&reg_res) == 0x100)
quirks |= MATSU_SD_CAP_16BIT;
quirks |= TMIO_SD_CAP_16BIT;
}
ret = matsu_sd_probe(dev, quirks);
ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
if (!ret)
renesas_sdhi_reset_tuning(dev_get_priv(dev));
@ -360,9 +360,9 @@ U_BOOT_DRIVER(renesas_sdhi) = {
.name = "renesas-sdhi",
.id = UCLASS_MMC,
.of_match = renesas_sdhi_match,
.bind = matsu_sd_bind,
.bind = tmio_sd_bind,
.probe = renesas_sdhi_probe,
.priv_auto_alloc_size = sizeof(struct matsu_sd_priv),
.platdata_auto_alloc_size = sizeof(struct matsu_sd_plat),
.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
.ops = &renesas_sdhi_ops,
};

414
drivers/mmc/matsushita-common.c → drivers/mmc/tmio-common.c
View file

@ -18,42 +18,42 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
#include "matsushita-common.h"
#include "tmio-common.h"
DECLARE_GLOBAL_DATA_PTR;
static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
{
return readq(priv->regbase + (reg << 1));
}
static void matsu_sd_writeq(struct matsu_sd_priv *priv,
static void tmio_sd_writeq(struct tmio_sd_priv *priv,
u64 val, unsigned int reg)
{
writeq(val, priv->regbase + (reg << 1));
}
static u16 matsu_sd_readw(struct matsu_sd_priv *priv, unsigned int reg)
static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
{
return readw(priv->regbase + (reg >> 1));
}
static void matsu_sd_writew(struct matsu_sd_priv *priv,
static void tmio_sd_writew(struct tmio_sd_priv *priv,
u16 val, unsigned int reg)
{
writew(val, priv->regbase + (reg >> 1));
}
u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
{
u32 val;
if (priv->caps & MATSU_SD_CAP_64BIT)
if (priv->caps & TMIO_SD_CAP_64BIT)
return readl(priv->regbase + (reg << 1));
else if (priv->caps & MATSU_SD_CAP_16BIT) {
else if (priv->caps & TMIO_SD_CAP_16BIT) {
val = readw(priv->regbase + (reg >> 1)) & 0xffff;
if ((reg == MATSU_SD_RSP10) || (reg == MATSU_SD_RSP32) ||
(reg == MATSU_SD_RSP54) || (reg == MATSU_SD_RSP76)) {
if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
(reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
}
return val;
@ -61,16 +61,16 @@ u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
return readl(priv->regbase + reg);
}
void matsu_sd_writel(struct matsu_sd_priv *priv,
void tmio_sd_writel(struct tmio_sd_priv *priv,
u32 val, unsigned int reg)
{
if (priv->caps & MATSU_SD_CAP_64BIT)
if (priv->caps & TMIO_SD_CAP_64BIT)
writel(val, priv->regbase + (reg << 1));
else if (priv->caps & MATSU_SD_CAP_16BIT) {
else if (priv->caps & TMIO_SD_CAP_16BIT) {
writew(val & 0xffff, priv->regbase + (reg >> 1));
if (reg == MATSU_SD_INFO1 || reg == MATSU_SD_INFO1_MASK ||
reg == MATSU_SD_INFO2 || reg == MATSU_SD_INFO2_MASK ||
reg == MATSU_SD_ARG)
if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
reg == TMIO_SD_ARG)
writew(val >> 16, priv->regbase + (reg >> 1) + 2);
} else
writel(val, priv->regbase + reg);
@ -96,12 +96,12 @@ static void __dma_unmap_single(dma_addr_t addr, size_t size,
invalidate_dcache_range(addr, addr + size);
}
static int matsu_sd_check_error(struct udevice *dev)
static int tmio_sd_check_error(struct udevice *dev)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
struct tmio_sd_priv *priv = dev_get_priv(dev);
u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
if (info2 & MATSU_SD_INFO2_ERR_RTO) {
if (info2 & TMIO_SD_INFO2_ERR_RTO) {
/*
* TIMEOUT must be returned for unsupported command. Do not
* display error log since this might be a part of sequence to
@ -110,19 +110,19 @@ static int matsu_sd_check_error(struct udevice *dev)
return -ETIMEDOUT;
}
if (info2 & MATSU_SD_INFO2_ERR_TO) {
if (info2 & TMIO_SD_INFO2_ERR_TO) {
dev_err(dev, "timeout error\n");
return -ETIMEDOUT;
}
if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
MATSU_SD_INFO2_ERR_IDX)) {
if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
TMIO_SD_INFO2_ERR_IDX)) {
dev_err(dev, "communication out of sync\n");
return -EILSEQ;
}
if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
MATSU_SD_INFO2_ERR_ILW)) {
if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
TMIO_SD_INFO2_ERR_ILW)) {
dev_err(dev, "illegal access\n");
return -EIO;
}
@ -130,20 +130,20 @@ static int matsu_sd_check_error(struct udevice *dev)
return 0;
}
static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
u32 flag)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
long wait = 1000000;
int ret;
while (!(matsu_sd_readl(priv, reg) & flag)) {
while (!(tmio_sd_readl(priv, reg) & flag)) {
if (wait-- < 0) {
dev_err(dev, "timeout\n");
return -ETIMEDOUT;
}
ret = matsu_sd_check_error(dev);
ret = tmio_sd_check_error(dev);
if (ret)
return ret;
@ -153,8 +153,8 @@ static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
return 0;
}
#define matsu_pio_read_fifo(__width, __suffix) \
static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv, \
#define tmio_pio_read_fifo(__width, __suffix) \
static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
char *pbuf, uint blksz) \
{ \
u##__width *buf = (u##__width *)pbuf; \
@ -162,53 +162,53 @@ static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv, \
\
if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
for (i = 0; i < blksz / ((__width) / 8); i++) { \
*buf++ = matsu_sd_read##__suffix(priv, \
MATSU_SD_BUF); \
*buf++ = tmio_sd_read##__suffix(priv, \
TMIO_SD_BUF); \
} \
} else { \
for (i = 0; i < blksz / ((__width) / 8); i++) { \
u##__width data; \
data = matsu_sd_read##__suffix(priv, \
MATSU_SD_BUF); \
data = tmio_sd_read##__suffix(priv, \
TMIO_SD_BUF); \
put_unaligned(data, buf++); \
} \
} \
}
matsu_pio_read_fifo(64, q)
matsu_pio_read_fifo(32, l)
matsu_pio_read_fifo(16, w)
tmio_pio_read_fifo(64, q)
tmio_pio_read_fifo(32, l)
tmio_pio_read_fifo(16, w)
static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
uint blocksize)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
int ret;
/* wait until the buffer is filled with data */
ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
MATSU_SD_INFO2_BRE);
ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
TMIO_SD_INFO2_BRE);
if (ret)
return ret;
/*
* Clear the status flag _before_ read the buffer out because
* MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
* TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
*/
matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
if (priv->caps & MATSU_SD_CAP_64BIT)
matsu_pio_read_fifo_64(priv, pbuf, blocksize);
else if (priv->caps & MATSU_SD_CAP_16BIT)
matsu_pio_read_fifo_16(priv, pbuf, blocksize);
if (priv->caps & TMIO_SD_CAP_64BIT)
tmio_pio_read_fifo_64(priv, pbuf, blocksize);
else if (priv->caps & TMIO_SD_CAP_16BIT)
tmio_pio_read_fifo_16(priv, pbuf, blocksize);
else
matsu_pio_read_fifo_32(priv, pbuf, blocksize);
tmio_pio_read_fifo_32(priv, pbuf, blocksize);
return 0;
}
#define matsu_pio_write_fifo(__width, __suffix) \
static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv, \
#define tmio_pio_write_fifo(__width, __suffix) \
static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
const char *pbuf, uint blksz)\
{ \
const u##__width *buf = (const u##__width *)pbuf; \
@ -216,47 +216,47 @@ static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv, \
\
if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
for (i = 0; i < blksz / ((__width) / 8); i++) { \
matsu_sd_write##__suffix(priv, *buf++, \
MATSU_SD_BUF); \
tmio_sd_write##__suffix(priv, *buf++, \
TMIO_SD_BUF); \
} \
} else { \
for (i = 0; i < blksz / ((__width) / 8); i++) { \
u##__width data = get_unaligned(buf++); \
matsu_sd_write##__suffix(priv, data, \
MATSU_SD_BUF); \
tmio_sd_write##__suffix(priv, data, \
TMIO_SD_BUF); \
} \
} \
}
matsu_pio_write_fifo(64, q)
matsu_pio_write_fifo(32, l)
matsu_pio_write_fifo(16, w)
tmio_pio_write_fifo(64, q)
tmio_pio_write_fifo(32, l)
tmio_pio_write_fifo(16, w)
static int matsu_sd_pio_write_one_block(struct udevice *dev,
static int tmio_sd_pio_write_one_block(struct udevice *dev,
const char *pbuf, uint blocksize)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
int ret;
/* wait until the buffer becomes empty */
ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
MATSU_SD_INFO2_BWE);
ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
TMIO_SD_INFO2_BWE);
if (ret)
return ret;
matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
if (priv->caps & MATSU_SD_CAP_64BIT)
matsu_pio_write_fifo_64(priv, pbuf, blocksize);
else if (priv->caps & MATSU_SD_CAP_16BIT)
matsu_pio_write_fifo_16(priv, pbuf, blocksize);
if (priv->caps & TMIO_SD_CAP_64BIT)
tmio_pio_write_fifo_64(priv, pbuf, blocksize);
else if (priv->caps & TMIO_SD_CAP_16BIT)
tmio_pio_write_fifo_16(priv, pbuf, blocksize);
else
matsu_pio_write_fifo_32(priv, pbuf, blocksize);
tmio_pio_write_fifo_32(priv, pbuf, blocksize);
return 0;
}
static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
{
const char *src = data->src;
char *dest = data->dest;
@ -264,10 +264,10 @@ static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
for (i = 0; i < data->blocks; i++) {
if (data->flags & MMC_DATA_READ)
ret = matsu_sd_pio_read_one_block(dev, dest,
ret = tmio_sd_pio_read_one_block(dev, dest,
data->blocksize);
else
ret = matsu_sd_pio_write_one_block(dev, src,
ret = tmio_sd_pio_write_one_block(dev, src,
data->blocksize);
if (ret)
return ret;
@ -281,36 +281,36 @@ static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
return 0;
}
static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
dma_addr_t dma_addr)
{
u32 tmp;
matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
/* enable DMA */
tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
tmp |= MATSU_SD_EXTMODE_DMA_EN;
matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
tmp |= TMIO_SD_EXTMODE_DMA_EN;
tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
/* suppress the warning "right shift count >= width of type" */
dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
}
static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
unsigned int blocks)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
long wait = 1000000 + 10 * blocks;
while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
if (wait-- < 0) {
dev_err(dev, "timeout during DMA\n");
return -ETIMEDOUT;
@ -319,7 +319,7 @@ static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
udelay(10);
}
if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
dev_err(dev, "error during DMA\n");
return -EIO;
}
@ -327,9 +327,9 @@ static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
return 0;
}
static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
size_t len = data->blocks * data->blocksize;
void *buf;
enum dma_data_direction dir;
@ -337,7 +337,7 @@ static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
u32 poll_flag, tmp;
int ret;
tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
if (data->flags & MMC_DATA_READ) {
buf = data->dest;
@ -348,24 +348,24 @@ static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
* bit 17 is a hardware bug and forbidden. It is bit 17 on
* Renesas SoCs and bit 20 does not work on them.
*/
poll_flag = (priv->caps & MATSU_SD_CAP_RCAR) ?
MATSU_SD_DMA_INFO1_END_RD :
MATSU_SD_DMA_INFO1_END_RD2;
tmp |= MATSU_SD_DMA_MODE_DIR_RD;
poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ?
TMIO_SD_DMA_INFO1_END_RD :
TMIO_SD_DMA_INFO1_END_RD2;
tmp |= TMIO_SD_DMA_MODE_DIR_RD;
} else {
buf = (void *)data->src;
dir = DMA_TO_DEVICE;
poll_flag = MATSU_SD_DMA_INFO1_END_WR;
tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
poll_flag = TMIO_SD_DMA_INFO1_END_WR;
tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
}
matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
dma_addr = __dma_map_single(buf, len, dir);
matsu_sd_dma_start(priv, dma_addr);
tmio_sd_dma_start(priv, dma_addr);
ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
__dma_unmap_single(dma_addr, len, dir);
@ -373,9 +373,9 @@ static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
}
/* check if the address is DMA'able */
static bool matsu_sd_addr_is_dmaable(unsigned long addr)
static bool tmio_sd_addr_is_dmaable(unsigned long addr)
{
if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
return false;
#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
@ -391,43 +391,43 @@ static bool matsu_sd_addr_is_dmaable(unsigned long addr)
return true;
}
int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
int ret;
u32 tmp;
if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
dev_err(dev, "command busy\n");
return -EBUSY;
}
/* clear all status flags */
matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
/* disable DMA once */
tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
tmp = cmd->cmdidx;
if (data) {
matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
/* Do not send CMD12 automatically */
tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
if (data->blocks > 1)
tmp |= MATSU_SD_CMD_MULTI;
tmp |= TMIO_SD_CMD_MULTI;
if (data->flags & MMC_DATA_READ)
tmp |= MATSU_SD_CMD_RD;
tmp |= TMIO_SD_CMD_RD;
}
/*
@ -438,19 +438,19 @@ int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
*/
switch (cmd->resp_type) {
case MMC_RSP_NONE:
tmp |= MATSU_SD_CMD_RSP_NONE;
tmp |= TMIO_SD_CMD_RSP_NONE;
break;
case MMC_RSP_R1:
tmp |= MATSU_SD_CMD_RSP_R1;
tmp |= TMIO_SD_CMD_RSP_R1;
break;
case MMC_RSP_R1b:
tmp |= MATSU_SD_CMD_RSP_R1B;
tmp |= TMIO_SD_CMD_RSP_R1B;
break;
case MMC_RSP_R2:
tmp |= MATSU_SD_CMD_RSP_R2;
tmp |= TMIO_SD_CMD_RSP_R2;
break;
case MMC_RSP_R3:
tmp |= MATSU_SD_CMD_RSP_R3;
tmp |= TMIO_SD_CMD_RSP_R3;
break;
default:
dev_err(dev, "unknown response type\n");
@ -459,18 +459,18 @@ int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
cmd->cmdidx, tmp, cmd->cmdarg);
matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
MATSU_SD_INFO1_RSP);
ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
TMIO_SD_INFO1_RSP);
if (ret)
return ret;
if (cmd->resp_type & MMC_RSP_136) {
u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
((rsp_103_72 & 0xff000000) >> 24);
@ -481,29 +481,29 @@ int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
} else {
/* bit 39-8 */
cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
}
if (data) {
/* use DMA if the HW supports it and the buffer is aligned */
if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
matsu_sd_addr_is_dmaable((long)data->src))
ret = matsu_sd_dma_xfer(dev, data);
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
tmio_sd_addr_is_dmaable((long)data->src))
ret = tmio_sd_dma_xfer(dev, data);
else
ret = matsu_sd_pio_xfer(dev, data);
ret = tmio_sd_pio_xfer(dev, data);
ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
MATSU_SD_INFO1_CMP);
ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
TMIO_SD_INFO1_CMP);
if (ret)
return ret;
}
matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2, MATSU_SD_INFO2_SCLKDIVEN);
tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN);
return ret;
}
static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
struct mmc *mmc)
{
u32 val, tmp;
@ -511,40 +511,40 @@ static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
switch (mmc->bus_width) {
case 0:
case 1:
val = MATSU_SD_OPTION_WIDTH_1;
val = TMIO_SD_OPTION_WIDTH_1;
break;
case 4:
val = MATSU_SD_OPTION_WIDTH_4;
val = TMIO_SD_OPTION_WIDTH_4;
break;
case 8:
val = MATSU_SD_OPTION_WIDTH_8;
val = TMIO_SD_OPTION_WIDTH_8;
break;
default:
return -EINVAL;
}
tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
tmp |= val;
matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
return 0;
}
static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
struct mmc *mmc)
{
u32 tmp;
tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
if (mmc->ddr_mode)
tmp |= MATSU_SD_IF_MODE_DDR;
tmp |= TMIO_SD_IF_MODE_DDR;
else
tmp &= ~MATSU_SD_IF_MODE_DDR;
matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
tmp &= ~TMIO_SD_IF_MODE_DDR;
tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
}
static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
struct mmc *mmc)
{
unsigned int divisor;
@ -556,54 +556,54 @@ static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
if (divisor <= 1)
val = (priv->caps & MATSU_SD_CAP_RCAR) ?
MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1;
val = (priv->caps & TMIO_SD_CAP_RCAR) ?
TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
else if (divisor <= 2)
val = MATSU_SD_CLKCTL_DIV2;
val = TMIO_SD_CLKCTL_DIV2;
else if (divisor <= 4)
val = MATSU_SD_CLKCTL_DIV4;
val = TMIO_SD_CLKCTL_DIV4;
else if (divisor <= 8)
val = MATSU_SD_CLKCTL_DIV8;
val = TMIO_SD_CLKCTL_DIV8;
else if (divisor <= 16)
val = MATSU_SD_CLKCTL_DIV16;
val = TMIO_SD_CLKCTL_DIV16;
else if (divisor <= 32)
val = MATSU_SD_CLKCTL_DIV32;
val = TMIO_SD_CLKCTL_DIV32;
else if (divisor <= 64)
val = MATSU_SD_CLKCTL_DIV64;
val = TMIO_SD_CLKCTL_DIV64;
else if (divisor <= 128)
val = MATSU_SD_CLKCTL_DIV128;
val = TMIO_SD_CLKCTL_DIV128;
else if (divisor <= 256)
val = MATSU_SD_CLKCTL_DIV256;
else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
val = MATSU_SD_CLKCTL_DIV512;
val = TMIO_SD_CLKCTL_DIV256;
else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
val = TMIO_SD_CLKCTL_DIV512;
else
val = MATSU_SD_CLKCTL_DIV1024;
val = TMIO_SD_CLKCTL_DIV1024;
tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
(tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
if (tmp & TMIO_SD_CLKCTL_SCLKEN &&
(tmp & TMIO_SD_CLKCTL_DIV_MASK) == val)
return;
/* stop the clock before changing its rate to avoid a glitch signal */
tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
tmp |= val | MATSU_SD_CLKCTL_OFFEN;
matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
tmp |= val | TMIO_SD_CLKCTL_OFFEN;
tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
tmp |= MATSU_SD_CLKCTL_SCLKEN;
matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
tmp |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
udelay(1000);
}
static void matsu_sd_set_pins(struct udevice *dev)
static void tmio_sd_set_pins(struct udevice *dev)
{
__maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
#ifdef CONFIG_DM_REGULATOR
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
if (priv->vqmmc_dev) {
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
@ -638,50 +638,50 @@ static void matsu_sd_set_pins(struct udevice *dev)
#endif
}
int matsu_sd_set_ios(struct udevice *dev)
int tmio_sd_set_ios(struct udevice *dev)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc *mmc = mmc_get_mmc_dev(dev);
int ret;
dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
mmc->clock, mmc->ddr_mode, mmc->bus_width);
ret = matsu_sd_set_bus_width(priv, mmc);
ret = tmio_sd_set_bus_width(priv, mmc);
if (ret)
return ret;
matsu_sd_set_ddr_mode(priv, mmc);
matsu_sd_set_clk_rate(priv, mmc);
matsu_sd_set_pins(dev);
tmio_sd_set_ddr_mode(priv, mmc);
tmio_sd_set_clk_rate(priv, mmc);
tmio_sd_set_pins(dev);
return 0;
}
int matsu_sd_get_cd(struct udevice *dev)
int tmio_sd_get_cd(struct udevice *dev)
{
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
return 1;
return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
MATSU_SD_INFO1_CD);
return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
TMIO_SD_INFO1_CD);
}
static void matsu_sd_host_init(struct matsu_sd_priv *priv)
static void tmio_sd_host_init(struct tmio_sd_priv *priv)
{
u32 tmp;
/* soft reset of the host */
tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
tmp &= ~MATSU_SD_SOFT_RST_RSTX;
matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
tmp |= MATSU_SD_SOFT_RST_RSTX;
matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
tmp &= ~TMIO_SD_SOFT_RST_RSTX;
tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
tmp |= TMIO_SD_SOFT_RST_RSTX;
tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
/* FIXME: implement eMMC hw_reset */
matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
/*
* Connected to 32bit AXI.
@ -689,28 +689,28 @@ static void matsu_sd_host_init(struct matsu_sd_priv *priv)
* Write an appropriate value depending on the IP version.
*/
if (priv->version >= 0x10)
matsu_sd_writel(priv, 0x101, MATSU_SD_HOST_MODE);
tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
else
matsu_sd_writel(priv, 0x0, MATSU_SD_HOST_MODE);
tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
}
}
int matsu_sd_bind(struct udevice *dev)
int tmio_sd_bind(struct udevice *dev)
{
struct matsu_sd_plat *plat = dev_get_platdata(dev);
struct tmio_sd_plat *plat = dev_get_platdata(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
int matsu_sd_probe(struct udevice *dev, u32 quirks)
int tmio_sd_probe(struct udevice *dev, u32 quirks)
{
struct matsu_sd_plat *plat = dev_get_platdata(dev);
struct matsu_sd_priv *priv = dev_get_priv(dev);
struct tmio_sd_plat *plat = dev_get_platdata(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
struct clk clk;
@ -761,25 +761,25 @@ int matsu_sd_probe(struct udevice *dev, u32 quirks)
if (quirks)
priv->caps = quirks;
priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
MATSU_SD_VERSION_IP;
priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
TMIO_SD_VERSION_IP;
dev_dbg(dev, "version %x\n", priv->version);
if (priv->version >= 0x10) {
priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
priv->caps |= MATSU_SD_CAP_DIV1024;
priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
priv->caps |= TMIO_SD_CAP_DIV1024;
}
if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
NULL))
priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
matsu_sd_host_init(priv);
tmio_sd_host_init(priv);
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
plat->cfg.f_min = priv->mclk /
(priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
(priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
plat->cfg.f_max = priv->mclk;
plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
upriv->mmc = &plat->mmc;

151
drivers/mmc/tmio-common.h Normal file
View file

@ -0,0 +1,151 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TMIO_COMMON_H__
#define __TMIO_COMMON_H__
#define TMIO_SD_CMD 0x000 /* command */
#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
#define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
#define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
#define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
#define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
#define TMIO_SD_CMD_RSP_NONE (3 << 8)/* response: none */
#define TMIO_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
#define TMIO_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
#define TMIO_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
#define TMIO_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
#define TMIO_SD_ARG 0x008 /* command argument */
#define TMIO_SD_STOP 0x010 /* stop action control */
#define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
#define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
#define TMIO_SD_SECCNT 0x014 /* sector counter */
#define TMIO_SD_RSP10 0x018 /* response[39:8] */
#define TMIO_SD_RSP32 0x020 /* response[71:40] */
#define TMIO_SD_RSP54 0x028 /* response[103:72] */
#define TMIO_SD_RSP76 0x030 /* response[127:104] */
#define TMIO_SD_INFO1 0x038 /* IRQ status 1 */
#define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
#define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
#define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
#define TMIO_SD_INFO1_CMP BIT(2) /* data complete */
#define TMIO_SD_INFO1_RSP BIT(0) /* response complete */
#define TMIO_SD_INFO2 0x03c /* IRQ status 2 */
#define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
#define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */
#define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
#define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */
#define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */
#define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
#define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */
#define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
#define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
#define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */
#define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */
#define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
#define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
#define TMIO_SD_INFO1_MASK 0x040
#define TMIO_SD_INFO2_MASK 0x044
#define TMIO_SD_CLKCTL 0x048 /* clock divisor */
#define TMIO_SD_CLKCTL_DIV_MASK 0x104ff
#define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
#define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
#define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
#define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
#define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
#define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
#define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
#define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
#define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
#define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
#define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
#define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
#define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
#define TMIO_SD_SIZE 0x04c /* block size */
#define TMIO_SD_OPTION 0x050
#define TMIO_SD_OPTION_WIDTH_MASK (5 << 13)
#define TMIO_SD_OPTION_WIDTH_1 (4 << 13)
#define TMIO_SD_OPTION_WIDTH_4 (0 << 13)
#define TMIO_SD_OPTION_WIDTH_8 (1 << 13)
#define TMIO_SD_BUF 0x060 /* read/write buffer */
#define TMIO_SD_EXTMODE 0x1b0
#define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
#define TMIO_SD_SOFT_RST 0x1c0
#define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
#define TMIO_SD_VERSION 0x1c4 /* version register */
#define TMIO_SD_VERSION_IP 0xff /* IP version */
#define TMIO_SD_HOST_MODE 0x1c8
#define TMIO_SD_IF_MODE 0x1cc
#define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
#define TMIO_SD_VOLT 0x1e4 /* voltage switch */
#define TMIO_SD_VOLT_MASK (3 << 0)
#define TMIO_SD_VOLT_OFF (0 << 0)
#define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */
#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
#define TMIO_SD_DMA_MODE 0x410
#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
#define TMIO_SD_DMA_CTL 0x414
#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
#define TMIO_SD_DMA_RST 0x418
#define TMIO_SD_DMA_RST_RD BIT(9)
#define TMIO_SD_DMA_RST_WR BIT(8)
#define TMIO_SD_DMA_INFO1 0x420
#define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
#define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
#define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
#define TMIO_SD_DMA_INFO1_MASK 0x424
#define TMIO_SD_DMA_INFO2 0x428
#define TMIO_SD_DMA_INFO2_ERR_RD BIT(17)
#define TMIO_SD_DMA_INFO2_ERR_WR BIT(16)
#define TMIO_SD_DMA_INFO2_MASK 0x42c
#define TMIO_SD_DMA_ADDR_L 0x440
#define TMIO_SD_DMA_ADDR_H 0x444
/* alignment required by the DMA engine of this controller */
#define TMIO_SD_DMA_MINALIGN 0x10
struct tmio_sd_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct tmio_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
u32 caps;
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
#define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
#define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
#define TMIO_SD_CAP_RCAR \
(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
};
int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data);
int tmio_sd_set_ios(struct udevice *dev);
int tmio_sd_get_cd(struct udevice *dev);
int tmio_sd_bind(struct udevice *dev);
int tmio_sd_probe(struct udevice *dev, u32 quirks);
u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg);
void tmio_sd_writel(struct tmio_sd_priv *priv,
u32 val, unsigned int reg);
#endif /* __TMIO_COMMON_H__ */

16
drivers/mmc/uniphier-sd.c
View file

@ -17,12 +17,12 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
#include "matsushita-common.h"
#include "tmio-common.h"
static const struct dm_mmc_ops uniphier_sd_ops = {
.send_cmd = matsu_sd_send_cmd,
.set_ios = matsu_sd_set_ios,
.get_cd = matsu_sd_get_cd,
.send_cmd = tmio_sd_send_cmd,
.set_ios = tmio_sd_set_ios,
.get_cd = tmio_sd_get_cd,
};
static const struct udevice_id uniphier_sd_match[] = {
@ -32,16 +32,16 @@ static const struct udevice_id uniphier_sd_match[] = {
static int uniphier_sd_probe(struct udevice *dev)
{
return matsu_sd_probe(dev, 0);
return tmio_sd_probe(dev, 0);
}
U_BOOT_DRIVER(uniphier_mmc) = {
.name = "uniphier-mmc",
.id = UCLASS_MMC,
.of_match = uniphier_sd_match,
.bind = matsu_sd_bind,
.bind = tmio_sd_bind,
.probe = uniphier_sd_probe,
.priv_auto_alloc_size = sizeof(struct matsu_sd_priv),
.platdata_auto_alloc_size = sizeof(struct matsu_sd_plat),
.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
.ops = &uniphier_sd_ops,
};

3
drivers/net/sh_eth.c
View file

@ -906,7 +906,10 @@ int sh_ether_ofdata_to_platdata(struct udevice *dev)
}
static const struct udevice_id sh_ether_ids[] = {
{ .compatible = "renesas,ether-r8a7790" },
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
{ .compatible = "renesas,ether-r8a7794" },
{ }
};

2
drivers/serial/serial_sh.c
View file

@ -270,6 +270,8 @@ U_BOOT_DRIVER(serial_sh) = {
# define SCIF_BASE SCIF6_BASE
#elif defined(CONFIG_CONS_SCIF7)
# define SCIF_BASE SCIF7_BASE
#elif defined(CONFIG_CONS_SCIFA0)
# define SCIF_BASE SCIFA0_BASE
#else
# error "Default SCIF doesn't set....."
#endif

8
include/configs/porter.h
View file

@ -54,13 +54,11 @@
"initrd_high=0xffffffff\0"
/* SPL support */
#define CONFIG_SPL_TEXT_BASE 0xe6304000
#define CONFIG_SPL_TEXT_BASE 0xe6300000
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
/* TPL support */
#ifdef CONFIG_TPL_BUILD
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
#endif

55
include/configs/stout.h
View file

@ -17,14 +17,9 @@
#include "rcar-gen2-common.h"
/* STACK */
#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
#endif
#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
#define STACK_AREA_SIZE 0x00100000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
@ -43,47 +38,31 @@
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_RCAR
#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SYS_TMU_CLK_DIV 4
/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0"
/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA 0x00400000
/* MSIF, SCIFA0 */
#define CONFIG_SMSTP2_ENA 0x00002010
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA 0x00000180
/* SDHI */
#define CONFIG_SH_SDHI_FREQ 97500000
/* SPL support */
#define CONFIG_SPL_TEXT_BASE 0xe6300000
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIFA0
#define CONFIG_SH_SCIF_CLK_FREQ 52000000
#endif
#endif /* __STOUT_H */