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https://github.com/AsahiLinux/u-boot
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arm: powerpc: Tidy up code style for cache functions
Remove the unwanted space before the bracket. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
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62270f4395
commit
6cc915b5fb
6 changed files with 28 additions and 24 deletions
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@ -253,17 +253,17 @@ static void cache_disable(uint32_t cache_bit)
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#endif
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#endif
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#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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void icache_enable (void)
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void icache_enable(void)
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{
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{
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return;
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return;
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}
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}
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void icache_disable (void)
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void icache_disable(void)
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{
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{
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return;
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return;
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}
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}
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int icache_status (void)
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int icache_status(void)
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{
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{
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return 0; /* always off */
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return 0; /* always off */
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}
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}
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@ -285,17 +285,17 @@ int icache_status(void)
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#endif
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#endif
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#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void dcache_enable (void)
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void dcache_enable(void)
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{
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{
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return;
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return;
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}
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}
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void dcache_disable (void)
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void dcache_disable(void)
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{
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{
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return;
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return;
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}
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}
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int dcache_status (void)
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int dcache_status(void)
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{
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{
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return 0; /* always off */
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return 0; /* always off */
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}
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}
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@ -8,7 +8,7 @@
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#include <common.h>
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#include <common.h>
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#include <asm/asm.h>
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#include <asm/asm.h>
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int dcache_status (void)
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int dcache_status(void)
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{
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{
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int i = 0;
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int i = 0;
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int mask = 0x80;
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int mask = 0x80;
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@ -18,7 +18,7 @@ int dcache_status (void)
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return i;
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return i;
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}
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}
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int icache_status (void)
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int icache_status(void)
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{
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{
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int i = 0;
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int i = 0;
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int mask = 0x20;
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int mask = 0x20;
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@ -28,28 +28,32 @@ int icache_status (void)
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return i;
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return i;
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}
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}
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void icache_enable (void) {
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void icache_enable(void)
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{
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MSRSET(0x20);
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MSRSET(0x20);
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}
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}
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void icache_disable(void) {
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void icache_disable(void)
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{
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/* we are not generate ICACHE size -> flush whole cache */
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/* we are not generate ICACHE size -> flush whole cache */
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flush_cache(0, 32768);
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flush_cache(0, 32768);
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MSRCLR(0x20);
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MSRCLR(0x20);
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}
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}
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void dcache_enable (void) {
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void dcache_enable(void)
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{
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MSRSET(0x80);
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MSRSET(0x80);
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}
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}
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void dcache_disable(void) {
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void dcache_disable(void)
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{
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#ifdef XILINX_USE_DCACHE
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#ifdef XILINX_USE_DCACHE
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flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
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flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
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#endif
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#endif
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MSRCLR(0x80);
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MSRCLR(0x80);
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}
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}
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void flush_cache (ulong addr, ulong size)
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void flush_cache(ulong addr, ulong size)
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{
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{
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int i;
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int i;
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for (i = 0; i < size; i += 4)
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for (i = 0; i < size; i += 4)
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@ -109,7 +109,7 @@ extern void cm_remap(void);
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writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
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writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
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#endif
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#endif
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icache_enable ();
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icache_enable();
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return 0;
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return 0;
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}
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}
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@ -164,8 +164,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
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* chip is in programming mode.
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* chip is in programming mode.
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*/
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*/
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cflag = icache_status ();
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cflag = icache_status();
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icache_disable ();
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icache_disable();
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iflag = disable_interrupts ();
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iflag = disable_interrupts ();
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printf ("\n");
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printf ("\n");
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@ -237,7 +237,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
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enable_interrupts ();
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enable_interrupts ();
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if (cflag)
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if (cflag)
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icache_enable ();
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icache_enable();
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return rc;
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return rc;
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}
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}
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@ -267,8 +267,8 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
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* chip is in programming mode.
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* chip is in programming mode.
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*/
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*/
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cflag = icache_status ();
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cflag = icache_status();
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icache_disable ();
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icache_disable();
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iflag = disable_interrupts ();
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iflag = disable_interrupts ();
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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@ -303,7 +303,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
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enable_interrupts ();
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enable_interrupts ();
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if (cflag)
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if (cflag)
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icache_enable ();
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icache_enable();
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return rc;
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return rc;
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}
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}
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@ -189,7 +189,7 @@ int testdram(void);
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int icache_status (void);
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int icache_status (void);
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void icache_enable (void);
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void icache_enable (void);
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void icache_disable(void);
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void icache_disable(void);
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int dcache_status (void);
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int dcache_status(void);
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void dcache_enable (void);
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void dcache_enable (void);
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void dcache_disable(void);
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void dcache_disable(void);
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void mmu_disable(void);
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void mmu_disable(void);
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@ -57,12 +57,12 @@ ulong cpu_post_makecr (long v)
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int cpu_post_test (int flags)
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int cpu_post_test (int flags)
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{
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{
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int ic = icache_status ();
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int ic = icache_status();
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int ret = 0;
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int ret = 0;
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WATCHDOG_RESET();
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WATCHDOG_RESET();
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if (ic)
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if (ic)
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icache_disable ();
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icache_disable();
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if (ret == 0)
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if (ret == 0)
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ret = cpu_post_test_cmp ();
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ret = cpu_post_test_cmp ();
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@ -110,7 +110,7 @@ int cpu_post_test (int flags)
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WATCHDOG_RESET();
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WATCHDOG_RESET();
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if (ic)
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if (ic)
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icache_enable ();
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icache_enable();
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WATCHDOG_RESET();
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WATCHDOG_RESET();
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