Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-14 00:47:26 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge tag 'u-boot-imx-20240115' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse source
This commit is contained in:
Tom Rini 2024-01-16 09:49:48 -05:00
commit 6ca9349b67
23 changed files with 1070 additions and 201 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/dts/Makefile
View file

@ -1076,6 +1076,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phygate-tauri-l.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \

70
arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi Normal file
View file

@ -0,0 +1,70 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#include "imx8mm-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&pinctrl_uart3 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&uart3 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
&usdhc3 {
bootph-pre-ram;
};
&wdog1 {
bootph-pre-ram;
};

489
arch/arm/dts/imx8mm-phygate-tauri-l.dts Normal file
View file

@ -0,0 +1,489 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include "imx8mm-phycore-som.dtsi"
/ {
model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
compatible = "phytec,imx8mm-phygate-tauri-l",
"phytec,imx8mm-phycore-som", "fsl,imx8mm";
chosen {
stdout-path = &uart3;
};
can_osc_40m: clock-can {
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "can_osc_40m";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
key {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
label = "KEY-A";
linux,code = <KEY_A>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
led-2 {
color = <LED_COLOR_ID_YELLOW>;
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
};
usdhc1_pwrseq: pwr-seq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <60>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
};
reg_usb_hub_vbus: regulator-hub-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhubpwr>;
regulator-name = "usb_hub_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1pwr>;
regulator-name = "usb_otg1_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
};
};
&ecspi1 {
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* CAN MCP251XFD */
can0: can@0 {
compatible = "microchip,mcp251xfd";
reg = <0>;
clocks = <&can_osc_40m>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
spi-max-frequency = <10000000>;
};
tpm: tpm@1 {
compatible = "tcg,tpm_tis-spi";
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
reg = <1>;
spi-max-frequency = <38000000>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
temp_sense0: temperature-sensor@49 {
compatible = "ti,tmp102";
reg = <0x49>;
interrupt-parent = <&gpio4>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tempsense>;
#thermal-sensor-cells = <1>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
/* RTC */
&rv3028 {
trickle-resistor-ohms = <3000>;
};
&uart1 {
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* UART2 - RS232 */
&uart2 {
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* UART - console */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* USB */
&usbotg1 {
adp-disable;
dr_mode = "otg";
over-current-active-low;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
vbus-supply = <&reg_usb_hub_vbus>;
status = "okay";
};
/* SD-Card */
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&reg_nvcc_sd2>;
status = "okay";
};
&iomuxc {
pinctrl_can_int: can-intgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
>;
};
pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
>;
};
pinctrl_gpiokeys: keygrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* COEX2 */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
/* COEX1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
>;
};
pinctrl_tempsense: tempsensegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usbhubpwr: usbhubpwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
>;
};
pinctrl_usbotg1pwr: usbotg1pwrgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
>;
};
pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

39
arch/arm/mach-imx/imx8m/Kconfig
View file

@ -2,6 +2,7 @@ if ARCH_IMX8M
config IMX8M
bool
select BINMAN
select GICV3 if ARMV8_PSCI
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
@ -41,13 +42,11 @@ choice
config TARGET_IMX8MQ_CM
bool "Ronetix iMX8MQ-CM SoM"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
select FSL_CAAM
@ -56,26 +55,22 @@ config TARGET_IMX8MQ_EVK
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MQ_REFORM2
bool "imx8mq_reform2"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
select BINMAN
select IMX8MM
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -85,7 +80,6 @@ config TARGET_IMX8MM_EVK
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -104,21 +98,18 @@ config TARGET_IMX8MM_ICORE_MX8MM
config TARGET_IMX8MM_MX8MENLO
bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_PHG
bool "i.MX8MM PHG board"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -130,7 +121,6 @@ config TARGET_IMX8MM_VENICE
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -140,21 +130,18 @@ config TARGET_KONTRON_MX8MM
config TARGET_IMX8MN_BSH_SMM_S2
bool "imx8mn-bsh-smm-s2"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_BSH_SMM_S2PRO
bool "imx8mn-bsh-smm-s2pro"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -163,7 +150,6 @@ config TARGET_IMX8MN_EVK
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
@ -172,7 +158,6 @@ config TARGET_IMX8MN_DDR4_EVK
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -184,14 +169,12 @@ config TARGET_IMX8MN_VENICE
config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Plus"
select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_BEACON
bool "imx8mm Beacon Embedded devkit"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -201,21 +184,18 @@ config TARGET_IMX8MP_BEACON
config TARGET_IMX8MP_DEBIX_MODEL_A
bool "Polyhex i.MX8M Plus Debix Model A SBC"
select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_ICORE_MX8MP
bool "Engicam i.Core MX8M Plus SOM"
select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
@ -229,7 +209,6 @@ config TARGET_IMX8MP_ICORE_MX8MP
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -239,7 +218,6 @@ config TARGET_IMX8MP_EVK
config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -251,13 +229,11 @@ config TARGET_IMX8MP_VENICE
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MN_VAR_SOM
bool "Variscite imx8mn_var_som"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
@ -268,27 +244,23 @@ config TARGET_IMX8MN_VAR_SOM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MP
bool "Support Toradex Verdin iMX8M Plus module"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -298,7 +270,6 @@ config TARGET_IMX8MM_BEACON
config TARGET_IMX8MN_BEACON
bool "imx8mn Beacon Embedded devkit"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -308,21 +279,18 @@ config TARGET_IMX8MN_BEACON
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_CL_IOT_GATE
bool "CompuLab iot-gate-imx8"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -330,7 +298,6 @@ config TARGET_IMX8MM_CL_IOT_GATE
config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
bool "CompuLab iot-gate-imx8 with optee support"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@ -338,28 +305,24 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
config TARGET_IMX8MP_RSB3720A1_4G
bool "Support i.MX8MP RSB3720A1 4G"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MP_RSB3720A1_6G
bool "Support i.MX8MP RSB3720A1 6G"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_MSC_SM2S_IMX8MP
bool "MSC SMARC2 i.MX8MPLUS"
select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_LIBREM5
bool "Purism Librem5 Phone"
select BINMAN
select IMX8MQ
select SUPPORT_SPL
select IMX8M_LPDDR4

3
arch/arm/mach-imx/imx9/Kconfig
View file

@ -12,6 +12,7 @@ config IMX9_LOW_DRIVE_MODE
config IMX9
bool
select BINMAN
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
@ -29,12 +30,10 @@ choice
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
select BINMAN
select IMX93
config TARGET_IMX93_VAR_SOM
bool "imx93_var_som"
select BINMAN
select IMX93
select IMX9_LPDDR4X

45
arch/arm/mach-imx/imx9/soc.c
View file

@ -507,8 +507,53 @@ int print_cpuinfo(void)
return 0;
}
static int fixup_thermal_trips(void *blob, const char *name)
{
int minc, maxc;
int node, trip;
node = fdt_path_offset(blob, "/thermal-zones");
if (node < 0)
return node;
node = fdt_subnode_offset(blob, node, name);
if (node < 0)
return node;
node = fdt_subnode_offset(blob, node, "trips");
if (node < 0)
return node;
get_cpu_temp_grade(&minc, &maxc);
fdt_for_each_subnode(trip, blob, node) {
const char *type;
int temp, ret;
type = fdt_getprop(blob, trip, "type", NULL);
if (!type)
continue;
temp = 0;
if (!strcmp(type, "critical"))
temp = 1000 * (maxc - 5);
else if (!strcmp(type, "passive"))
temp = 1000 * (maxc - 10);
if (temp) {
ret = fdt_setprop_u32(blob, trip, "temperature", temp);
if (ret)
return ret;
}
}
return 0;
}
int ft_system_setup(void *blob, struct bd_info *bd)
{
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
return 0;
}

27
board/liebherr/xea/boot_img_scr.h Normal file
View file

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Struct for boot image source description for placing in last
* two SPI NOR flash sectors on legcom.
*/
struct boot_img_src {
u8 magic; /* Must be 'B' = 0x42 */
u8 flags; /* flags to specify mmcblk[0|1] boot[0|1] */
u8 crc8; /* CRC-8 over above two bytes */
} __packed;
/*
* Bit definition in boot_img_src.flags:
* Bit 0: mmcblk device 0 or 1 (1 - if this bit set)
* Bit 1: mmcblk boot partition 0 or 1.
* for eMMC: boot0 if this bit is cleared, boot1 - if set
* for SD-card the boot partition value will always be 0
* (independent of the value of this bit)
*
*/
#define BOOT_SRC_MMC1 BIT(0)
#define BOOT_SRC_PART1 BIT(1)
/* Offset of the first boot image source descriptor in SPI NOR */
#define SPI_FLASH_BOOT_SRC_OFFS 0xFE0000
#define SPI_FLASH_SECTOR_SIZE 0x10000

85
board/liebherr/xea/xea.c
View file

@ -32,6 +32,11 @@
#include <errno.h>
#include <usb.h>
#include <serial.h>
#include <u-boot/crc.h>
#include "boot_img_scr.h"
#include <spi.h>
#include <spi_flash.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
@ -66,6 +71,52 @@ void board_init_f(ulong arg)
preloader_console_init();
}
static struct boot_img_src img_src[2];
static int spi_load_boot_info(void)
{
struct spi_flash *flash;
int err;
flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
CONFIG_SF_DEFAULT_CS,
CONFIG_SF_DEFAULT_SPEED,
CONFIG_SF_DEFAULT_MODE);
if (!flash) {
printf("%s: SPI probe err\n", __func__);
return -ENODEV;
}
/*
* Load both boot info structs from SPI flash
*/
err = spi_flash_read(flash, SPI_FLASH_BOOT_SRC_OFFS,
sizeof(img_src[0]),
(void *)&img_src[0]);
if (err) {
debug("%s: First boot info NOR sector read error %d\n",
__func__, err);
return err;
}
err = spi_flash_read(flash,
SPI_FLASH_BOOT_SRC_OFFS + SPI_FLASH_SECTOR_SIZE,
sizeof(img_src[0]),
(void *)&img_src[1]);
if (err) {
debug("%s: First boot info NOR sector read error %d\n",
__func__, err);
return err;
}
debug("%s: BI0 0x%x 0x%x 0x%x\n", __func__,
img_src[0].magic, img_src[0].flags, img_src[0].crc8);
debug("%s: BI1 0x%x 0x%x 0x%x\n", __func__,
img_src[1].magic, img_src[1].flags, img_src[1].crc8);
return 0;
}
static int boot_tiva0, boot_tiva1;
/* Check if TIVAs request booting via U-Boot proper */
@ -114,6 +165,40 @@ void spl_board_init(void)
boot_tiva1 = dm_gpio_get_value(&btiva1);
}
int spl_mmc_emmc_boot_partition(struct mmc *mmc)
{
int i, src_idx = -1, ret;
ret = spi_load_boot_info();
if (ret) {
printf("%s: Cannot read XEA boot info! [%d]\n", __func__, ret);
/* To avoid bricking board - by default boot from boot0 eMMC */
return 1;
}
for (i = 0; i < 2; i++) {
if (img_src[i].magic == 'B' &&
img_src[i].crc8 == crc8(0, &img_src[i].magic, 2)) {
src_idx = i;
break;
}
}
debug("%s: src idx: %d\n", __func__, src_idx);
if (src_idx < 0)
/*
* Always use eMMC (mmcblkX) boot0 if no
* valid image source description found
*/
return 1;
if (img_src[src_idx].flags & BOOT_SRC_PART1)
return 2;
return 1;
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_MMC1;

139
board/liebherr/xea/xea.env Normal file
View file

@ -0,0 +1,139 @@
bootmode=update
bootpri=mmc_mmc
bootsec=sf_swu
consdev=ttyAMA0
baudrate=115200
dtbfile=imx28-xea.dtb
rootdev=/dev/mmcblk0p2
netdev=eth0
swufile=swupdate-image-xea-upd.itb
sf_kernel_offset=0xA0000
sf_swu_size=0xF40000
ethact=FEC
arch=xea
lwe_env=
if dhcp ${loadaddr} ${hostname}/${lwe_uenv} ; then
source ${loadaddr};
fi
lwe_uenv=env_uboot_xea.bin
do_update_mmc=
if mmc rescan ; then
mmc dev 0 ${update_mmc_part} ;
if dhcp ${hostname}/${update_filename} ; then
setexpr fw_sz ${filesize} / 0x200 ;
setexpr fw_sz ${fw_sz} + 1 ;
mmc write ${loadaddr} ${update_offset} ${fw_sz} ;
fi ;
fi
do_update_sf=
if sf probe ; then
if dhcp ${hostname}/${update_filename} ; then
sf erase ${update_offset} +${filesize} ;
sf write ${loadaddr} ${update_offset} ${filesize} ;
fi ;
fi
factory_reset=
if sf probe ; then
run update_swu ;
setenv bootmode update ;
saveenv ;
fi
update_spl_filename=u-boot.sb
update_spl=
setenv update_filename ${update_spl_filename} ;
setenv update_offset 0 ;
run do_update_sf
update_uboot_filename=u-boot.img
update_uboot=
setenv update_filename ${update_uboot_filename} ;
setenv update_offset 0x10000 ;
run do_update_sf ;
setenv update_mmc_part 1 ;
setenv update_offset 0 ;
run do_update_mmc ;
setenv update_mmc_part 2 ;
run do_update_mmc
update_kernel_filename=uImage
update_kernel=
setenv update_mmc_part 1 ;
setenv update_filename ${update_kernel_filename} ;
setenv update_offset 0x800 ;
run do_update_mmc ;
setenv update_filename ${dtbfile} ;
setenv update_offset 0x400 ;
run do_update_mmc
update_swu=
setenv update_filename ${swufile} ;
setenv update_offset ${sf_kernel_offset} ;
run do_update_sf
addcons=
setenv bootargs ${bootargs}
console=${consdev},${baudrate}
addip=
setenv bootargs ${bootargs}
ip=${ipaddr}:${serverip}:${gatewayip}:
${netmask}:${hostname}:${netdev}:off
addmisc=
setenv bootargs ${bootargs} ${miscargs}
addargs=run addcons addmisc
mmcload=
mmc rescan ;
mmc dev 0 1 ;
mmc read ${loadaddr} 0x800 0x2000 ;
mmc read ${dtbaddr} 0x400 0x80
netload=
dhcp ${loadaddr} ${hostname}/${bootfile} ;
tftp ${dtbaddr} ${hostname}/${dtbfile}
usbload=
usb start ;
load usb 0:1 ${loadaddr} ${bootfile}
miscargs=panic=1
mmcargs=setenv bootargs root=${rootdev} rw rootwait
nfsargs=
setenv bootargs root=/dev/nfs rw
nfsroot=${serverip}:${rootpath},v3,tcp
mmc_mmc=
if run mmcload mmcargs addargs ; then
bootm ${loadaddr} - ${dtbaddr} ;
fi
mmc_nfs=
if run mmcload nfsargs addip addargs ; then
bootm ${loadaddr} - ${dtbaddr} ;
fi
sf_mmc=
if run sfload mmcargs addargs ; then
bootm ${loadaddr} - ${dtbaddr} ;
fi
sf_swu=
if sf probe ; then
sf read ${loadaddr} ${sf_kernel_offset} ${sf_swu_size} ;
setenv bootargs root=/dev/ram0 rw ;
run addargs ;
bootm ${loadaddr} ;
fi
net_mmc=
if run netload mmcargs addargs ; then
bootm ${loadaddr} - ${dtbaddr} ;
fi
net_nfs=
if run netload nfsargs addip addargs ; then
bootm ${loadaddr} - ${dtbaddr} ;
fi
prebootcmd=
if test ${envsaved} != y ; then ;
setenv envsaved y ;
saveenv ;
fi ;
if test ${bootmode} = normal ; then
setenv bootdelay 0 ;
setenv bootpri mmc_mmc ;
elif test ${bootmode} = devel ; then
setenv bootdelay 3 ;
setenv bootpri net_mmc ;
else
if test ${bootmode} != update ; then
echo Warning: unknown bootmode ${bootmode} ;
fi ;
setenv bootdelay 1 ;
setenv bootpri sf_swu ;
fi

4
board/phytec/common/Makefile
View file

@ -7,5 +7,5 @@ ifdef CONFIG_SPL_BUILD
obj- := __dummy__.o
endif
obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o
obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o
obj-y += phytec_som_detection.o
obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o

2
board/phytec/common/phytec_som_detection.c
View file

@ -5,8 +5,6 @@
*/
#include <common.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <i2c.h>

6
board/phytec/phycore_imx8mm/MAINTAINERS
View file

@ -5,6 +5,12 @@ S: Maintained
F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
F: arch/arm/dts/imx8mm-phycore-som.dtsi
F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
F: arch/arm/dts/imx8mm-phygate-tauri-l.dts
F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
F: board/phytec/phycore_imx8mm/
F: configs/imx8mm-phygate-tauri-l_defconfig
F: configs/phycore-imx8mm_defconfig
F: doc/board/phytec/imx8mm-phygate-tauri-l.rst
F: doc/board/phytec/index.rst
F: doc/board/phytec/phycore_imx8mm.rst
F: include/configs/phycore_imx8mm.h

1
board/phytec/phycore_imx8mp/MAINTAINERS
View file

@ -6,4 +6,5 @@ F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mp/
F: configs/phycore-imx8mp_defconfig
F: doc/board/phytec/phycore-imx8mp.rst
F: include/configs/phycore_imx8mp.h

1
configs/imx28_xea_defconfig
View file

@ -123,4 +123,5 @@ CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXS_SPI=y
CONFIG_SPL_CRC8=y
# CONFIG_SPL_OF_LIBFDT is not set

2
configs/imx28_xea_sb_defconfig
View file

@ -74,7 +74,7 @@ CONFIG_MMC_MXS=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_SPANSION=y

115
configs/imx8mm-phygate-tauri-l_defconfig Normal file
View file

@ -0,0 +1,115 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x920000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=4096
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_WATCHDOG=y

60
doc/board/phytec/imx8mm-phygate-tauri-l.rst Normal file
View file

@ -0,0 +1,60 @@
.. SPDX-License-Identifier: GPL-2.0+
phyGATE-Tauri-L-i.MX 8M Mini
============================
The phyGATE-Tauri-L-i.MX 8M Mini with 2GB of main memory is supported.
Quick Start
-----------
- Build the ARM Trusted firmware binary
- Get ddr firmware
- Build U-Boot
- Boot
Build the ARM Trusted firmware binary
-------------------------------------
.. code-block:: bash
$ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
$ cd trusted-firmware-a
$ export CROSS_COMPILE=aarch64-linux-gnu
$ export IMX_BOOT_UART_BASE=0x30880000
$ make PLAT=imx8mm bl31
Get the ddr firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin
$ chmod +x firmware-imx-8.23.bin
$ ./firmware-imx-8.23.bin
Build U-Boot for SD card
------------------------
Copy binaries
^^^^^^^^^^^^^
.. code-block:: bash
$ cp <TF-A dir>/build/imx8mm/release/bl31.bin .
$ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*.bin .
Build U-Boot
^^^^^^^^^^^^
.. code-block:: bash
$ make imx8mm-phygate-tauri-l_defconfig
$ make flash.bin
Flash SD card
^^^^^^^^^^^^^
.. code-block:: bash
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=sync

1
doc/board/phytec/index.rst
View file

@ -6,5 +6,6 @@ PHYTEC
.. toctree::
:maxdepth: 2
imx8mm-phygate-tauri-l
phycore-imx8mm
phycore-imx8mp

4
doc/board/variscite/imx93_var_som.rst
View file

@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
imx93_var_som
=======================
=============
U-Boot for the Variscite VAR-SOM-MX93 Symphony evaluation board
@ -38,7 +38,7 @@ Get the DDR firmware
$ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Get ahab-container.img
---------------------------------------
----------------------
.. code-block:: bash

11
include/configs/imx8mm_data_modul_edm_sbc.h
View file

@ -34,13 +34,11 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
"bootlimit=3\0" \
"devtype=mmc\0" \
"devpart=1\0" \
/* Give slow devices beyond USB HUB chance to come up. */ \
"usb_pgood_delay=2000\0" \
"dfu_alt_info=" \
/* RAM block at DRAM offset 256..768 MiB */ \
"ram ram0=ram ram 0x50000000 0x20000000&" \
@ -76,6 +74,11 @@
"setenv stderr ${stderr},nc && " \
"setenv stdout ${stdout},nc && " \
"setenv stdin ${stdin},nc ; " \
"fi"
"fi\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
/* Give slow devices beyond USB HUB chance to come up. */ \
"usb_pgood_delay=2000\0"
#endif

9
include/configs/imx8mp_data_modul_edm_sbc.h
View file

@ -29,8 +29,6 @@
"bootlimit=3\0" \
"devtype=mmc\0" \
"devpart=1\0" \
/* Give slow devices beyond USB HUB chance to come up. */ \
"usb_pgood_delay=2000\0" \
"dmo_update_env=" \
"setenv dmo_update_env true ; saveenv ; saveenv\0" \
"dmo_update_sf_write_data=" \
@ -40,6 +38,11 @@
"run dmo_update_sf_write_data\0" \
"dmo_update_sd_to_sf=" \
"load mmc 1:1 ${loadaddr} boot/flash.bin && " \
"run dmo_update_sf_write_data\0"
"run dmo_update_sf_write_data\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
/* Give slow devices beyond USB HUB chance to come up. */ \
"usb_pgood_delay=2000\0"
#endif

17
include/configs/imx8mp_dhcom_pdk2.h
View file

@ -28,15 +28,9 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"altbootcmd=run bootcmd ; reset\0" \
"bootlimit=3\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x58000000\0" \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
/* Give slow devices beyond USB HUB chance to come up. */ \
"usb_pgood_delay=2000\0" \
"dfu_alt_info=" \
/* RAM block at DRAM offset 256..768 MiB */ \
"ram ram0=ram ram 0x50000000 0x20000000&" \
@ -68,6 +62,15 @@
"dh_update_emmc_to_sf=" \
"load mmc 1:1 ${loadaddr} boot/flash.bin && " \
"run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x58000000\0" \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
/* Give slow devices beyond USB HUB chance to come up. */ \
"usb_pgood_delay=2000\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \

140
include/configs/xea.h
View file

@ -25,146 +25,6 @@
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environment */
#define CFG_EXTRA_ENV_SETTINGS \
"bootmode=update\0" \
"bootpri=mmc_mmc\0" \
"bootsec=sf_swu\0" \
"consdev=ttyAMA0\0" \
"baudrate=115200\0" \
"dtbaddr=0x44000000\0" \
"dtbfile=imx28-xea.dtb\0" \
"rootdev=/dev/mmcblk0p2\0" \
"netdev=eth0\0" \
"rdaddr=0x43000000\0" \
"swufile=swupdate.img\0" \
"sf_kernel_offset=0x100000\0" \
"sf_kernel_size=0x400000\0" \
"sf_swu_offset=0x500000\0" \
"sf_swu_size=0x800000\0" \
"rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \
"do_update_mmc=" \
"if mmc rescan ; then " \
"mmc dev 0 ${update_mmc_part} ; " \
"if dhcp ${hostname}/${update_filename} ; then " \
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
"setexpr fw_sz ${fw_sz} + 1 ; " \
"mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
"fi ; " \
"fi\0" \
"do_update_sf=" \
"if sf probe ; then " \
"if dhcp ${hostname}/${update_filename} ; then " \
"sf erase ${update_offset} +${filesize} ; " \
"sf write ${loadaddr} ${update_offset} ${filesize} ; " \
"fi ; " \
"fi\0" \
"update_spl_filename=u-boot.sb\0" \
"update_spl=" \
"setenv update_filename ${update_spl_filename} ; " \
"setenv update_offset 0 ; " \
"run do_update_sf\0" \
"update_uboot_filename=u-boot.img\0" \
"update_uboot=" \
"setenv update_filename ${update_uboot_filename} ; " \
"setenv update_offset 0x10000 ; " \
"run do_update_sf ; " \
"setenv update_mmc_part 1 ; " \
"setenv update_offset 0 ; " \
"run do_update_mmc\0" \
"update_kernel_filename=uImage\0" \
"update_kernel=" \
"setenv update_mmc_part 1 ; " \
"setenv update_filename ${update_kernel_filename} ; " \
"setenv update_offset 0x800 ; " \
"run do_update_mmc ; " \
"setenv update_filename ${dtbfile} ; " \
"setenv update_offset 0x400 ; " \
"run do_update_mmc\0" \
"update_sfkernel=" \
"setenv update_filename fitImage ; " \
"setenv update_offset ${sf_kernel_offset} ; " \
"run do_update_sf\0" \
"update_swu=" \
"setenv update_filename ${swufile} ; " \
"setenv update_offset ${sf_swu_offset} ; " \
"run do_update_sf\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
"addip=" \
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:${netdev}:off\0" \
"addmisc=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc\0" \
"mmcload=" \
"mmc rescan ; " \
"mmc dev 0 1 ; " \
"mmc read ${loadaddr} 0x800 0x2000 ; " \
"mmc read ${dtbaddr} 0x400 0x80\0" \
"netload=" \
"dhcp ${loadaddr} ${hostname}/${bootfile} ; " \
"tftp ${dtbaddr} ${hostname}/${dtbfile}\0" \
"sfload=" \
"sf probe ; " \
"sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \
"usbload=" \
"usb start ; " \
"load usb 0:1 ${loadaddr} ${bootfile}\0" \
"miscargs=panic=1\0" \
"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
"nfsargs=" \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
"mmc_mmc=" \
"if run mmcload mmcargs addargs ; then " \
"bootm ${loadaddr} - ${dtbaddr} ; " \
"fi\0" \
"mmc_nfs=" \
"if run mmcload nfsargs addip addargs ; then " \
"bootm ${loadaddr} - ${dtbaddr} ; " \
"fi\0" \
"sf_mmc=" \
"if run sfload mmcargs addargs ; then " \
"bootm ${loadaddr} - ${dtbaddr} ; " \
"fi\0" \
"sf_swu=" \
"if run sfload ; then " \
"sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; " \
"setenv bootargs root=/dev/ram0 rw ; " \
"run addargs ; " \
"bootm ${loadaddr} ${rdaddr} ; " \
"fi\0" \
"net_mmc=" \
"if run netload mmcargs addargs ; then " \
"bootm ${loadaddr} - ${dtbaddr} ; " \
"fi\0" \
"net_nfs=" \
"if run netload nfsargs addip addargs ; then " \
"bootm ${loadaddr} - ${dtbaddr} ; " \
"fi\0" \
"prebootcmd=" \
"if test \"${envsaved}\" != y ; then ; " \
"setenv envsaved y ; " \
"saveenv ; " \
"fi ; " \
"if test \"${bootmode}\" = normal ; then " \
"setenv bootdelay 0 ; " \
"setenv bootpri mmc_mmc ; " \
"elif test \"${bootmode}\" = devel ; then " \
"setenv bootdelay 3 ; " \
"setenv bootpri net_mmc ; " \
"else " \
"if test \"${bootmode}\" != update ; then " \
"echo Warning: unknown bootmode \"${bootmode}\" ; " \
"fi ; " \
"setenv bootdelay 1 ; " \
"setenv bootpri sf_swu ; " \
"fi\0"
/* The rest of the configuration is shared */
#include <configs/mxs.h>