Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-25 14:10:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS

Browse source 
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define

 #define NAND_MAX_CHIPS          CONFIG_SYS_MAX_NAND_DEVICE

but that's bogus and did not work anyhow.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Wolfgang Grandegger 2009-01-16 18:55:54 +01:00 committed by Scott Wood
parent c70564e6b1
commit 6c869637fe
66 changed files with 12 additions and 77 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
doc/README.nand
View file

@ -172,7 +172,7 @@ More Definitions:
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_DAVINCI_BROKEN_ECC #define CONFIG_SYS_DAVINCI_BROKEN_ECC
Versions of U-Boot <= 1.3.3 and Montavista Linux kernels Versions of U-Boot <= 1.3.3 and Montavista Linux kernels

2
drivers/mtd/nand/nand_base.c
View file

@ -2144,7 +2144,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
{ {
int page, len, status, pages_per_block, ret, chipnr; int page, len, status, pages_per_block, ret, chipnr;
struct nand_chip *chip = mtd->priv; struct nand_chip *chip = mtd->priv;
int rewrite_bbt[NAND_MAX_CHIPS]={0}; int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
unsigned int bbt_masked_page = 0xffffffff; unsigned int bbt_masked_page = 0xffffffff;
MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",

2
drivers/mtd/nand_legacy/nand_legacy.c
View file

@ -457,7 +457,7 @@ static void NanD_ScanChips(struct nand_chip *nand)
{ {
int floor, chip; int floor, chip;
int numchips[NAND_MAX_FLOORS]; int numchips[NAND_MAX_FLOORS];
int maxchips = NAND_MAX_CHIPS; int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
int ret = 1; int ret = 1;
nand->numchips = 0; nand->numchips = 0;

1
include/configs/ASH405.h
View file

@ -150,7 +150,6 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/CATcenter.h
View file

@ -219,7 +219,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */

1
include/configs/CMS700.h
View file

@ -157,7 +157,6 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/DU440.h
View file

@ -411,7 +411,6 @@ int du440_phy_addr(int devnum);
* NAND FLASH * NAND FLASH
*/ */
#define CONFIG_SYS_MAX_NAND_DEVICE 2 #define CONFIG_SYS_MAX_NAND_DEVICE 2
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS} CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}

1
include/configs/G2000.h
View file

@ -205,7 +205,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */

1
include/configs/HH405.h
View file

@ -209,7 +209,6 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/HUB405.h
View file

@ -149,7 +149,6 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/IDS8247.h
View file

@ -275,7 +275,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_DISABLE_CE(nand) do \ #define NAND_DISABLE_CE(nand) do \
{ \ { \

1
include/configs/M5329EVB.h
View file

@ -215,7 +215,6 @@
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_MAX_CHIPS 1
# define NAND_ALLOW_ERASE_ALL 1 # define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0" # define CONFIG_JFFS2_DEV "nand0"

1
include/configs/M5373EVB.h
View file

@ -215,7 +215,6 @@
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_MAX_CHIPS 1
# define NAND_ALLOW_ERASE_ALL 1 # define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0" # define CONFIG_JFFS2_DEV "nand0"

1
include/configs/MPC8313ERDB.h
View file

@ -232,7 +232,6 @@
#endif #endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1

1
include/configs/MPC8315ERDB.h
View file

@ -223,7 +223,6 @@
*/ */
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1

1
include/configs/MPC8360ERDK.h
View file

@ -211,7 +211,6 @@
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_UPM 1 #define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE

1
include/configs/MPC837XEMDS.h
View file

@ -271,7 +271,6 @@
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */

1
include/configs/MPC8536DS.h
View file

@ -248,7 +248,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
CONFIG_SYS_NAND_BASE + 0x80000, \ CONFIG_SYS_NAND_BASE + 0x80000, \
CONFIG_SYS_NAND_BASE + 0xC0000} CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4 #define CONFIG_SYS_MAX_NAND_DEVICE 4
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1

1
include/configs/MPC8572DS.h
View file

@ -267,7 +267,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0x80000,\
CONFIG_SYS_NAND_BASE + 0xC0000} CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4 #define CONFIG_SYS_MAX_NAND_DEVICE 4
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1

1
include/configs/NC650.h
View file

@ -250,7 +250,6 @@
* NAND flash support * NAND flash support
*/ */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9 * SYPCR - System Protection Control 11-9

1
include/configs/NETPHONE.h
View file

@ -514,7 +514,6 @@
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \ #define NAND_DISABLE_CE(nand) \

1
include/configs/NETTA.h
View file

@ -633,7 +633,6 @@
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
#define NAND_DISABLE_CE(nand) \ #define NAND_DISABLE_CE(nand) \

1
include/configs/NETTA2.h
View file

@ -515,7 +515,6 @@
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \ #define NAND_DISABLE_CE(nand) \

1
include/configs/NETVIA.h
View file

@ -411,7 +411,6 @@
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_DISABLE_CE(nand) \ #define NAND_DISABLE_CE(nand) \
do { \ do { \

1
include/configs/PLU405.h
View file

@ -173,7 +173,6 @@
* NAND-FLASH stuff * NAND-FLASH stuff
*/ */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/PMC440.h
View file

@ -505,7 +505,6 @@
* NAND FLASH * NAND FLASH
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_SYS_NAND_QUIET_TEST 1

2
include/configs/PPChameleonEVB.h
View file

@ -224,8 +224,6 @@
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25
#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */

1
include/configs/SXNI855T.h
View file

@ -206,7 +206,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* DFBUSY is available on Port C, bit 12; 0 if busy */ /* DFBUSY is available on Port C, bit 12; 0 if busy */
#define NAND_WAIT_READY(nand) \ #define NAND_WAIT_READY(nand) \

1
include/configs/TQM8272.h
View file

@ -424,7 +424,6 @@
#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
CONFIG_SYS_NAND1_BASE, \ CONFIG_SYS_NAND1_BASE, \

1
include/configs/TQM85xx.h
View file

@ -363,7 +363,6 @@
#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#if (CONFIG_SYS_MAX_NAND_DEVICE == 1) #if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }

1
include/configs/VCMA9.h
View file

@ -264,7 +264,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB() #define NAND_WAIT_READY(nand) NF_WaitRB()

1
include/configs/VOH405.h
View file

@ -159,7 +159,6 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/WUH405.h
View file

@ -147,7 +147,6 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25 #define NAND_BIG_DELAY_US 25

1
include/configs/acadia.h
View file

@ -262,7 +262,6 @@
* NAND FLASH * NAND FLASH
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */

1
include/configs/afeb9260.h
View file

@ -97,7 +97,6 @@
#define DATAFLASH_TCHS (0x1 << 24) #define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */ /* NAND flash */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1

1
include/configs/alpr.h
View file

@ -335,7 +335,6 @@
* NAND-FLASH stuff * NAND-FLASH stuff
*-----------------------------------------------------------------------*/ *-----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 4 #define CONFIG_SYS_MAX_NAND_DEVICE 4
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ #define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }

1
include/configs/at91cap9adk.h
View file

@ -118,7 +118,6 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_BANKS 1
/* NAND flash */ /* NAND flash */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1

1
include/configs/at91rm9200dk.h
View file

@ -129,7 +129,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */

1
include/configs/at91sam9260ek.h
View file

@ -100,7 +100,6 @@
#define DATAFLASH_TCHS (0x1 << 24) #define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */ /* NAND flash */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1

1
include/configs/at91sam9261ek.h
View file

@ -111,7 +111,6 @@
#define DATAFLASH_TCHS (0x1 << 24) #define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */ /* NAND flash */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1

1
include/configs/at91sam9263ek.h
View file

@ -123,7 +123,6 @@
#endif #endif
/* NAND flash */ /* NAND flash */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1

1
include/configs/at91sam9rlek.h
View file

@ -104,7 +104,6 @@
#define CONFIG_SYS_NO_FLASH 1 #define CONFIG_SYS_NO_FLASH 1
/* NAND flash */ /* NAND flash */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_DBW_8 1

1
include/configs/bamboo.h
View file

@ -197,7 +197,6 @@
* NAND FLASH * NAND FLASH
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 2 #define CONFIG_SYS_MAX_NAND_DEVICE 2
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */

1
include/configs/bf537-stamp.h
View file

@ -278,7 +278,6 @@
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define BFIN_NAND_READY PF3 #define BFIN_NAND_READY PF3
#define NAND_WAIT_READY(nand) \ #define NAND_WAIT_READY(nand) \

1
include/configs/canyonlands.h
View file

@ -234,7 +234,6 @@
* NAND-FLASH related * NAND-FLASH related
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */

1
include/configs/csb637.h
View file

@ -131,7 +131,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */

1
include/configs/davinci_dvevm.h
View file

@ -127,7 +127,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define DEF_BOOTM "" #define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR) #elif defined(CONFIG_SYS_USE_NOR)

1
include/configs/davinci_schmoogie.h
View file

@ -89,7 +89,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/*=====================*/ /*=====================*/
/* Board related stuff */ /* Board related stuff */

1
include/configs/davinci_sffsdr.h
View file

@ -85,7 +85,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/* I2C switch definitions for PCA9543 chip */ /* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 #define CONFIG_SYS_I2C_PCA9543_ADDR 0x70

1
include/configs/davinci_sonata.h
View file

@ -122,7 +122,6 @@
#define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define DEF_BOOTM "" #define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR) #elif defined(CONFIG_SYS_USE_NOR)

1
include/configs/delta.h
View file

@ -258,7 +258,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1 #define CONFIG_SYS_NO_FLASH 1

1
include/configs/kilauea.h
View file

@ -214,7 +214,6 @@
* NAND FLASH * NAND FLASH
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */

1
include/configs/netstar.h
View file

@ -120,7 +120,6 @@
* NAND flash * NAND flash
*/ */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL 1 #define NAND_ALLOW_ERASE_ALL 1

1
include/configs/omap2420h4.h
View file

@ -163,7 +163,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) #define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) #define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)

1
include/configs/pdnb3.h
View file

@ -264,7 +264,6 @@
* NAND-FLASH stuff * NAND-FLASH stuff
*/ */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
#endif #endif

1
include/configs/quad100hd.h
View file

@ -224,7 +224,6 @@
#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */ #define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif #endif

1
include/configs/sbc2410x.h
View file

@ -209,7 +209,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB() #define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)

1
include/configs/sc3.h
View file

@ -424,7 +424,6 @@ extern unsigned long offsetOfEnvironment;
* NAND-FLASH stuff * NAND-FLASH stuff
*/ */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x77D00000 #define CONFIG_SYS_NAND_BASE 0x77D00000

1
include/configs/sequoia.h
View file

@ -373,7 +373,6 @@
* NAND FLASH * NAND FLASH
*/ */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */

1
include/configs/smdk6400.h
View file

@ -227,7 +227,6 @@
/* NAND configuration */ /* NAND configuration */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x70200010 #define CONFIG_SYS_NAND_BASE 0x70200010
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_S3C_NAND_HWECC #define CONFIG_SYS_S3C_NAND_HWECC
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */

1
include/configs/socrates.h
View file

@ -186,7 +186,6 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_CMD_NAND #define CONFIG_CMD_NAND
/* LIME GDC */ /* LIME GDC */

1
include/configs/stxxtc.h
View file

@ -464,7 +464,6 @@
#define ADDR_COLUMN_PAGE 3 #define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
#define NAND_DISABLE_CE(nand) \ #define NAND_DISABLE_CE(nand) \

1
include/configs/zylonite.h
View file

@ -227,7 +227,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1 #define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1 #define CONFIG_SYS_NO_FLASH 1

8
include/linux/mtd/bbm.h
View file

@ -18,8 +18,8 @@
#define __LINUX_MTD_BBM_H #define __LINUX_MTD_BBM_H
/* The maximum number of NAND chips in an array */ /* The maximum number of NAND chips in an array */
#ifndef NAND_MAX_CHIPS #ifndef CONFIG_SYS_NAND_MAX_CHIPS
#define NAND_MAX_CHIPS 8 #define CONFIG_SYS_NAND_MAX_CHIPS 1
#endif #endif
/** /**
@ -48,10 +48,10 @@
*/ */
struct nand_bbt_descr { struct nand_bbt_descr {
int options; int options;
int pages[NAND_MAX_CHIPS]; int pages[CONFIG_SYS_NAND_MAX_CHIPS];
int offs; int offs;
int veroffs; int veroffs;
uint8_t version[NAND_MAX_CHIPS]; uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
int len; int len;
int maxblocks; int maxblocks;
int reserved_block_code; int reserved_block_code;

9
include/linux/mtd/nand.h
View file

@ -46,11 +46,6 @@ extern void nand_release (struct mtd_info *mtd);
/* Internal helper for board drivers which need to override command function */ /* Internal helper for board drivers which need to override command function */
extern void nand_wait_ready(struct mtd_info *mtd); extern void nand_wait_ready(struct mtd_info *mtd);
/* The maximum number of NAND chips in an array */
#ifndef NAND_MAX_CHIPS
#define NAND_MAX_CHIPS 8
#endif
/* This constant declares the max. oobsize / page, which /* This constant declares the max. oobsize / page, which
* is supported now. If you add a chip with bigger oobsize/page * is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly. * adjust this accordingly.
@ -477,10 +472,6 @@ struct nand_manufacturers {
extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[]; extern struct nand_manufacturers nand_manuf_ids[];
#ifndef NAND_MAX_CHIPS
#define NAND_MAX_CHIPS 8
#endif
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
extern int nand_default_bbt(struct mtd_info *mtd); extern int nand_default_bbt(struct mtd_info *mtd);

5
include/linux/mtd/nand_legacy.h
View file

@ -40,6 +40,11 @@
#error This module is for the legacy NAND support #error This module is for the legacy NAND support
#endif #endif
/* The maximum number of NAND chips in an array */
#ifndef CONFIG_SYS_NAND_MAX_CHIPS
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#endif
/* /*
* Standard NAND flash commands * Standard NAND flash commands
*/ */