mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
NAND: remove NAND_MAX_CHIPS definitions
This change follows the change by Wolfgang Grandegger (commit 6c869637fe
),
which allows to remove useless NAND_MAX_CHIPS definitions in board config
files.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
d3022c5f5c
commit
6bbb3e93a5
24 changed files with 2 additions and 31 deletions
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@ -273,11 +273,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#endif
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#endif
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#endif
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
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@ -144,10 +144,9 @@
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#endif
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#endif
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#define CONFIG_SYS_FPGA_BASE 0xFF000000
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#define CONFIG_SYS_FPGA_BASE 0xFF000000
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
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#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
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@ -237,7 +237,6 @@
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#define CONFIG_NAND_S3C2410
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#define CONFIG_NAND_S3C2410
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#define CONFIG_SYS_S3C2410_NAND_HWECC
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#define CONFIG_SYS_S3C2410_NAND_HWECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0x4E000000
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#define CONFIG_SYS_NAND_BASE 0x4E000000
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#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
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#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
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#define CONFIG_S3C24XX_TACLS 1
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#define CONFIG_S3C24XX_TACLS 1
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@ -247,13 +247,9 @@
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*/
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*/
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#define CONFIG_CMD_NAND /* enable NAND support */
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#define CONFIG_CMD_NAND /* enable NAND support */
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#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
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#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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/*
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/*
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* Configuration parameters for MPC5121 NAND driver
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* Configuration parameters for MPC5121 NAND driver
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@ -70,7 +70,6 @@
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND
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#endif
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#endif
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@ -69,7 +69,6 @@
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#endif
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#endif
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@ -69,7 +69,6 @@
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#endif
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#endif
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@ -131,7 +131,6 @@
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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/*
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/*
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@ -68,7 +68,6 @@
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#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
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#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND
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#endif
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#endif
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@ -295,7 +295,6 @@
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/* NAND flash */
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/* NAND flash */
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#define CONFIG_NAND_ATMEL
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#define CONFIG_NAND_ATMEL
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_DBW_8 1
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@ -115,7 +115,6 @@
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#define CONFIG_SYS_CLE_MASK 0x10
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#define CONFIG_SYS_CLE_MASK 0x10
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#define CONFIG_SYS_ALE_MASK 0x8
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#define CONFIG_SYS_ALE_MASK 0x8
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_MAX_CHIPS 1
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#endif
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#endif
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#ifdef CONFIG_USE_NOR
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#ifdef CONFIG_USE_NOR
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@ -182,7 +182,6 @@
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#define CONFIG_SYS_ALE_MASK 0x8
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#define CONFIG_SYS_ALE_MASK 0x8
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#undef CONFIG_SYS_NAND_HW_ECC
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#undef CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_MAX_CHIPS 1
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#endif
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#endif
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/*
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/*
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@ -197,7 +197,6 @@
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#endif
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#endif
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@ -114,7 +114,6 @@
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/* Max number of NAND devices */
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/* Max number of NAND devices */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, }
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#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, }
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#define NAND_MAX_CHIPS 1
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/* Block 0--not used by bootcode */
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/* Block 0--not used by bootcode */
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#define CONFIG_ENV_OFFSET 0x0
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#define CONFIG_ENV_OFFSET 0x0
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@ -133,7 +133,6 @@
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* NAND Flash configuration
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* NAND Flash configuration
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*/
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define BOOTFLASH_START 0x0
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#define BOOTFLASH_START 0x0
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@ -154,7 +154,6 @@
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x60000000
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#define CONFIG_SYS_NAND_BASE 0x60000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define NAND_MAX_CHIPS 8
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/* Environment is in NAND */
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/* Environment is in NAND */
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_IS_IN_NAND
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@ -178,9 +178,7 @@
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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/*
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/*
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* Configuration parameters for MPC5121 NAND driver
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* Configuration parameters for MPC5121 NAND driver
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@ -242,7 +242,6 @@
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 2
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#define CONFIG_SYS_MAX_NAND_DEVICE 2
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
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#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
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/*
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/*
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@ -132,7 +132,6 @@
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*/
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*/
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#ifdef CONFIG_CMD_NAND
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#endif
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#endif
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@ -225,9 +225,7 @@
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#define CONFIG_CMD_NAND /* enable NAND support */
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#define CONFIG_CMD_NAND /* enable NAND support */
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
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#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
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/*
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/*
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@ -233,7 +233,6 @@
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/* NAND flash */
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/* NAND flash */
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#define CONFIG_NAND_ATMEL
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#define CONFIG_NAND_ATMEL
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_DBW_8 1
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@ -117,7 +117,6 @@
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#define CONFIG_SYS_NAND_OOBSIZE 128
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#define CONFIG_SYS_NAND_OOBSIZE 128
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
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#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
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#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
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#define CONFIG_NAND_S3C2410
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#define CONFIG_NAND_S3C2410
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#define CONFIG_SYS_S3C2410_NAND_HWECC
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#define CONFIG_SYS_S3C2410_NAND_HWECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0x4E000000
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#define CONFIG_SYS_NAND_BASE 0x4E000000
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#endif
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#endif
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_DEVICE
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#define CONFIG_JFFS2_NAND
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#define CONFIG_JFFS2_NAND
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#define NAND_MAX_CHIPS 1
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#define CONFIG_ENV_OFFSET 0x180000
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#define CONFIG_ENV_OFFSET 0x180000
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/*
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/*
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