mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
Merge git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Tom Rini
commit
6b29a395b6
306 changed files with 1071 additions and 1104 deletions
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@ -10,25 +10,37 @@ choice
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|||
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config TARGET_SBC8548
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bool "Support sbc8548"
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select ARCH_MPC8548
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||||
config TARGET_SOCRATES
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||||
bool "Support socrates"
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||||
select ARCH_MPC8544
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|
||||
config TARGET_B4420QDS
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bool "Support B4420QDS"
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select ARCH_B4420
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select SUPPORT_SPL
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||||
select PHYS_64BIT
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config TARGET_B4860QDS
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bool "Support B4860QDS"
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select ARCH_B4860
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_BSC9131RDB
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bool "Support BSC9131RDB"
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select ARCH_BSC9131
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select SUPPORT_SPL
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config TARGET_BSC9132QDS
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bool "Support BSC9132QDS"
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select ARCH_BSC9132
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select SUPPORT_SPL
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config TARGET_C29XPCIE
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bool "Support C29XPCIE"
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select ARCH_C29X
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select SUPPORT_SPL
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select SUPPORT_TPL
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select PHYS_64BIT
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@ -36,135 +48,266 @@ config TARGET_C29XPCIE
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config TARGET_P3041DS
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bool "Support P3041DS"
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select PHYS_64BIT
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select ARCH_P3041
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config TARGET_P4080DS
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bool "Support P4080DS"
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select PHYS_64BIT
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select ARCH_P4080
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config TARGET_P5020DS
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bool "Support P5020DS"
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select PHYS_64BIT
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select ARCH_P5020
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config TARGET_P5040DS
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bool "Support P5040DS"
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select PHYS_64BIT
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select ARCH_P5040
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config TARGET_MPC8536DS
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bool "Support MPC8536DS"
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select ARCH_MPC8536
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config TARGET_MPC8540ADS
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bool "Support MPC8540ADS"
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select ARCH_MPC8540
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config TARGET_MPC8541CDS
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bool "Support MPC8541CDS"
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select ARCH_MPC8541
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config TARGET_MPC8544DS
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bool "Support MPC8544DS"
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select ARCH_MPC8544
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config TARGET_MPC8548CDS
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bool "Support MPC8548CDS"
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select ARCH_MPC8548
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config TARGET_MPC8555CDS
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bool "Support MPC8555CDS"
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select ARCH_MPC8555
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config TARGET_MPC8560ADS
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bool "Support MPC8560ADS"
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select ARCH_MPC8560
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config TARGET_MPC8568MDS
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bool "Support MPC8568MDS"
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select ARCH_MPC8568
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config TARGET_MPC8569MDS
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bool "Support MPC8569MDS"
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select ARCH_MPC8569
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config TARGET_MPC8572DS
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bool "Support MPC8572DS"
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select ARCH_MPC8572
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config TARGET_P1010RDB
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bool "Support P1010RDB"
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config TARGET_P1010RDB_PA
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bool "Support P1010RDB_PA"
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select ARCH_P1010
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select SUPPORT_SPL
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select SUPPORT_TPL
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config TARGET_P1010RDB_PB
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bool "Support P1010RDB_PB"
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select ARCH_P1010
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select SUPPORT_SPL
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select SUPPORT_TPL
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config TARGET_P1022DS
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bool "Support P1022DS"
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select ARCH_P1022
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select SUPPORT_SPL
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select SUPPORT_TPL
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config TARGET_P1023RDB
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bool "Support P1023RDB"
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select ARCH_P1023
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config TARGET_P1_P2_RDB_PC
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bool "Support p1_p2_rdb_pc"
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config TARGET_P1020MBG
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bool "Support P1020MBG-PC"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1020
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config TARGET_P1020RDB_PC
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bool "Support P1020RDB-PC"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1020
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config TARGET_P1020RDB_PD
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bool "Support P1020RDB-PD"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1020
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config TARGET_P1020UTM
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bool "Support P1020UTM"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1020
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config TARGET_P1021RDB
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bool "Support P1021RDB"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1021
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config TARGET_P1024RDB
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bool "Support P1024RDB"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1024
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config TARGET_P1025RDB
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bool "Support P1025RDB"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P1025
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config TARGET_P2020RDB
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bool "Support P2020RDB-PC"
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select SUPPORT_SPL
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select SUPPORT_TPL
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select ARCH_P2020
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config TARGET_P1_TWR
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bool "Support p1_twr"
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select ARCH_P1025
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config TARGET_P2041RDB
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bool "Support P2041RDB"
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select ARCH_P2041
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select PHYS_64BIT
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config TARGET_QEMU_PPCE500
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bool "Support qemu-ppce500"
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select ARCH_QEMU_E500
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select PHYS_64BIT
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config TARGET_T102XQDS
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bool "Support T102xQDS"
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config TARGET_T1024QDS
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bool "Support T1024QDS"
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select ARCH_T1024
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T102XRDB
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bool "Support T102xRDB"
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config TARGET_T1023RDB
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bool "Support T1023RDB"
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select ARCH_T1023
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T1024RDB
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bool "Support T1024RDB"
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select ARCH_T1024
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T1040QDS
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bool "Support T1040QDS"
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select ARCH_T1040
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select PHYS_64BIT
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config TARGET_T104XRDB
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bool "Support T104xRDB"
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config TARGET_T1040RDB
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bool "Support T1040RDB"
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select ARCH_T1040
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T208XQDS
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bool "Support T208xQDS"
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config TARGET_T1040D4RDB
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bool "Support T1040D4RDB"
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select ARCH_T1040
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T208XRDB
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bool "Support T208xRDB"
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config TARGET_T1042RDB
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bool "Support T1042RDB"
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select ARCH_T1042
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T1042D4RDB
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bool "Support T1042D4RDB"
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select ARCH_T1042
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T1042RDB_PI
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bool "Support T1042RDB_PI"
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select ARCH_T1042
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T2080QDS
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bool "Support T2080QDS"
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select ARCH_T2080
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T2080RDB
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bool "Support T2080RDB"
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select ARCH_T2080
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T2081QDS
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bool "Support T2081QDS"
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select ARCH_T2081
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T4160QDS
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bool "Support T4160QDS"
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select ARCH_T4160
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T4160RDB
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bool "Support T4160RDB"
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select ARCH_T4160
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T4240QDS
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bool "Support T4240QDS"
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select ARCH_T4240
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T4240RDB
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bool "Support T4240RDB"
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select ARCH_T4240
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_CONTROLCENTERD
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bool "Support controlcenterd"
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select ARCH_P1022
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config TARGET_KMP204X
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bool "Support kmp204x"
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select ARCH_P2041
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select PHYS_64BIT
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config TARGET_XPEDITE520X
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bool "Support xpedite520x"
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select ARCH_MPC8548
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config TARGET_XPEDITE537X
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bool "Support xpedite537x"
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select ARCH_MPC8572
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config TARGET_XPEDITE550X
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bool "Support xpedite550x"
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select ARCH_P2020
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config TARGET_UCP1020
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bool "Support uCP1020"
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select ARCH_P1020
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config TARGET_CYRUS
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bool "Support Varisys Cyrus"
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@ -172,6 +315,156 @@ config TARGET_CYRUS
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endchoice
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config ARCH_B4420
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bool
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config ARCH_B4860
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bool
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config ARCH_BSC9131
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bool
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config ARCH_BSC9132
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bool
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config ARCH_C29X
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bool
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|
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config ARCH_MPC8536
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bool
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||||
|
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config ARCH_MPC8540
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||||
bool
|
||||
|
||||
config ARCH_MPC8541
|
||||
bool
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||||
|
||||
config ARCH_MPC8544
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||||
bool
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||||
|
||||
config ARCH_MPC8548
|
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bool
|
||||
|
||||
config ARCH_MPC8555
|
||||
bool
|
||||
|
||||
config ARCH_MPC8560
|
||||
bool
|
||||
|
||||
config ARCH_MPC8568
|
||||
bool
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||||
|
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config ARCH_MPC8569
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bool
|
||||
|
||||
config ARCH_MPC8572
|
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bool
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||||
|
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config ARCH_P1010
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bool
|
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|
||||
config ARCH_P1011
|
||||
bool
|
||||
|
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config ARCH_P1020
|
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bool
|
||||
|
||||
config ARCH_P1021
|
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bool
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||||
|
||||
config ARCH_P1022
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bool
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||||
|
||||
config ARCH_P1023
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bool
|
||||
|
||||
config ARCH_P1024
|
||||
bool
|
||||
|
||||
config ARCH_P1025
|
||||
bool
|
||||
|
||||
config ARCH_P2020
|
||||
bool
|
||||
|
||||
config ARCH_P2041
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bool
|
||||
|
||||
config ARCH_P3041
|
||||
bool
|
||||
|
||||
config ARCH_P4080
|
||||
bool
|
||||
|
||||
config ARCH_P5020
|
||||
bool
|
||||
|
||||
config ARCH_P5040
|
||||
bool
|
||||
|
||||
config ARCH_QEMU_E500
|
||||
bool
|
||||
|
||||
config ARCH_T1023
|
||||
bool
|
||||
|
||||
config ARCH_T1024
|
||||
bool
|
||||
|
||||
config ARCH_T1040
|
||||
bool
|
||||
|
||||
config ARCH_T1042
|
||||
bool
|
||||
|
||||
config ARCH_T2080
|
||||
bool
|
||||
|
||||
config ARCH_T2081
|
||||
bool
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||||
|
||||
config ARCH_T4160
|
||||
bool
|
||||
|
||||
config ARCH_T4240
|
||||
bool
|
||||
|
||||
config MAX_CPUS
|
||||
int "Maximum number of CPUs permitted for MPC85xx"
|
||||
default 12 if ARCH_T4240
|
||||
default 8 if ARCH_P4080 || \
|
||||
ARCH_T4160
|
||||
default 4 if ARCH_B4860 || \
|
||||
ARCH_P2041 || \
|
||||
ARCH_P3041 || \
|
||||
ARCH_P5040 || \
|
||||
ARCH_T1040 || \
|
||||
ARCH_T1042 || \
|
||||
ARCH_T2080 || \
|
||||
ARCH_T2081
|
||||
default 2 if ARCH_B4420 || \
|
||||
ARCH_BSC9132 || \
|
||||
ARCH_MPC8572 || \
|
||||
ARCH_P1020 || \
|
||||
ARCH_P1021 || \
|
||||
ARCH_P1022 || \
|
||||
ARCH_P1023 || \
|
||||
ARCH_P1024 || \
|
||||
ARCH_P1025 || \
|
||||
ARCH_P2020 || \
|
||||
ARCH_P5020 || \
|
||||
ARCH_T1020 || \
|
||||
ARCH_T1022 || \
|
||||
ARCH_T1023 || \
|
||||
ARCH_T1024
|
||||
default 1
|
||||
help
|
||||
Set this number to the maximum number of possible CPUs in the SoC.
|
||||
SoCs may have multiple clusters with each cluster may have multiple
|
||||
ports. If some ports are reserved but higher ports are used for
|
||||
cores, count the reserved ports. This will allocate enough memory
|
||||
in spin table to properly handle all cores.
|
||||
|
||||
source "board/freescale/b4860qds/Kconfig"
|
||||
source "board/freescale/bsc9131rdb/Kconfig"
|
||||
source "board/freescale/bsc9132qds/Kconfig"
|
||||
|
|
|
|||
|
|
@ -39,24 +39,23 @@ obj-$(CONFIG_PCI) += pci.o
|
|||
obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
|
||||
|
||||
# various SoC specific assignments
|
||||
obj-$(CONFIG_PPC_P2041) += p2041_ids.o
|
||||
obj-$(CONFIG_PPC_P3041) += p3041_ids.o
|
||||
obj-$(CONFIG_PPC_P4080) += p4080_ids.o
|
||||
obj-$(CONFIG_PPC_P5020) += p5020_ids.o
|
||||
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
|
||||
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
|
||||
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
|
||||
obj-$(CONFIG_PPC_T4080) += t4240_ids.o
|
||||
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
|
||||
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040_ids.o
|
||||
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
|
||||
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
|
||||
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
|
||||
obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
|
||||
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
|
||||
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
|
||||
obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
|
||||
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
|
||||
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
|
||||
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
|
||||
obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1023) += t1024_ids.o
|
||||
obj-$(CONFIG_PPC_T1024) += t1024_ids.o
|
||||
obj-$(CONFIG_PPC_T2080) += t2080_ids.o
|
||||
obj-$(CONFIG_PPC_T2081) += t2080_ids.o
|
||||
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
|
||||
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
|
||||
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
|
||||
obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
|
||||
|
||||
|
||||
obj-$(CONFIG_QE) += qe_io.o
|
||||
|
|
@ -65,52 +64,46 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
|
|||
obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
|
||||
|
||||
# SoC specific SERDES support
|
||||
obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
|
||||
obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
|
||||
obj-$(CONFIG_MPC8544) += mpc8544_serdes.o
|
||||
obj-$(CONFIG_MPC8548) += mpc8548_serdes.o
|
||||
obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
|
||||
obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
|
||||
obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
|
||||
obj-$(CONFIG_P1010) += p1010_serdes.o
|
||||
obj-$(CONFIG_P1011) += p1021_serdes.o
|
||||
obj-$(CONFIG_P1012) += p1021_serdes.o
|
||||
obj-$(CONFIG_P1013) += p1022_serdes.o
|
||||
obj-$(CONFIG_P1014) += p1010_serdes.o
|
||||
obj-$(CONFIG_P1017) += p1023_serdes.o
|
||||
obj-$(CONFIG_P1020) += p1021_serdes.o
|
||||
obj-$(CONFIG_P1021) += p1021_serdes.o
|
||||
obj-$(CONFIG_P1022) += p1022_serdes.o
|
||||
obj-$(CONFIG_P1023) += p1023_serdes.o
|
||||
obj-$(CONFIG_P1024) += p1021_serdes.o
|
||||
obj-$(CONFIG_P1025) += p1021_serdes.o
|
||||
obj-$(CONFIG_P2010) += p2020_serdes.o
|
||||
obj-$(CONFIG_P2020) += p2020_serdes.o
|
||||
obj-$(CONFIG_PPC_P2041) += p2041_serdes.o
|
||||
obj-$(CONFIG_PPC_P3041) += p3041_serdes.o
|
||||
obj-$(CONFIG_PPC_P4080) += p4080_serdes.o
|
||||
obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
|
||||
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
|
||||
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
|
||||
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
|
||||
obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
|
||||
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
|
||||
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
|
||||
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
|
||||
obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
|
||||
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
|
||||
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
|
||||
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
|
||||
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
|
||||
obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
|
||||
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
|
||||
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
|
||||
obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
|
||||
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
|
||||
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
|
||||
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
|
||||
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
|
||||
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1023) += t1024_serdes.o
|
||||
obj-$(CONFIG_PPC_T1024) += t1024_serdes.o
|
||||
obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
|
||||
obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
|
||||
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
|
||||
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
|
||||
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
|
||||
obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
obj-y += cpu_init_early.o
|
||||
obj-y += interrupts.o
|
||||
ifneq ($(CONFIG_QEMU_E500),y)
|
||||
ifneq ($(CONFIG_ARCH_QEMU_E500),y)
|
||||
obj-y += speed.o
|
||||
endif
|
||||
obj-y += tlb.o
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = {
|
|||
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
|
||||
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
|
||||
|
||||
#ifndef CONFIG_PPC_B4420
|
||||
#ifndef CONFIG_ARCH_B4420
|
||||
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
|
||||
|
|
@ -81,7 +81,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = {
|
|||
SET_FMAN_RX_1G_LIODN(1, 3, 91),
|
||||
SET_FMAN_RX_1G_LIODN(1, 4, 92),
|
||||
SET_FMAN_RX_1G_LIODN(1, 5, 93),
|
||||
#ifndef CONFIG_PPC_B4420
|
||||
#ifndef CONFIG_ARCH_B4420
|
||||
SET_FMAN_RX_10G_LIODN(1, 0, 94),
|
||||
SET_FMAN_RX_10G_LIODN(1, 1, 95),
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ struct serdes_config {
|
|||
u8 lanes[SRDS_MAX_LANES];
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PPC_B4860
|
||||
#ifdef CONFIG_ARCH_B4860
|
||||
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{0x01, {AURORA, AURORA, CPRI6, CPRI5,
|
||||
|
|
@ -180,7 +180,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
{0x0D, {NONE, NONE, CPRI6, CPRI5,
|
||||
CPRI4, CPRI3, NONE, NONE} },
|
||||
|
|
|
|||
|
|
@ -26,12 +26,12 @@ static void check_erratum_a4849(uint32_t svr)
|
|||
void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
|
||||
unsigned int i;
|
||||
|
||||
#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
|
||||
#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
|
||||
static const uint8_t offsets[] = {
|
||||
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_P4080
|
||||
#ifdef CONFIG_ARCH_P4080
|
||||
static const uint8_t offsets[] = {
|
||||
0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
|
||||
};
|
||||
|
|
@ -45,11 +45,11 @@ static void check_erratum_a4849(uint32_t svr)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
|
||||
#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
|
||||
x108 = 0x12;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_P4080
|
||||
#ifdef CONFIG_ARCH_P4080
|
||||
/*
|
||||
* For P4080, the erratum document says that the value at offset 0x108
|
||||
* should be 0x12 on rev2, or 0x1c on rev3.
|
||||
|
|
@ -323,7 +323,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
if (IS_SVR_REV(svr, 1, 0))
|
||||
puts("Work-around for Erratum A-008044 enabled\n");
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
|
||||
#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
|
||||
(defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
|
||||
puts("Work-around for Erratum XFI on B4860QDS enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
|
||||
|
|
|
|||
|
|
@ -293,8 +293,8 @@ int checkcpu (void)
|
|||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
/* Everything after the first generation of PQ3 parts has RSTCR */
|
||||
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
|
||||
defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
|
||||
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
|
||||
defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
|
||||
unsigned long val, msr;
|
||||
|
||||
/*
|
||||
|
|
@ -404,7 +404,7 @@ void mpc85xx_reginfo(void)
|
|||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
|
||||
defined(CONFIG_QEMU_E500)
|
||||
defined(CONFIG_ARCH_QEMU_E500)
|
||||
return fsl_ddr_sdram_size();
|
||||
#else
|
||||
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
||||
|
|
|
|||
|
|
@ -442,7 +442,7 @@ ulong cpu_init_f(void)
|
|||
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
struct law_entry law;
|
||||
#endif
|
||||
#ifdef CONFIG_MPC8548
|
||||
#ifdef CONFIG_ARCH_MPC8548
|
||||
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
|
||||
uint svr = get_svr();
|
||||
|
||||
|
|
@ -959,7 +959,7 @@ int cpu_init_r(void)
|
|||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
|
||||
#if defined(CONFIG_PPC_C29X)
|
||||
#if defined(CONFIG_ARCH_C29X)
|
||||
if ((SVR_SOC_VER(svr) == SVR_C292) ||
|
||||
(SVR_SOC_VER(svr) == SVR_C293))
|
||||
sec_init_idx(1);
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ void cpu_init_early_f(void *fdt)
|
|||
|
||||
/* gd area was zeroed during startup */
|
||||
|
||||
#ifdef CONFIG_QEMU_E500
|
||||
#ifdef CONFIG_ARCH_QEMU_E500
|
||||
/*
|
||||
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
|
||||
* so we need to populate it before it accesses it.
|
||||
|
|
|
|||
|
|
@ -490,7 +490,7 @@ static void ft_fixup_qe_snum(void *blob)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_P4080)
|
||||
#if defined(CONFIG_ARCH_P4080)
|
||||
static void fdt_fixup_usb(void *fdt)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
|
@ -511,8 +511,8 @@ static void fdt_fixup_usb(void *fdt)
|
|||
#define fdt_fixup_usb(x)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
|
||||
defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
|
||||
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
|
||||
defined(CONFIG_ARCH_T4160)
|
||||
void fdt_fixup_dma3(void *blob)
|
||||
{
|
||||
/* the 3rd DMA is not functional if SRIO2 is chosen */
|
||||
|
|
@ -520,7 +520,7 @@ void fdt_fixup_dma3(void *blob)
|
|||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
|
||||
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
|
||||
|
|
@ -529,8 +529,7 @@ void fdt_fixup_dma3(void *blob)
|
|||
case 0x29:
|
||||
case 0x2d:
|
||||
case 0x2e:
|
||||
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
|
||||
defined(CONFIG_PPC_T4080)
|
||||
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
|
||||
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
|
||||
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
|
||||
|
|
@ -556,7 +555,7 @@ void fdt_fixup_dma3(void *blob)
|
|||
#define fdt_fixup_dma3(x)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_T1040)
|
||||
#if defined(CONFIG_ARCH_T1040)
|
||||
static void fdt_fixup_l2_switch(void *blob)
|
||||
{
|
||||
uchar l2swaddr[6];
|
||||
|
|
|
|||
|
|
@ -391,7 +391,7 @@ const char *serdes_clock_to_string(u32 clock)
|
|||
case SRDS_PLLCR0_RFCK_SEL_161_13:
|
||||
return "161.1328123";
|
||||
default:
|
||||
#if defined(CONFIG_T4240QDS)
|
||||
#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
|
||||
return "???";
|
||||
#else
|
||||
return "122.88";
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ static const struct {
|
|||
{ 17, 163, FSL_SRDS_BANK_2 },
|
||||
{ 18, 164, FSL_SRDS_BANK_2 },
|
||||
{ 19, 165, FSL_SRDS_BANK_2 },
|
||||
#ifdef CONFIG_PPC_P4080
|
||||
#ifdef CONFIG_ARCH_P4080
|
||||
{ 20, 170, FSL_SRDS_BANK_3 },
|
||||
{ 21, 171, FSL_SRDS_BANK_3 },
|
||||
{ 22, 172, FSL_SRDS_BANK_3 },
|
||||
|
|
@ -491,7 +491,7 @@ void fsl_serdes_init(void)
|
|||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
int cfg;
|
||||
serdes_corenet_t *srds_regs;
|
||||
#ifdef CONFIG_PPC_P5040
|
||||
#ifdef CONFIG_ARCH_P5040
|
||||
serdes_corenet_t *srds2_regs;
|
||||
#endif
|
||||
int lane, bank, idx;
|
||||
|
|
@ -577,7 +577,7 @@ void fsl_serdes_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_P5040
|
||||
#ifdef CONFIG_ARCH_P5040
|
||||
/*
|
||||
* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
|
||||
* protocols, these lanes are routed to SATA. We use serdes_prtcl_map
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
|
|||
|
||||
pci_register_hose(hose);
|
||||
|
||||
#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
|
||||
#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
|
||||
/*
|
||||
* This is a SW workaround for an apparent HW problem
|
||||
* in the PCI controller on the MPC85555/41 CDS boards.
|
||||
|
|
|
|||
|
|
@ -130,9 +130,8 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
* it uses 6.
|
||||
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
|
||||
*/
|
||||
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
|
||||
defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
|
||||
defined(CONFIG_PPC_T2081)
|
||||
#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
|
||||
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
svr = get_svr();
|
||||
switch (SVR_SOC_VER(svr)) {
|
||||
case SVR_T4240:
|
||||
|
|
@ -202,11 +201,11 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
|
||||
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
|
||||
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#define FM1_CLK_SEL 0xe0000000
|
||||
#define FM1_CLK_SHIFT 29
|
||||
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
|
||||
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
|
||||
#define FM1_CLK_SEL 0x00000007
|
||||
#define FM1_CLK_SHIFT 0
|
||||
#else
|
||||
|
|
@ -216,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
#define FM1_CLK_SHIFT 26
|
||||
#endif
|
||||
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
|
||||
#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
|
||||
#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
|
||||
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
|
||||
#else
|
||||
rcw_tmp = in_be32(&gur->rcwsr[7]);
|
||||
|
|
@ -456,7 +455,7 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
#define ESDHC_CLK_SEL 0x00000007
|
||||
#define ESDHC_CLK_SHIFT 0
|
||||
#define ESDHC_CLK_RCWSR 15
|
||||
|
|
@ -480,7 +479,7 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
case 4:
|
||||
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
|
||||
break;
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
case 5:
|
||||
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
|
||||
break;
|
||||
|
|
@ -596,7 +595,7 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
|
||||
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
|
||||
sys_info->freq_qe = sys_info->freq_systembus;
|
||||
#else
|
||||
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
|
||||
|
|
@ -625,8 +624,8 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
* for four times the clock divider values.
|
||||
*/
|
||||
lcrr_div *= 4;
|
||||
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
|
||||
!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
|
||||
#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
|
||||
!defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
|
||||
/*
|
||||
* Yes, the entire PQ38 family use the same
|
||||
* bit-representation for twice the clock divider values.
|
||||
|
|
@ -652,7 +651,7 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
int get_clocks (void)
|
||||
{
|
||||
sys_info_t sys_info;
|
||||
#ifdef CONFIG_MPC8544
|
||||
#ifdef CONFIG_ARCH_MPC8544
|
||||
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
#endif
|
||||
#if defined(CONFIG_CPM2)
|
||||
|
|
@ -681,11 +680,11 @@ int get_clocks (void)
|
|||
* for that SOC. This information is taken from application note
|
||||
* AN2919.
|
||||
*/
|
||||
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
|
||||
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
|
||||
defined(CONFIG_P1022)
|
||||
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
|
||||
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
|
||||
defined(CONFIG_ARCH_P1022)
|
||||
gd->arch.i2c1_clk = sys_info.freq_systembus;
|
||||
#elif defined(CONFIG_MPC8544)
|
||||
#elif defined(CONFIG_ARCH_MPC8544)
|
||||
/*
|
||||
* On the 8544, the I2C clock is the same as the SEC clock. This can be
|
||||
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
|
||||
|
|
@ -707,8 +706,7 @@ int get_clocks (void)
|
|||
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
||||
gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
|
||||
#else
|
||||
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
|
||||
defined(CONFIG_P1014)
|
||||
#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
|
||||
gd->arch.sdhc_clk = gd->bus_clk;
|
||||
#else
|
||||
gd->arch.sdhc_clk = gd->bus_clk / 2;
|
||||
|
|
|
|||
|
|
@ -311,7 +311,7 @@ l2_disabled:
|
|||
#endif
|
||||
mtspr HID0,r0
|
||||
|
||||
#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
|
||||
#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
|
||||
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
|
||||
mfspr r3,PVR
|
||||
andi. r3,r3, 0xff
|
||||
|
|
@ -345,7 +345,7 @@ l2_disabled:
|
|||
mtspr DBCR0,r0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC8569
|
||||
#ifdef CONFIG_ARCH_MPC8569
|
||||
#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
|
||||
#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
|
||||
|
||||
|
|
@ -376,7 +376,7 @@ l2_disabled:
|
|||
tlbivax 0,r4
|
||||
isync
|
||||
|
||||
#endif /* CONFIG_MPC8569 */
|
||||
#endif /* CONFIG_ARCH_MPC8569 */
|
||||
|
||||
/*
|
||||
* Search for the TLB that covers the code we're executing, and shrink it
|
||||
|
|
|
|||
|
|
@ -161,7 +161,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
|
|||
{}
|
||||
};
|
||||
|
||||
#ifndef CONFIG_PPC_T2081
|
||||
#ifndef CONFIG_ARCH_T2081
|
||||
static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
|
|
@ -181,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
|
|||
|
||||
static const struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
#ifndef CONFIG_PPC_T2081
|
||||
#ifndef CONFIG_ARCH_T2081
|
||||
serdes2_cfg_tbl,
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ struct serdes_config {
|
|||
u8 lanes[SRDS_MAX_LANES];
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PPC_T4240
|
||||
#ifdef CONFIG_ARCH_T4240
|
||||
static const struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
|
|
@ -263,7 +263,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
|
|||
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
|
||||
{}
|
||||
};
|
||||
#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
|
||||
#elif defined(CONFIG_ARCH_T4160)
|
||||
static const struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{1, {NONE, NONE, NONE, NONE,
|
||||
|
|
|
|||
|
|
@ -10,18 +10,28 @@ choice
|
|||
|
||||
config TARGET_SBC8641D
|
||||
bool "Support sbc8641d"
|
||||
select ARCH_MPC8641
|
||||
|
||||
config TARGET_MPC8610HPCD
|
||||
bool "Support MPC8610HPCD"
|
||||
select ARCH_MPC8610
|
||||
|
||||
config TARGET_MPC8641HPCN
|
||||
bool "Support MPC8641HPCN"
|
||||
select ARCH_MPC8641
|
||||
|
||||
config TARGET_XPEDITE517X
|
||||
bool "Support xpedite517x"
|
||||
select ARCH_MPC8641
|
||||
|
||||
endchoice
|
||||
|
||||
config ARCH_MPC8610
|
||||
bool
|
||||
|
||||
config ARCH_MPC8641
|
||||
bool
|
||||
|
||||
source "board/freescale/mpc8610hpcd/Kconfig"
|
||||
source "board/freescale/mpc8641hpcn/Kconfig"
|
||||
source "board/sbc8641d/Kconfig"
|
||||
|
|
|
|||
|
|
@ -19,6 +19,6 @@ obj-y += cpu_init.o
|
|||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-y += interrupts.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_MPC8610) += mpc8610_serdes.o
|
||||
obj-$(CONFIG_MPC8641) += mpc8641_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o
|
||||
obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o
|
||||
obj-y += speed.o
|
||||
|
|
|
|||
|
|
@ -90,9 +90,9 @@ checkcpu(void)
|
|||
|
||||
puts("L2: ");
|
||||
if (get_l2cr() & 0x80000000) {
|
||||
#if defined(CONFIG_MPC8610)
|
||||
#if defined(CONFIG_ARCH_MPC8610)
|
||||
puts("256");
|
||||
#elif defined(CONFIG_MPC8641)
|
||||
#elif defined(CONFIG_ARCH_MPC8641)
|
||||
puts("512");
|
||||
#endif
|
||||
puts(" KiB enabled\n");
|
||||
|
|
@ -139,7 +139,7 @@ get_tbclk(void)
|
|||
void
|
||||
watchdog_reset(void)
|
||||
{
|
||||
#if defined(CONFIG_MPC8610)
|
||||
#if defined(CONFIG_ARCH_MPC8610)
|
||||
/*
|
||||
* This actually feed the hard enabled watchdog.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ int get_clocks(void)
|
|||
* for that SOC. This information is taken from application note
|
||||
* AN2919.
|
||||
*/
|
||||
#ifdef CONFIG_MPC8610
|
||||
#ifdef CONFIG_ARCH_MPC8610
|
||||
gd->arch.i2c1_clk = sys_info.freq_systembus;
|
||||
#else
|
||||
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
|
||||
|
|
|
|||
|
|
@ -57,10 +57,6 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_MAX_CPUS
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Provide a default boot page translation virtual address that lines up with
|
||||
* Freescale's default e500 reset page.
|
||||
|
|
|
|||
|
|
@ -35,8 +35,7 @@
|
|||
#define CONFIG_SYS_NUM_TLBCAMS 16
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC8536)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#if defined(CONFIG_ARCH_MPC8536)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
|
|
@ -44,21 +43,18 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_MPC8540)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8540)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8541)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8541)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8544)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8544)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
|
||||
|
|
@ -66,8 +62,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_MPC8548)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8548)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
|
||||
|
|
@ -85,21 +80,18 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
|
||||
|
||||
#elif defined(CONFIG_MPC8555)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8555)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8560)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8560)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8568)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8568)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
|
|
@ -113,8 +105,7 @@
|
|||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
|
||||
#elif defined(CONFIG_MPC8569)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_MPC8569)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define QE_MURAM_SIZE 0x20000UL
|
||||
|
|
@ -129,8 +120,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_MPC8572)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_MPC8572)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
|
|
@ -140,8 +130,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1010)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_P1010)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||
|
|
@ -169,8 +158,7 @@
|
|||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
/* P1011 is single core version of P1020 */
|
||||
#elif defined(CONFIG_P1011)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_P1011)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
|
|
@ -183,75 +171,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P1012 is single core version of P1021 */
|
||||
#elif defined(CONFIG_P1012)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_FSL_PCIE_DISABLE_ASPM
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P1013 is single core version of P1022 */
|
||||
#elif defined(CONFIG_P1013)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_FSL_SATA_ERRATUM_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1014)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
|
||||
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
|
||||
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
|
||||
/* P1017 is single core version of P1023 */
|
||||
#elif defined(CONFIG_P1017)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 2
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1020)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P1020)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
|
|
@ -266,8 +186,7 @@
|
|||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_P1021)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P1021)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
|
|
@ -283,8 +202,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
|
||||
#elif defined(CONFIG_P1022)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P1022)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
|
|
@ -298,8 +216,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
||||
|
||||
#elif defined(CONFIG_P1023)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P1023)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
|
|
@ -317,8 +234,7 @@
|
|||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
||||
|
||||
/* P1024 is lower end variant of P1020 */
|
||||
#elif defined(CONFIG_P1024)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P1024)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_TSECV2
|
||||
|
|
@ -332,8 +248,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P1025 is lower end variant of P1021 */
|
||||
#elif defined(CONFIG_P1025)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P1025)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
|
|
@ -349,21 +264,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P2010 is single core version of P2020 */
|
||||
#elif defined(CONFIG_P2010)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004508
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P2020)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_P2020)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
|
|
@ -380,10 +281,9 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
|
||||
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
|
||||
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
|
|
@ -418,10 +318,9 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
||||
|
||||
#elif defined(CONFIG_PPC_P3041)
|
||||
#elif defined(CONFIG_ARCH_P3041)
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
|
|
@ -458,10 +357,9 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
||||
|
||||
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
|
||||
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MAX_CPUS 8
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
|
|
@ -509,11 +407,10 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A007075
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
||||
|
||||
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
|
||||
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
|
|
@ -545,11 +442,10 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
||||
|
||||
#elif defined(CONFIG_PPC_P5040)
|
||||
#elif defined(CONFIG_ARCH_P5040)
|
||||
#define CONFIG_SYS_PPC64
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
|
|
@ -579,8 +475,7 @@
|
|||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
||||
|
||||
#elif defined(CONFIG_BSC9131)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_BSC9131)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_TSECV2
|
||||
|
|
@ -598,8 +493,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A004477
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
#elif defined(CONFIG_BSC9132)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_BSC9132)
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
|
|
@ -625,16 +519,14 @@
|
|||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
|
||||
defined(CONFIG_PPC_T4080)
|
||||
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
|
||||
#define CONFIG_E6500
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#ifdef CONFIG_PPC_T4240
|
||||
#define CONFIG_MAX_CPUS 12
|
||||
#ifdef CONFIG_ARCH_T4240
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
|
|
@ -648,12 +540,8 @@
|
|||
#define CONFIG_SYS_NUM_FM2_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#if defined(CONFIG_PPC_T4160)
|
||||
#define CONFIG_MAX_CPUS 8
|
||||
#if defined(CONFIG_ARCH_T4160)
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#elif defined(CONFIG_PPC_T4080)
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
|
||||
#endif
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
||||
|
|
@ -691,7 +579,7 @@
|
|||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
|
||||
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
|
||||
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
|
||||
#define CONFIG_E6500
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -733,9 +621,8 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
#ifdef CONFIG_PPC_B4860
|
||||
#ifdef CONFIG_ARCH_B4860
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_MAX_DSP_CPUS 12
|
||||
#define CONFIG_NUM_DSP_CPUS 6
|
||||
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
|
||||
|
|
@ -749,7 +636,6 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#else
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#define CONFIG_MAX_DSP_CPUS 2
|
||||
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
|
||||
|
|
@ -759,7 +645,7 @@
|
|||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
||||
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
|
||||
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define CONFIG_E5500
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -769,11 +655,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 16
|
||||
|
|
@ -810,7 +691,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A008378
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009663
|
||||
|
||||
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
|
||||
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
|
||||
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
||||
#define CONFIG_E5500
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -821,11 +702,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 16
|
||||
|
|
@ -859,7 +735,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A008378
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A009663
|
||||
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#define CONFIG_E6500
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -867,14 +743,13 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 4
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
|
|
@ -882,7 +757,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#elif defined(CONFIG_PPC_T2081)
|
||||
#elif defined(CONFIG_ARCH_T2081)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#endif
|
||||
|
|
@ -914,8 +789,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
|
||||
#elif defined(CONFIG_PPC_C29X)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_C29X)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 12
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||
|
|
@ -930,8 +804,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
|
||||
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
|
||||
|
||||
#elif defined(CONFIG_QEMU_E500)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#elif defined(CONFIG_ARCH_QEMU_E500)
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
|
||||
|
||||
#else
|
||||
|
|
@ -955,7 +828,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
|||
#define CONFIG_SYS_FSL_DDRC_GEN3
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_PPC_C29X)
|
||||
#if !defined(CONFIG_ARCH_C29X)
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -11,12 +11,10 @@
|
|||
|
||||
/* SoC specific defines for Freescale MPC86xx processors */
|
||||
|
||||
#if defined(CONFIG_MPC8610)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#if defined(CONFIG_ARCH_MPC8610)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
|
||||
#elif defined(CONFIG_MPC8641)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#elif defined(CONFIG_ARCH_MPC8641)
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@
|
|||
*/
|
||||
#define CPM_DATAONLY_BASE ((uint)128)
|
||||
#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
|
||||
#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
|
||||
#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
|
||||
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
|
||||
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
|
||||
#else /* MPC8540, MPC8560 */
|
||||
|
|
|
|||
|
|
@ -79,13 +79,13 @@ enum law_trgt_if {
|
|||
enum law_trgt_if {
|
||||
LAW_TRGT_IF_PCI = 0x00,
|
||||
LAW_TRGT_IF_PCI_2 = 0x01,
|
||||
#ifndef CONFIG_MPC8641
|
||||
#ifndef CONFIG_ARCH_MPC8641
|
||||
LAW_TRGT_IF_PCIE_1 = 0x02,
|
||||
#endif
|
||||
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
|
||||
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
|
||||
LAW_TRGT_IF_OCN_DSP = 0x03,
|
||||
#else
|
||||
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
|
||||
#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
|
||||
LAW_TRGT_IF_PCIE_3 = 0x03,
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -95,7 +95,7 @@ enum law_trgt_if {
|
|||
LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
|
||||
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
|
||||
LAW_TRGT_IF_RIO = 0x0c,
|
||||
#if defined(CONFIG_BSC9132)
|
||||
#if defined(CONFIG_ARCH_BSC9132)
|
||||
LAW_TRGT_IF_CLASS_DSP = 0x0d,
|
||||
#else
|
||||
LAW_TRGT_IF_RIO_2 = 0x0d,
|
||||
|
|
@ -117,11 +117,11 @@ enum law_trgt_if {
|
|||
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
|
||||
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
|
||||
|
||||
#ifdef CONFIG_MPC8641
|
||||
#ifdef CONFIG_ARCH_MPC8641
|
||||
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
|
||||
#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
|
||||
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
|
||||
#endif
|
||||
#endif /* CONFIG_FSL_CORENET */
|
||||
|
|
|
|||
|
|
@ -325,9 +325,9 @@ void lbc_sdram_init(void);
|
|||
*/
|
||||
#define LCRR_CLKDIV 0x0000001F
|
||||
#define LCRR_CLKDIV_SHIFT 0
|
||||
#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
|
||||
defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
|
||||
defined(CONFIG_MPC8560)
|
||||
#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
|
||||
defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
|
||||
defined(CONFIG_ARCH_MPC8560)
|
||||
#define LCRR_CLKDIV_2 0x00000002
|
||||
#define LCRR_CLKDIV_4 0x00000004
|
||||
#define LCRR_CLKDIV_8 0x00000008
|
||||
|
|
|
|||
|
|
@ -16,25 +16,30 @@
|
|||
|
||||
#if defined(CONFIG_FSL_CORENET)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
|
||||
#elif defined(CONFIG_BSC9132QDS)
|
||||
#elif defined(CONFIG_TARGET_BSC9132QDS)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
|
||||
#elif defined(CONFIG_C29XPCIE)
|
||||
#elif defined(CONFIG_TARGET_C29XPCIE)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
|
||||
#else
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
|
||||
|
||||
#if defined(CONFIG_B4860QDS) || \
|
||||
defined(CONFIG_T4240QDS) || \
|
||||
#if defined(CONFIG_TARGET_B4860QDS) || \
|
||||
defined(CONFIG_TARGET_B4420QDS) || \
|
||||
defined(CONFIG_TARGET_T4160QDS) || \
|
||||
defined(CONFIG_TARGET_T4240QDS) || \
|
||||
defined(CONFIG_T2080QDS) || \
|
||||
defined(CONFIG_T2080RDB) || \
|
||||
defined(CONFIG_T1040QDS) || \
|
||||
defined(CONFIG_T104xD4QDS) || \
|
||||
defined(CONFIG_T104xRDB) || \
|
||||
defined(CONFIG_T104xD4RDB) || \
|
||||
defined(CONFIG_PPC_T1023) || \
|
||||
defined(CONFIG_PPC_T1024)
|
||||
defined(CONFIG_TARGET_T1040RDB) || \
|
||||
defined(CONFIG_TARGET_T1040D4RDB) || \
|
||||
defined(CONFIG_TARGET_T1042RDB) || \
|
||||
defined(CONFIG_TARGET_T1042D4RDB) || \
|
||||
defined(CONFIG_TARGET_T1042RDB_PI) || \
|
||||
defined(CONFIG_ARCH_T1023) || \
|
||||
defined(CONFIG_ARCH_T1024)
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_CPC_REINIT_F
|
||||
#endif
|
||||
|
|
@ -54,15 +59,15 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_C29XPCIE)
|
||||
#if defined(CONFIG_TARGET_C29XPCIE)
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_P3041) || \
|
||||
defined(CONFIG_PPC_P4080) || \
|
||||
defined(CONFIG_PPC_P5020) || \
|
||||
defined(CONFIG_PPC_P5040) || \
|
||||
defined(CONFIG_PPC_P2041)
|
||||
#if defined(CONFIG_ARCH_P3041) || \
|
||||
defined(CONFIG_ARCH_P4080) || \
|
||||
defined(CONFIG_ARCH_P5020) || \
|
||||
defined(CONFIG_ARCH_P5040) || \
|
||||
defined(CONFIG_ARCH_P2041)
|
||||
#define CONFIG_FSL_TRUST_ARCH_v1
|
||||
#endif
|
||||
|
||||
|
|
@ -134,13 +139,13 @@
|
|||
/* The bootscript header address is different for B4860 because the NOR
|
||||
* mapping is different on B4 due to reduced NOR size.
|
||||
*/
|
||||
#if defined(CONFIG_B4860QDS)
|
||||
#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
|
||||
#elif defined(CONFIG_FSL_CORENET)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
|
||||
#elif defined(CONFIG_BSC9132QDS)
|
||||
#elif defined(CONFIG_TARGET_BSC9132QDS)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
|
||||
#elif defined(CONFIG_C29XPCIE)
|
||||
#elif defined(CONFIG_TARGET_C29XPCIE)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
|
||||
#else
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
|
||||
|
|
|
|||
|
|
@ -124,10 +124,10 @@ typedef struct ccsr_i2c {
|
|||
u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
|
||||
} ccsr_i2c_t;
|
||||
|
||||
#if defined(CONFIG_MPC8540) \
|
||||
|| defined(CONFIG_MPC8541) \
|
||||
|| defined(CONFIG_MPC8548) \
|
||||
|| defined(CONFIG_MPC8555)
|
||||
#if defined(CONFIG_ARCH_MPC8540) || \
|
||||
defined(CONFIG_ARCH_MPC8541) || \
|
||||
defined(CONFIG_ARCH_MPC8548) || \
|
||||
defined(CONFIG_ARCH_MPC8555)
|
||||
/* DUART Registers */
|
||||
typedef struct ccsr_duart {
|
||||
u8 res1[1280];
|
||||
|
|
@ -1759,8 +1759,7 @@ typedef struct ccsr_gur {
|
|||
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
|
||||
defined(CONFIG_PPC_T4080)
|
||||
#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
|
||||
|
|
@ -1770,13 +1769,13 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
|
||||
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
|
||||
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
|
||||
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
|
||||
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
|
||||
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
|
||||
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
||||
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
|
||||
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
|
|
@ -1797,7 +1796,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define PXCKEN_MASK 0x80000000
|
||||
#define PXCK_MASK 0x00FF0000
|
||||
#define PXCK_BITS_START 16
|
||||
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
|
||||
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \
|
||||
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
|
||||
|
|
@ -1812,7 +1811,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define PXCKEN_MASK 0x80000000
|
||||
#define PXCK_MASK 0x00FF0000
|
||||
#define PXCK_BITS_START 16
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
|
|
@ -1848,7 +1847,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
|
||||
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
|
||||
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
|
||||
#ifdef CONFIG_PPC_P4080
|
||||
#ifdef CONFIG_ARCH_P4080
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
|
||||
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
|
||||
|
|
@ -1856,8 +1855,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
|
||||
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_P2041) \
|
||||
|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
|
||||
#if defined(CONFIG_ARCH_P2041) || \
|
||||
defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
|
||||
|
|
@ -1866,7 +1865,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
|
||||
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_P5040)
|
||||
#if defined(CONFIG_ARCH_P5040)
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
|
||||
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
|
||||
|
|
@ -1875,8 +1874,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
|
||||
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
|
||||
defined(CONFIG_PPC_T4080)
|
||||
#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
|
||||
|
|
@ -1885,7 +1883,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
|
||||
|
|
@ -2120,16 +2118,16 @@ typedef struct ccsr_rcpm {
|
|||
#else
|
||||
typedef struct ccsr_gur {
|
||||
u32 porpllsr; /* POR PLL ratio status */
|
||||
#ifdef CONFIG_MPC8536
|
||||
#ifdef CONFIG_ARCH_MPC8536
|
||||
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
|
||||
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
|
||||
#elif defined(CONFIG_PPC_C29X)
|
||||
#elif defined(CONFIG_ARCH_C29X)
|
||||
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
|
||||
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
|
||||
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
|
||||
>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
|
||||
#else
|
||||
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
|
||||
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
|
||||
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
|
||||
#else
|
||||
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
|
||||
|
|
@ -2150,7 +2148,7 @@ typedef struct ccsr_gur {
|
|||
#define PORBMSR_ROMLOC_NOR 0xf
|
||||
u32 porimpscr; /* POR I/O impedance status & control */
|
||||
u32 pordevsr; /* POR I/O device status regsiter */
|
||||
#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
|
||||
#if defined(CONFIG_ARCH_P1023)
|
||||
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
|
||||
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
|
||||
#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
|
||||
|
|
@ -2162,26 +2160,26 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
|
||||
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
|
||||
#define MPC85xx_PORDEVSR_PCI1 0x00800000
|
||||
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
|
||||
#if defined(CONFIG_ARCH_P1022)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
|
||||
#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
|
||||
#elif defined(CONFIG_ARCH_P1023)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
|
||||
#else
|
||||
#if defined(CONFIG_P1010)
|
||||
#if defined(CONFIG_ARCH_P1010)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
|
||||
#elif defined(CONFIG_BSC9132)
|
||||
#elif defined(CONFIG_ARCH_BSC9132)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
|
||||
#elif defined(CONFIG_PPC_C29X)
|
||||
#elif defined(CONFIG_ARCH_C29X)
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
|
||||
#else
|
||||
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
|
||||
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
|
||||
#endif /* if defined(CONFIG_P1010) */
|
||||
#endif /* if defined(CONFIG_ARCH_P1010) */
|
||||
#endif
|
||||
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
|
||||
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
|
||||
|
|
@ -2193,7 +2191,7 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
|
||||
u32 pordbgmsr; /* POR debug mode status */
|
||||
u32 pordevsr2; /* POR I/O device status 2 */
|
||||
#if defined(CONFIG_PPC_C29X)
|
||||
#if defined(CONFIG_ARCH_C29X)
|
||||
#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
|
||||
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
|
||||
#endif
|
||||
|
|
@ -2203,14 +2201,14 @@ typedef struct ccsr_gur {
|
|||
u8 res1[8];
|
||||
u32 gpporcr; /* General-purpose POR configuration */
|
||||
u8 res2[12];
|
||||
#if defined(CONFIG_MPC8536)
|
||||
#if defined(CONFIG_ARCH_MPC8536)
|
||||
u32 gencfgr; /* General Configuration Register */
|
||||
#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
|
||||
#else
|
||||
u32 gpiocr; /* GPIO control */
|
||||
#endif
|
||||
u8 res3[12];
|
||||
#if defined(CONFIG_MPC8569)
|
||||
#if defined(CONFIG_ARCH_MPC8569)
|
||||
u32 plppar1; /* Platform port pin assignment 1 */
|
||||
u32 plppar2; /* Platform port pin assignment 2 */
|
||||
u32 plpdir1; /* Platform port pin direction 1 */
|
||||
|
|
@ -2222,7 +2220,7 @@ typedef struct ccsr_gur {
|
|||
u32 gpindr; /* General-purpose input data */
|
||||
u8 res5[12];
|
||||
u32 pmuxcr; /* Alt. function signal multiplex control */
|
||||
#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
|
||||
#if defined(CONFIG_ARCH_P1010)
|
||||
#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
|
||||
#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
|
||||
#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
|
||||
|
|
@ -2268,7 +2266,7 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
|
||||
#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
|
||||
#endif
|
||||
#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
|
||||
#if defined(CONFIG_ARCH_P1023)
|
||||
#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
|
||||
#else
|
||||
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
|
||||
|
|
@ -2290,13 +2288,13 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PMUXCR_QE11 0x00000010
|
||||
#define MPC85xx_PMUXCR_QE12 0x00000008
|
||||
#endif
|
||||
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
|
||||
#if defined(CONFIG_ARCH_P1022)
|
||||
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
|
||||
#define MPC85xx_PMUXCR_TDM 0x00014800
|
||||
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
|
||||
#define MPC85xx_PMUXCR_SPI 0x00000000
|
||||
#endif
|
||||
#if defined(CONFIG_BSC9131)
|
||||
#if defined(CONFIG_ARCH_BSC9131)
|
||||
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
|
||||
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
|
||||
#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
|
||||
|
|
@ -2340,17 +2338,17 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
|
||||
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
|
||||
#endif
|
||||
#ifdef CONFIG_BSC9132
|
||||
#ifdef CONFIG_ARCH_BSC9132
|
||||
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
|
||||
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_C29X)
|
||||
#if defined(CONFIG_ARCH_C29X)
|
||||
#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
|
||||
#define MPC85xx_PMUXCR_SPI 0x00000000
|
||||
#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
|
||||
#endif
|
||||
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
|
||||
#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
|
||||
#if defined(CONFIG_ARCH_P1010)
|
||||
#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
|
||||
#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
|
||||
#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
|
||||
|
|
@ -2375,12 +2373,12 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
|
||||
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
|
||||
#endif
|
||||
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
|
||||
#if defined(CONFIG_ARCH_P1022)
|
||||
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
|
||||
#define MPC85xx_PMUXCR2_USB 0x00150000
|
||||
#endif
|
||||
#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
|
||||
#if defined(CONFIG_BSC9131)
|
||||
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
|
||||
#if defined(CONFIG_ARCH_BSC9131)
|
||||
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
|
||||
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
|
||||
#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
|
||||
|
|
@ -2425,7 +2423,7 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
|
||||
#endif
|
||||
u32 pmuxcr3;
|
||||
#if defined(CONFIG_BSC9131)
|
||||
#if defined(CONFIG_ARCH_BSC9131)
|
||||
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
|
||||
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
|
||||
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
|
||||
|
|
@ -2441,7 +2439,7 @@ typedef struct ccsr_gur {
|
|||
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
|
||||
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
|
||||
#endif
|
||||
#ifdef CONFIG_BSC9132
|
||||
#ifdef CONFIG_ARCH_BSC9132
|
||||
#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
|
||||
#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
|
||||
#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
|
||||
|
|
@ -2484,11 +2482,11 @@ typedef struct ccsr_gur {
|
|||
u32 svr; /* System version */
|
||||
u8 res10[8];
|
||||
u32 rstcr; /* Reset control */
|
||||
#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
|
||||
#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
|
||||
u8 res11a[76];
|
||||
par_io_t qe_par_io[7];
|
||||
u8 res11b[1600];
|
||||
#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
|
||||
#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
|
||||
u8 res11a[12];
|
||||
u32 iovselsr;
|
||||
u8 res11b[60];
|
||||
|
|
@ -2504,7 +2502,7 @@ typedef struct ccsr_gur {
|
|||
u32 ddrdllcr; /* DDR DLL control */
|
||||
u8 res14[12];
|
||||
u32 lbcdllcr; /* LBC DLL control */
|
||||
#if defined(CONFIG_BSC9131)
|
||||
#if defined(CONFIG_ARCH_BSC9131)
|
||||
u8 res15[12];
|
||||
u32 halt_req_mask;
|
||||
#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
|
||||
|
|
@ -2883,8 +2881,8 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
|
||||
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
|
||||
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
|
||||
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
|
||||
&& !defined(CONFIG_PPC_B4420)
|
||||
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
|
||||
!defined(CONFIG_ARCH_B4420)
|
||||
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
|
||||
|
|
@ -2940,7 +2938,7 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
|
||||
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
|
||||
#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
|
||||
#else
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
|
||||
|
|
@ -2964,7 +2962,7 @@ struct ccsr_pman {
|
|||
#endif
|
||||
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
|
||||
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
|
||||
#if defined(CONFIG_PPC_C29X)
|
||||
#if defined(CONFIG_ARCH_C29X)
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
|
||||
#else
|
||||
|
|
@ -2988,7 +2986,7 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
|
||||
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
|
||||
|
||||
#if defined(CONFIG_BSC9132)
|
||||
#if defined(CONFIG_ARCH_BSC9132)
|
||||
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
|
||||
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
|
||||
(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
|
||||
|
|
|
|||
|
|
@ -1195,7 +1195,7 @@ extern immap_t *immr;
|
|||
|
||||
|
||||
#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
|
||||
#ifdef CONFIG_MPC8610
|
||||
#ifdef CONFIG_ARCH_MPC8610
|
||||
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
|
||||
#else
|
||||
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
|
||||
|
|
|
|||
|
|
@ -1048,7 +1048,7 @@
|
|||
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
|
||||
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
|
||||
|
||||
#ifdef CONFIG_MPC8536
|
||||
#ifdef CONFIG_ARCH_MPC8536
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
|
||||
#else
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_B4860QDS
|
||||
if TARGET_B4860QDS || TARGET_B4420QDS
|
||||
|
||||
config SYS_BOARD
|
||||
default "b4860qds"
|
||||
|
|
|
|||
|
|
@ -8,7 +8,8 @@ ifdef CONFIG_SPL_BUILD
|
|||
obj-y += spl.o
|
||||
else
|
||||
obj-y += b4860qds.o
|
||||
obj-$(CONFIG_B4860QDS) += eth_b4860qds.o
|
||||
obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o
|
||||
obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ int configure_vsc3316_3308(void)
|
|||
}
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
case 0x17:
|
||||
case 0x18:
|
||||
/*
|
||||
|
|
@ -496,7 +496,7 @@ int configure_vsc3316_3308(void)
|
|||
/* Configure VSC3308 crossbar switch */
|
||||
ret = select_i2c_ch_pca(I2C_CH_VSC3308);
|
||||
switch (serdes2_prtcl) {
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
case 0x9d:
|
||||
#endif
|
||||
case 0x9E:
|
||||
|
|
@ -929,7 +929,7 @@ int config_serdes2_refclks(void)
|
|||
* For this SerDes2's Refclk1 need to be set to 100MHz
|
||||
*/
|
||||
switch (serdes2_prtcl) {
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
case 0x9d:
|
||||
#endif
|
||||
case 0x9E:
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
|
|||
{7, 8}, {9, 0}, {5, 14},
|
||||
{4, 15}, {2, 12}, {12, 13} };
|
||||
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
|
||||
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
|
||||
#endif
|
||||
|
|
@ -54,7 +54,7 @@ static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
|
|||
{7, 8}, {1, 9}, {14, 11},
|
||||
{15, 10}, {13, 3}, {12, 12} };
|
||||
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
|
||||
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -213,7 +213,7 @@ int board_eth_init(bd_t *bis)
|
|||
fm_info_set_phy_address(FM1_DTSEC6,
|
||||
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
|
||||
break;
|
||||
#ifdef CONFIG_PPC_B4420
|
||||
#ifdef CONFIG_ARCH_B4420
|
||||
case 0x17:
|
||||
case 0x18:
|
||||
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
|
||||
|
|
|
|||
|
|
@ -45,18 +45,18 @@ endif
|
|||
|
||||
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
|
||||
|
||||
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
|
||||
obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
|
||||
obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
|
||||
obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o
|
||||
obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
|
||||
obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
|
||||
|
||||
obj-$(CONFIG_MPC8536DS) += ics307_clk.o
|
||||
obj-$(CONFIG_MPC8572DS) += ics307_clk.o
|
||||
obj-$(CONFIG_P1022DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
|
||||
obj-$(CONFIG_P2020DS) += ics307_clk.o
|
||||
obj-$(CONFIG_P3041DS) += ics307_clk.o
|
||||
obj-$(CONFIG_P4080DS) += ics307_clk.o
|
||||
obj-$(CONFIG_P5020DS) += ics307_clk.o
|
||||
obj-$(CONFIG_P5040DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o
|
||||
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
|
||||
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
|
||||
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
|
||||
obj-$(CONFIG_ZM7300) += zm7300.o
|
||||
|
|
@ -65,11 +65,11 @@ obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
|
|||
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
|
||||
|
||||
# deal with common files for P-series corenet based devices
|
||||
obj-$(CONFIG_P2041RDB) += p_corenet/
|
||||
obj-$(CONFIG_P3041DS) += p_corenet/
|
||||
obj-$(CONFIG_P4080DS) += p_corenet/
|
||||
obj-$(CONFIG_P5020DS) += p_corenet/
|
||||
obj-$(CONFIG_P5040DS) += p_corenet/
|
||||
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
|
||||
obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
|
||||
obj-$(CONFIG_TARGET_P4080DS) += p_corenet/
|
||||
obj-$(CONFIG_TARGET_P5020DS) += p_corenet/
|
||||
obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
|
||||
|
||||
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#define __PIXIS_H_ 1
|
||||
|
||||
/* PIXIS register set. */
|
||||
#if defined(CONFIG_MPC8536DS)
|
||||
#if defined(CONFIG_TARGET_MPC8536DS)
|
||||
typedef struct pixis {
|
||||
u8 id;
|
||||
u8 ver;
|
||||
|
|
@ -46,7 +46,7 @@ typedef struct pixis {
|
|||
u8 res2[4];
|
||||
} __attribute__ ((packed)) pixis_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8544DS)
|
||||
#elif defined(CONFIG_TARGET_MPC8544DS)
|
||||
typedef struct pixis {
|
||||
u8 id;
|
||||
u8 ver;
|
||||
|
|
@ -73,7 +73,7 @@ typedef struct pixis {
|
|||
u8 res2[34];
|
||||
} __attribute__ ((packed)) pixis_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8572DS)
|
||||
#elif defined(CONFIG_TARGET_MPC8572DS)
|
||||
typedef struct pixis {
|
||||
u8 id;
|
||||
u8 ver;
|
||||
|
|
@ -102,7 +102,7 @@ typedef struct pixis {
|
|||
u8 res4[25];
|
||||
} __attribute__ ((packed)) pixis_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8610HPCD)
|
||||
#elif defined(CONFIG_TARGET_MPC8610HPCD)
|
||||
typedef struct pixis {
|
||||
u8 id;
|
||||
u8 ver; /* also called arch */
|
||||
|
|
@ -132,7 +132,7 @@ typedef struct pixis {
|
|||
u8 res4[33];
|
||||
} __attribute__ ((packed)) pixis_t;
|
||||
|
||||
#elif defined(CONFIG_MPC8641HPCN)
|
||||
#elif defined(CONFIG_TARGET_MPC8641HPCN)
|
||||
typedef struct pixis {
|
||||
u8 id;
|
||||
u8 ver;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ int pib_init(void)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_PQ_MDS_PIB_ATM)
|
||||
#if defined(CONFIG_MPC8569MDS)
|
||||
#if defined(CONFIG_TARGET_MPC8569MDS)
|
||||
val8 = 0;
|
||||
i2c_write(0x20, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x20, 0x7, 1, &val8, 1);
|
||||
|
|
|
|||
|
|
@ -8,11 +8,11 @@
|
|||
|
||||
obj-y += corenet_ds.o
|
||||
obj-y += ddr.o
|
||||
obj-$(CONFIG_P3041DS) += eth_hydra.o
|
||||
obj-$(CONFIG_P4080DS) += eth_p4080.o
|
||||
obj-$(CONFIG_P5020DS) += eth_hydra.o
|
||||
obj-$(CONFIG_P5040DS) += eth_superhydra.o
|
||||
obj-$(CONFIG_P3041DS) += p3041ds_ddr.o
|
||||
obj-$(CONFIG_P4080DS) += p4080ds_ddr.o
|
||||
obj-$(CONFIG_P5020DS) += p5020ds_ddr.o
|
||||
obj-$(CONFIG_P5040DS) += p5040ds_ddr.o
|
||||
obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o
|
||||
obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o
|
||||
obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o
|
||||
obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o
|
||||
obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o
|
||||
obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o
|
||||
obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o
|
||||
obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@ int checkboard (void)
|
|||
{
|
||||
u8 sw;
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
|
||||
defined(CONFIG_P5040DS)
|
||||
#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
|
||||
defined(CONFIG_TARGET_P5040DS)
|
||||
unsigned int i;
|
||||
#endif
|
||||
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
|
||||
|
|
@ -56,15 +56,15 @@ int checkboard (void)
|
|||
* don't match.
|
||||
*/
|
||||
puts("SERDES Reference Clocks: ");
|
||||
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
|
||||
|| defined(CONFIG_P5040DS)
|
||||
#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
|
||||
defined(CONFIG_TARGET_P5040DS)
|
||||
sw = in_8(&PIXIS_SW(5));
|
||||
for (i = 0; i < 3; i++) {
|
||||
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
|
||||
|
||||
printf("Bank%u=%sMhz ", i+1, freq[clock]);
|
||||
}
|
||||
#ifdef CONFIG_P5040DS
|
||||
#ifdef CONFIG_TARGET_P5040DS
|
||||
/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
|
||||
sw = in_8(&PIXIS_SW(9));
|
||||
printf("Bank4=%sMhz ", freq[sw & 3]);
|
||||
|
|
@ -136,8 +136,8 @@ int misc_init_r(void)
|
|||
unsigned int i;
|
||||
u8 sw;
|
||||
|
||||
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
|
||||
|| defined(CONFIG_P5040DS)
|
||||
#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
|
||||
defined(CONFIG_TARGET_P5040DS)
|
||||
sw = in_8(&PIXIS_SW(5));
|
||||
for (i = 0; i < 3; i++) {
|
||||
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_P1010RDB
|
||||
if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB
|
||||
|
||||
config SYS_BOARD
|
||||
default "p1010rdb"
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ static uint sd_ifc_mux;
|
|||
|
||||
struct cpld_data {
|
||||
u8 cpld_ver; /* cpld revision */
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#if defined(CONFIG_TARGET_P1010RDB_PA)
|
||||
u8 pcba_ver; /* pcb revision number */
|
||||
u8 twindie_ddr3;
|
||||
u8 res1[6];
|
||||
|
|
@ -69,7 +69,7 @@ struct cpld_data {
|
|||
u8 por1; /* POR Options */
|
||||
u8 por2; /* POR Options */
|
||||
u8 por3; /* POR Options */
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#elif defined(CONFIG_TARGET_P1010RDB_PB)
|
||||
u8 rom_loc;
|
||||
#endif
|
||||
};
|
||||
|
|
@ -135,7 +135,7 @@ int config_board_mux(int ctrl_type)
|
|||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u8 tmp;
|
||||
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#if defined(CONFIG_TARGET_P1010RDB_PA)
|
||||
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
|
||||
|
||||
switch (ctrl_type) {
|
||||
|
|
@ -171,7 +171,7 @@ int config_board_mux(int ctrl_type)
|
|||
default:
|
||||
break;
|
||||
}
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#elif defined(CONFIG_TARGET_P1010RDB_PB)
|
||||
uint orig_bus = i2c_get_bus_num();
|
||||
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
|
||||
|
||||
|
|
@ -245,7 +245,7 @@ int config_board_mux(int ctrl_type)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_P1010RDB_PB
|
||||
#ifdef CONFIG_TARGET_P1010RDB_PB
|
||||
int i2c_pca9557_read(int type)
|
||||
{
|
||||
u8 val;
|
||||
|
|
@ -275,9 +275,9 @@ int checkboard(void)
|
|||
u8 val;
|
||||
|
||||
cpu = gd->arch.cpu;
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#if defined(CONFIG_TARGET_P1010RDB_PA)
|
||||
printf("Board: %sRDB-PA, ", cpu->name);
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#elif defined(CONFIG_TARGET_P1010RDB_PB)
|
||||
printf("Board: %sRDB-PB, ", cpu->name);
|
||||
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
|
||||
i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
|
||||
|
|
@ -290,10 +290,10 @@ int checkboard(void)
|
|||
config_board_mux(MUX_TYPE_IFC);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_P1010RDB_PA)
|
||||
#if defined(CONFIG_TARGET_P1010RDB_PA)
|
||||
val = (in_8(&cpld_data->pcba_ver) & 0xf);
|
||||
printf("PCB: v%x.0\n", val);
|
||||
#elif defined(CONFIG_P1010RDB_PB)
|
||||
#elif defined(CONFIG_TARGET_P1010RDB_PB)
|
||||
val = in_8(&cpld_data->cpld_ver);
|
||||
printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
|
||||
printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
|
||||
|
|
@ -544,7 +544,7 @@ int misc_init_r(void)
|
|||
else if (hwconfig("ifc"))
|
||||
config_board_mux(MUX_TYPE_IFC);
|
||||
|
||||
#ifdef CONFIG_P1010RDB_PB
|
||||
#ifdef CONFIG_TARGET_P1010RDB_PB
|
||||
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ void board_init_f(ulong bootflag)
|
|||
/* Clock configuration to access CPLD using IFC(GPCM) */
|
||||
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
|
||||
|
||||
#ifdef CONFIG_P1010RDB_PB
|
||||
#ifdef CONFIG_TARGET_P1010RDB_PB
|
||||
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,11 @@
|
|||
if TARGET_P1_P2_RDB_PC
|
||||
if TARGET_P1020MBG || \
|
||||
TARGET_P1020RDB_PC || \
|
||||
TARGET_P1020RDB_PD || \
|
||||
TARGET_P1020UTM || \
|
||||
TARGET_P1021RDB || \
|
||||
TARGET_P1024RDB || \
|
||||
TARGET_P1025RDB || \
|
||||
TARGET_P2020RDB
|
||||
|
||||
config SYS_BOARD
|
||||
default "p1_p2_rdb_pc"
|
||||
|
|
|
|||
|
|
@ -15,8 +15,8 @@
|
|||
|
||||
#ifdef CONFIG_SYS_DDR_RAW_TIMING
|
||||
#if defined(CONFIG_P1020RDB_PROTO) || \
|
||||
defined(CONFIG_P1021RDB) || \
|
||||
defined(CONFIG_P1020UTM)
|
||||
defined(CONFIG_TARGET_P1021RDB) || \
|
||||
defined(CONFIG_TARGET_P1020UTM)
|
||||
/* Micron MT41J256M8_187E */
|
||||
dimm_params_t ddr_raw_timing = {
|
||||
.n_ranks = 1,
|
||||
|
|
@ -47,7 +47,7 @@ dimm_params_t ddr_raw_timing = {
|
|||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 37500,
|
||||
};
|
||||
#elif defined(CONFIG_P2020RDB)
|
||||
#elif defined(CONFIG_TARGET_P2020RDB)
|
||||
/* Micron MT41J128M16_15E */
|
||||
dimm_params_t ddr_raw_timing = {
|
||||
.n_ranks = 1,
|
||||
|
|
@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = {
|
|||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 30000,
|
||||
};
|
||||
#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
|
||||
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
|
||||
/* Micron MT41J512M8_187E */
|
||||
dimm_params_t ddr_raw_timing = {
|
||||
.n_ranks = 2,
|
||||
|
|
@ -109,7 +109,7 @@ dimm_params_t ddr_raw_timing = {
|
|||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 37500,
|
||||
};
|
||||
#elif defined(CONFIG_P1020RDB_PC)
|
||||
#elif defined(CONFIG_TARGET_P1020RDB_PC)
|
||||
/*
|
||||
* Samsung K4B2G0846C-HCF8
|
||||
* The following timing are for "downshift"
|
||||
|
|
@ -146,8 +146,8 @@ dimm_params_t ddr_raw_timing = {
|
|||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 37500,
|
||||
};
|
||||
#elif defined(CONFIG_P1024RDB) || \
|
||||
defined(CONFIG_P1025RDB)
|
||||
#elif defined(CONFIG_TARGET_P1024RDB) || \
|
||||
defined(CONFIG_TARGET_P1025RDB)
|
||||
/*
|
||||
* Samsung K4B2G0846C-HCH9
|
||||
* The following timing are for "downshift"
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
#define GPIO_SLIC_PIN 30
|
||||
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
|
||||
|
||||
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
#define GPIO_DDR_RST_PORT 1
|
||||
#define GPIO_DDR_RST_PIN 8
|
||||
#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
|
||||
#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
|
||||
#define PCA_IOPORT_I2C_ADDR 0x23
|
||||
#define PCA_IOPORT_OUTPUT_CMD 0x2
|
||||
#define PCA_IOPORT_CFG_CMD 0x6
|
||||
|
|
@ -58,14 +58,14 @@
|
|||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
/* GPIO */
|
||||
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
|
||||
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
|
||||
#endif
|
||||
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
|
||||
{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
|
||||
{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
|
||||
|
||||
#ifdef CONFIG_P1025RDB
|
||||
#ifdef CONFIG_TARGET_P1025RDB
|
||||
/* QE_MUX_MDC */
|
||||
{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
|
||||
|
||||
|
|
@ -150,7 +150,7 @@ void board_gpio_init(void)
|
|||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
|
||||
|
||||
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
/* reset DDR3 */
|
||||
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
|
||||
udelay(1000);
|
||||
|
|
@ -379,7 +379,7 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_QE) && \
|
||||
(defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
|
||||
(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
|
||||
static void fdt_board_fixup_qe_pins(void *blob)
|
||||
{
|
||||
unsigned int oldbus;
|
||||
|
|
@ -428,7 +428,7 @@ int ft_board_setup(void *blob, bd_t *bd)
|
|||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
|
||||
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
|
||||
const char *soc_usb_compat = "fsl-usb2-dr";
|
||||
int usb_err, usb1_off, usb2_off;
|
||||
#endif
|
||||
|
|
@ -448,7 +448,7 @@ int ft_board_setup(void *blob, bd_t *bd)
|
|||
#ifdef CONFIG_QE
|
||||
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
|
||||
sizeof("okay"), 0);
|
||||
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
|
||||
#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
|
||||
fdt_board_fixup_qe_pins(blob);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -478,7 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
|
||||
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
|
||||
/* Delete USB2 node as it is muxed with eLBC */
|
||||
usb1_off = fdt_node_offset_by_compatible(blob, -1,
|
||||
soc_usb_compat);
|
||||
|
|
|
|||
|
|
@ -85,13 +85,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 8, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
|
||||
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
|
||||
/* 2G DDR on P1020MBG, map the second 1G */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 9, BOOKE_PAGESZ_1G, 1),
|
||||
#endif /* P1020MBG */
|
||||
#endif /* TARGET_P1020MBG */
|
||||
#endif /* RAMBOOT/SPL */
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_T102XQDS
|
||||
if TARGET_T1024QDS
|
||||
|
||||
config SYS_BOARD
|
||||
default "t102xqds"
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ void board_init_f(ulong bootflag)
|
|||
u32 plat_ratio, sys_clk, ccb_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
|
||||
#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
|
||||
/*
|
||||
* There is T1040 SoC issue where NOR, FPGA are inaccessible during
|
||||
* NAND boot because IFC signals > IFC_AD7 are not enabled.
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ static int board_mux_lane_to_slot(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_T1024
|
||||
#ifdef CONFIG_ARCH_T1024
|
||||
static void board_mux_setup(void)
|
||||
{
|
||||
u8 brdcfg15;
|
||||
|
|
@ -332,7 +332,7 @@ unsigned long get_board_ddr_clk(void)
|
|||
#define NUM_SRDS_PLL 2
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_PPC_T1024
|
||||
#ifdef CONFIG_ARCH_T1024
|
||||
board_mux_setup();
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_T102XRDB
|
||||
if TARGET_T1023RDB || TARGET_T1024RDB
|
||||
|
||||
config SYS_BOARD
|
||||
default "t102xrdb"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
if TARGET_T104XRDB
|
||||
if TARGET_T1040RDB || TARGET_T1040D4RDB || \
|
||||
TARGET_T1042RDB || TARGET_T1042D4RDB || \
|
||||
TARGET_T1042RDB_PI
|
||||
|
||||
config SYS_BOARD
|
||||
default "t104xrdb"
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ static void cpld_dump_regs(void)
|
|||
printf("int_status = 0x%02x\n", CPLD_READ(int_status));
|
||||
printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
|
||||
printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
|
||||
#if defined(CONFIG_T104XD4RDB)
|
||||
#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
|
||||
printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
|
||||
#else
|
||||
printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ struct cpld_data {
|
|||
u8 int_status; /* 0x12 - Interrupt status Register */
|
||||
u8 flash_ctl_status; /* 0x13 - Flash control and status register */
|
||||
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
|
||||
#if defined(CONFIG_T104XD4RDB)
|
||||
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
|
||||
u8 int_mask; /* 0x15 - Interrupt mask Register */
|
||||
#else
|
||||
u8 led_ctl_status; /* 0x15 - LED control and status register */
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ int board_eth_init(bd_t *bis)
|
|||
int idx = i - FM1_DTSEC1;
|
||||
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
|
||||
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
/* T1040RDB & T1040D4RDB only supports SGMII on
|
||||
* DTSEC3
|
||||
|
|
@ -52,7 +52,7 @@ int board_eth_init(bd_t *bis)
|
|||
CONFIG_SYS_SGMII1_PHY_ADDR);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_T1042RDB
|
||||
#ifdef CONFIG_TARGET_T1042RDB
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
|
||||
if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
|
||||
|
|
@ -62,7 +62,7 @@ int board_eth_init(bd_t *bis)
|
|||
CONFIG_SYS_SGMII1_PHY_ADDR);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_T1042D4RDB
|
||||
#ifdef CONFIG_TARGET_T1042D4RDB
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
|
||||
* & DTSEC3
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ int checkboard(void)
|
|||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
u8 sw;
|
||||
|
||||
#ifdef CONFIG_T104XD4RDB
|
||||
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
|
||||
printf("Board: %sD4RDB\n", cpu->name);
|
||||
#else
|
||||
printf("Board: %sRDB\n", cpu->name);
|
||||
|
|
@ -105,7 +105,7 @@ int misc_init_r(void)
|
|||
CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
|
||||
MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
|
||||
|
||||
#if defined(CONFIG_T1040D4RDB)
|
||||
#if defined(CONFIG_TARGET_T1040D4RDB)
|
||||
if (hwconfig("qe-tdm")) {
|
||||
CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
|
||||
MISC_MUX_QE_TDM);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_T208XQDS
|
||||
if TARGET_T2080QDS || TARGET_T2081QDS
|
||||
|
||||
config SYS_BOARD
|
||||
default "t208xqds"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_T208XRDB
|
||||
if TARGET_T2080RDB
|
||||
|
||||
config SYS_BOARD
|
||||
default "t208xrdb"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_T4240QDS
|
||||
if TARGET_T4160QDS || TARGET_T4240QDS
|
||||
|
||||
config SYS_BOARD
|
||||
default "t4qds"
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@
|
|||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
else
|
||||
obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o
|
||||
obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o
|
||||
obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
if TARGET_T4240RDB
|
||||
if TARGET_T4160RDB || TARGET_T4240RDB
|
||||
|
||||
config SYS_BOARD
|
||||
default "t4rdb"
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@
|
|||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
else
|
||||
obj-$(CONFIG_T4240RDB) += t4240rdb.o
|
||||
obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o
|
||||
obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
|
||||
obj-y += cpld.o
|
||||
obj-y += eth.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
#define FIRST_PORT_ADDR 3
|
||||
#define SECOND_PORT_ADDR 7
|
||||
|
||||
#ifdef CONFIG_PPC_P5040
|
||||
#ifdef CONFIG_ARCH_P5040
|
||||
#define FIRST_PORT FM1_DTSEC5
|
||||
#define SECOND_PORT FM2_DTSEC5
|
||||
#else
|
||||
|
|
@ -83,7 +83,7 @@ int board_eth_init(bd_t *bis)
|
|||
fm_disable_port(i);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_P5040
|
||||
#ifdef CONFIG_ARCH_P5040
|
||||
for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
|
||||
if (!IS_VALID_PORT(i))
|
||||
fm_disable_port(i);
|
||||
|
|
|
|||
|
|
@ -6,9 +6,9 @@
|
|||
#
|
||||
|
||||
obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
|
||||
obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
|
||||
obj-$(CONFIG_ARCH_MPC8572) += fsl_8xxx_clk.o
|
||||
obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
|
||||
obj-$(CONFIG_P2020) += fsl_8xxx_clk.o
|
||||
obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
|
||||
obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
|
||||
obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
|
||||
obj-$(CONFIG_NAND_ACTL) += actl_nand.o
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ unsigned long get_board_sys_clk(ulong dummy)
|
|||
if (in_be32(&gur->gpporcr) & 0x10000)
|
||||
return 66666666;
|
||||
else
|
||||
#ifdef CONFIG_P2020
|
||||
#ifdef CONFIG_ARCH_P2020
|
||||
return 100000000;
|
||||
#else
|
||||
return 50000000;
|
||||
|
|
@ -42,7 +42,7 @@ unsigned long get_board_ddr_clk(ulong dummy)
|
|||
if (ddr_ratio == 0x7)
|
||||
return get_board_sys_clk(dummy);
|
||||
|
||||
#ifdef CONFIG_P2020
|
||||
#ifdef CONFIG_ARCH_P2020
|
||||
if (in_be32(&gur->gpporcr) & 0x20000)
|
||||
return 66666666;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ void pci_init_board(void)
|
|||
} else {
|
||||
printf("PCI1: disabled\n");
|
||||
}
|
||||
#elif defined CONFIG_MPC8548
|
||||
#elif defined CONFIG_ARCH_MPC8548
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
/* PCI1 not present on MPC8572 */
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <linux/kconfig.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y
|
|||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_B4860QDS=y
|
||||
CONFIG_TARGET_B4420QDS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_B4860QDS=y
|
||||
CONFIG_TARGET_B4420QDS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -1,11 +1,10 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_B4860QDS=y
|
||||
CONFIG_TARGET_B4420QDS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_133"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,NAND"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="NAND"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SPIFLASH,SECURE_BOOT"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SPIFLASH"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE"
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue