mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
Merge git://www.denx.de/git/u-boot
Conflicts: board/tqm5200/tqm5200.c
This commit is contained in:
Markus Klotzbuecher
commit
6a40ef62c4
915 changed files with 42854 additions and 12091 deletions
41
.gitignore
vendored
Normal file
41
.gitignore
vendored
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
#
|
||||
# NOTE! Don't add files that are generated in specific
|
||||
# subdirectories here. Add them in the ".gitignore" file
|
||||
# in that subdirectory instead.
|
||||
#
|
||||
# Normal rules
|
||||
#
|
||||
|
||||
*.rej
|
||||
*.orig
|
||||
*.a
|
||||
*.o
|
||||
|
||||
#
|
||||
# Top-level generic files
|
||||
#
|
||||
|
||||
/System.map
|
||||
/u-boot
|
||||
/u-boot.map
|
||||
/u-boot.bin
|
||||
/u-boot.srec
|
||||
|
||||
#
|
||||
# Generated files
|
||||
#
|
||||
|
||||
*.depend
|
||||
/LOG
|
||||
/errlog
|
||||
/reloc_off
|
||||
|
||||
# stgit generated dirs
|
||||
patches-*
|
||||
|
||||
# quilt's files
|
||||
patches
|
||||
series
|
||||
|
||||
# cscope files
|
||||
cscope.*
|
||||
16
CREDITS
16
CREDITS
|
|
@ -117,7 +117,7 @@ N: Arun Dharankar
|
|||
E: ADharankar@ATTBI.Com
|
||||
D: threads / scheduler example code
|
||||
|
||||
N: Kári Davíðsson
|
||||
N: K?ri Dav??sson
|
||||
E: kd@flaga.is
|
||||
D: FLAGA DM Support
|
||||
|
||||
|
|
@ -143,7 +143,7 @@ E: info@elste.org
|
|||
D: Port for the ModNET50 Board, NET+50 CPU Port
|
||||
W: http://www.imms.de
|
||||
|
||||
N: Daniel Engström
|
||||
N: Daniel Engstr?m
|
||||
E: daniel@omicron.se
|
||||
D: x86 port, Support for sc520_cdp board
|
||||
|
||||
|
|
@ -303,6 +303,11 @@ D: Support for Nios Stratix Development Kit (DK-1S10)
|
|||
D: Support for SSV ADNP/ESC1 (Nios Cyclone)
|
||||
W: http://www.li-pro.net
|
||||
|
||||
N: Dave Liu
|
||||
E: daveliu@freescale.com
|
||||
D: Support for MPC832x, MPC8360, MPC837x
|
||||
W: www.freescale.com
|
||||
|
||||
N: Raymond Lo
|
||||
E: lo@routefree.com
|
||||
D: Support for DOS partitions
|
||||
|
|
@ -334,7 +339,7 @@ N: Frank Morauf
|
|||
E: frank.morauf@salzbrenner.com
|
||||
D: Support for Embedded Planet RPX Super Board
|
||||
|
||||
N: David Müller
|
||||
N: David M?ller
|
||||
E: d.mueller@elsoft.ch
|
||||
D: Support for Samsung ARM920T SMDK2410 eval board
|
||||
|
||||
|
|
@ -499,3 +504,8 @@ N: Alex Zuepke
|
|||
E: azu@sysgo.de
|
||||
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
|
||||
W: www.elinos.com
|
||||
|
||||
N: Nobuhiro Iwamatsu
|
||||
E: iwamatsu@nigauri.org
|
||||
D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
|
||||
W: http://www.nigauri.org/~iwamatsu/
|
||||
|
|
|
|||
28
MAINTAINERS
28
MAINTAINERS
|
|
@ -146,7 +146,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
|||
CPCI4052 PPC405GP
|
||||
CPCI405AB PPC405GP
|
||||
CPCI405DT PPC405GP
|
||||
CPCI440 PPC440GP
|
||||
CPCIISER4 PPC405GP
|
||||
DASA_SIM IOP480 (PPC401)
|
||||
DP405 PPC405EP
|
||||
|
|
@ -159,6 +158,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
|||
PCI405 PPC405GP
|
||||
PLU405 PPC405EP
|
||||
PMC405 PPC405GP
|
||||
PMC440 PPC440EPx
|
||||
VOH405 PPC405EP
|
||||
VOM405 PPC405EP
|
||||
WUH405 PPC405EP
|
||||
|
|
@ -204,6 +204,10 @@ Murray Jensen <Murray.Jensen@csiro.au>
|
|||
cogent_mpc8260 MPC8260
|
||||
hymod MPC8260
|
||||
|
||||
Larry Johnson <lrj@acm.org>
|
||||
|
||||
korat PPC440EPx
|
||||
|
||||
Brad Kemp <Brad.Kemp@seranoa.com>
|
||||
|
||||
ppmc8260 MPC8260
|
||||
|
|
@ -223,7 +227,9 @@ The LEOX team <team@leox.org>
|
|||
|
||||
Dave Liu <daveliu@freescale.com>
|
||||
|
||||
MPC832XEMDS MPC832x
|
||||
MPC8360EMDS MPC8360
|
||||
MPC837XEMDS MPC837x
|
||||
|
||||
Nye Liu <nyet@zumanetworks.com>
|
||||
|
||||
|
|
@ -303,8 +309,11 @@ Stefan Roese <sr@denx.de>
|
|||
bamboo PPC440EP
|
||||
bunbinga PPC405EP
|
||||
ebony PPC440GP
|
||||
haleakala PPC405EXr
|
||||
katmai PPC440SPe
|
||||
kilauea PPC405EX
|
||||
lwmon5 PPC440EPx
|
||||
makalu PPC405EX
|
||||
ocotea PPC440GX
|
||||
p3p440 PPC440GP
|
||||
pcs440ep PPC440EP
|
||||
|
|
@ -630,7 +639,22 @@ Hayden Fraser <Hayden.Fraser@freescale.com>
|
|||
|
||||
Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
ATSTK1000 AT32AP7000
|
||||
ATSTK1000 AT32AP7xxx
|
||||
ATSTK1002 AT32AP7000
|
||||
ATSTK1003 AT32AP7001
|
||||
ATSTK1004 AT32AP7002
|
||||
|
||||
#########################################################################
|
||||
# SuperH Systems: #
|
||||
# #
|
||||
# Maintainer Name, Email Address #
|
||||
# Board CPU #
|
||||
#########################################################################
|
||||
|
||||
Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
|
||||
|
||||
MS7750SE SH7750
|
||||
MS7722SE SH7722
|
||||
|
||||
#########################################################################
|
||||
# End of MAINTAINERS list #
|
||||
|
|
|
|||
36
MAKEALL
36
MAKEALL
|
|
@ -168,7 +168,6 @@ LIST_4xx=" \
|
|||
CPCI4052 \
|
||||
CPCI405AB \
|
||||
CPCI405DT \
|
||||
CPCI440 \
|
||||
CPCIISER4 \
|
||||
CRAYL1 \
|
||||
csb272 \
|
||||
|
|
@ -180,6 +179,8 @@ LIST_4xx=" \
|
|||
ERIC \
|
||||
EXBITGEN \
|
||||
G2000 \
|
||||
haleakala \
|
||||
haleakala_nand \
|
||||
hcu4 \
|
||||
hcu5 \
|
||||
HH405 \
|
||||
|
|
@ -187,8 +188,12 @@ LIST_4xx=" \
|
|||
JSE \
|
||||
KAREF \
|
||||
katmai \
|
||||
kilauea \
|
||||
kilauea_nand \
|
||||
korat \
|
||||
luan \
|
||||
lwmon5 \
|
||||
makalu \
|
||||
METROBOX \
|
||||
MIP405 \
|
||||
MIP405T \
|
||||
|
|
@ -203,6 +208,7 @@ LIST_4xx=" \
|
|||
PIP405 \
|
||||
PLU405 \
|
||||
PMC405 \
|
||||
PMC440 \
|
||||
PPChameleonEVB \
|
||||
rainier \
|
||||
sbc405 \
|
||||
|
|
@ -307,6 +313,7 @@ LIST_83xx=" \
|
|||
MPC8349ITXGP \
|
||||
MPC8360EMDS \
|
||||
MPC8360EMDS_ATM \
|
||||
MPC837XEMDS \
|
||||
sbc8349 \
|
||||
TQM834x \
|
||||
"
|
||||
|
|
@ -342,6 +349,7 @@ LIST_85xx=" \
|
|||
#########################################################################
|
||||
|
||||
LIST_86xx=" \
|
||||
MPC8610HPCD \
|
||||
MPC8641HPCN \
|
||||
sbc8641d \
|
||||
"
|
||||
|
|
@ -378,6 +386,7 @@ LIST_7xx=" \
|
|||
|
||||
LIST_ppc=" \
|
||||
${LIST_5xx} \
|
||||
${LIST_512x} \
|
||||
${LIST_5xxx} \
|
||||
${LIST_8xx} \
|
||||
${LIST_8220} \
|
||||
|
|
@ -476,6 +485,7 @@ LIST_ARM10=" \
|
|||
LIST_ARM11=" \
|
||||
cp1136 \
|
||||
omap2420h4 \
|
||||
apollon \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -554,6 +564,7 @@ LIST_mips5kc_el=""
|
|||
|
||||
LIST_au1xx0_el=" \
|
||||
dbau1550_el \
|
||||
pb1000 \
|
||||
"
|
||||
|
||||
LIST_mips_el=" \
|
||||
|
|
@ -640,6 +651,8 @@ LIST_coldfire=" \
|
|||
|
||||
LIST_avr32=" \
|
||||
atstk1002 \
|
||||
atstk1003 \
|
||||
atstk1004 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -653,6 +666,23 @@ LIST_blackfin=" \
|
|||
bf561-ezkit \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## SH Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_sh4=" \
|
||||
ms7750se \
|
||||
ms7722se \
|
||||
"
|
||||
|
||||
LIST_sh3=""
|
||||
|
||||
|
||||
LIST_sh=" \
|
||||
${LIST_sh3} \
|
||||
${LIST_sh4} \
|
||||
"
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#----- for now, just run PPC by default -----
|
||||
|
|
@ -687,7 +717,9 @@ do
|
|||
mips|mips_el| \
|
||||
nios|nios2| \
|
||||
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
|
||||
x86|I486|TSEC)
|
||||
x86|I486|TSEC| \
|
||||
sh|sh4|sh3 \
|
||||
)
|
||||
for target in `eval echo '$LIST_'${arg}`
|
||||
do
|
||||
build_target ${target}
|
||||
|
|
|
|||
185
Makefile
185
Makefile
|
|
@ -23,8 +23,8 @@
|
|||
|
||||
VERSION = 1
|
||||
PATCHLEVEL = 3
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
SUBLEVEL = 1
|
||||
EXTRAVERSION =
|
||||
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
|
||||
VERSION_FILE = $(obj)include/version_autogenerated.h
|
||||
|
||||
|
|
@ -152,6 +152,9 @@ endif
|
|||
ifeq ($(ARCH),avr32)
|
||||
CROSS_COMPILE = avr32-linux-
|
||||
endif
|
||||
ifeq ($(ARCH),sh)
|
||||
CROSS_COMPILE = sh4-linux-
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
|
|
@ -205,22 +208,30 @@ LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs
|
|||
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
|
||||
LIBS += net/libnet.a
|
||||
LIBS += disk/libdisk.a
|
||||
LIBS += rtc/librtc.a
|
||||
LIBS += dtt/libdtt.a
|
||||
LIBS += drivers/libdrivers.a
|
||||
LIBS += drivers/bios_emulator/libatibiosemu.a
|
||||
LIBS += drivers/nand/libnand.a
|
||||
LIBS += drivers/nand_legacy/libnand_legacy.a
|
||||
LIBS += drivers/onenand/libonenand.a
|
||||
LIBS += drivers/block/libblock.a
|
||||
LIBS += drivers/hwmon/libhwmon.a
|
||||
LIBS += drivers/i2c/libi2c.a
|
||||
LIBS += drivers/input/libinput.a
|
||||
LIBS += drivers/misc/libmisc.a
|
||||
LIBS += drivers/mtd/libmtd.a
|
||||
LIBS += drivers/mtd/nand/libnand.a
|
||||
LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
|
||||
LIBS += drivers/mtd/onenand/libonenand.a
|
||||
LIBS += drivers/net/libnet.a
|
||||
LIBS += drivers/net/sk98lin/libsk98lin.a
|
||||
LIBS += drivers/pci/libpci.a
|
||||
LIBS += drivers/pcmcia/libpcmcia.a
|
||||
ifeq ($(CPU),mpc83xx)
|
||||
LIBS += drivers/qe/qe.a
|
||||
endif
|
||||
ifeq ($(CPU),mpc85xx)
|
||||
LIBS += drivers/qe/qe.a
|
||||
endif
|
||||
LIBS += drivers/rtc/librtc.a
|
||||
LIBS += drivers/serial/libserial.a
|
||||
LIBS += drivers/sk98lin/libsk98lin.a
|
||||
LIBS += drivers/usb/libusb.a
|
||||
LIBS += drivers/video/libvideo.a
|
||||
LIBS += post/libpost.a post/drivers/libpostdrivers.a
|
||||
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
|
||||
"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
|
||||
|
|
@ -318,30 +329,70 @@ updater:
|
|||
$(MAKE) -C tools/updater all || exit 1
|
||||
|
||||
env:
|
||||
$(MAKE) -C tools/env all || exit 1
|
||||
$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
|
||||
|
||||
depend dep: version
|
||||
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
|
||||
|
||||
TAG_SUBDIRS += include
|
||||
TAG_SUBDIRS += lib_generic board/$(BOARDDIR)
|
||||
TAG_SUBDIRS += cpu/$(CPU)
|
||||
TAG_SUBDIRS += lib_$(ARCH)
|
||||
TAG_SUBDIRS += fs/cramfs
|
||||
TAG_SUBDIRS += fs/fat
|
||||
TAG_SUBDIRS += fs/fdos
|
||||
TAG_SUBDIRS += fs/jffs2
|
||||
TAG_SUBDIRS += net
|
||||
TAG_SUBDIRS += disk
|
||||
TAG_SUBDIRS += common
|
||||
TAG_SUBDIRS += drivers/bios_emulator
|
||||
TAG_SUBDIRS += drivers/block
|
||||
TAG_SUBDIRS += drivers/hwmon
|
||||
TAG_SUBDIRS += drivers/i2c
|
||||
TAG_SUBDIRS += drivers/input
|
||||
TAG_SUBDIRS += drivers/misc
|
||||
TAG_SUBDIRS += drivers/mtd
|
||||
TAG_SUBDIRS += drivers/mtd/nand
|
||||
TAG_SUBDIRS += drivers/mtd/nand_legacy
|
||||
TAG_SUBDIRS += drivers/mtd/onenand
|
||||
TAG_SUBDIRS += drivers/net
|
||||
TAG_SUBDIRS += drivers/net/sk98lin
|
||||
TAG_SUBDIRS += drivers/pci
|
||||
TAG_SUBDIRS += drivers/pcmcia
|
||||
TAG_SUBDIRS += drivers/qe
|
||||
TAG_SUBDIRS += drivers/rtc
|
||||
TAG_SUBDIRS += drivers/serial
|
||||
TAG_SUBDIRS += drivers/usb
|
||||
TAG_SUBDIRS += drivers/video
|
||||
|
||||
tags ctags:
|
||||
ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) include \
|
||||
lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
|
||||
fs/cramfs fs/fat fs/fdos fs/jffs2 \
|
||||
net disk rtc dtt drivers drivers/sk98lin common \
|
||||
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
|
||||
ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) $(TAG_SUBDIRS) \
|
||||
-name '*.[ch]' -print`
|
||||
|
||||
etags:
|
||||
etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) include \
|
||||
lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
|
||||
fs/cramfs fs/fat fs/fdos fs/jffs2 \
|
||||
net disk rtc dtt drivers drivers/sk98lin common \
|
||||
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
|
||||
etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) $(TAG_SUBDIRS) \
|
||||
-name '*.[ch]' -print`
|
||||
|
||||
$(obj)System.map: $(obj)u-boot
|
||||
@$(NM) $< | \
|
||||
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
|
||||
sort > $(obj)System.map
|
||||
|
||||
#
|
||||
# Auto-generate the autoconf.mk file (which is included by all makefiles)
|
||||
#
|
||||
# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
|
||||
# the dep file is only include in this top level makefile to determine when
|
||||
# to regenerate the autoconf.mk file.
|
||||
$(OBJTREE)/include/autoconf.mk: $(obj)include/config.h
|
||||
@echo Generating include/autoconf.mk
|
||||
@# Generate the dependancies
|
||||
@$(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $@ include/common.h > $@.dep
|
||||
@# Extract the config macros
|
||||
@$(CPP) $(CFLAGS) -dM include/common.h | sed -n -f tools/scripts/define2mk.sed >> $@
|
||||
|
||||
sinclude $(OBJTREE)/include/autoconf.mk.dep
|
||||
|
||||
#########################################################################
|
||||
else
|
||||
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
|
||||
|
|
@ -361,7 +412,8 @@ CHANGELOG:
|
|||
|
||||
unconfig:
|
||||
@rm -f $(obj)include/config.h $(obj)include/config.mk \
|
||||
$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp
|
||||
$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \
|
||||
$(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep
|
||||
|
||||
#========================================================================
|
||||
# PowerPC
|
||||
|
|
@ -1111,9 +1163,6 @@ CPCI405AB_config: unconfig
|
|||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
|
||||
@echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
|
||||
|
||||
CPCI440_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci440 esd
|
||||
|
||||
CPCIISER4_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
|
||||
|
||||
|
|
@ -1168,12 +1217,32 @@ KAREF_config: unconfig
|
|||
katmai_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc
|
||||
|
||||
# Kilauea & Haleakala images are identical (recognized via PVR)
|
||||
kilauea_config \
|
||||
haleakala_config: unconfig
|
||||
@$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc
|
||||
|
||||
kilauea_nand_config \
|
||||
haleakala_nand_config: unconfig
|
||||
@mkdir -p $(obj)include $(obj)board/amcc/kilauea
|
||||
@mkdir -p $(obj)nand_spl/board/amcc/kilauea
|
||||
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
|
||||
@$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc
|
||||
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp
|
||||
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
|
||||
korat_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx korat
|
||||
|
||||
luan_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
|
||||
|
||||
lwmon5_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
|
||||
|
||||
makalu_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc
|
||||
|
||||
METROBOX_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
|
||||
|
||||
|
|
@ -1217,6 +1286,9 @@ PLU405_config: unconfig
|
|||
PMC405_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
|
||||
|
||||
PMC440_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
|
||||
|
||||
PPChameleonEVB_config \
|
||||
PPChameleonEVB_BA_25_config \
|
||||
PPChameleonEVB_ME_25_config \
|
||||
|
|
@ -1610,14 +1682,14 @@ TQM8265_AA_config: unconfig
|
|||
fi; \
|
||||
echo "#define CONFIG_$${CFREQ}MHz" >>$(obj)include/config.h ; \
|
||||
echo "... with $${CFREQ}MHz system clock" ; \
|
||||
if [ "$${CACHE}" == "yes" ] ; then \
|
||||
if [ "$${CACHE}" = "yes" ] ; then \
|
||||
echo "#define CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
|
||||
echo "... with L2 Cache support" ; \
|
||||
else \
|
||||
echo "#undef CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
|
||||
echo "... without L2 Cache support" ; \
|
||||
fi; \
|
||||
if [ "$${BMODE}" == "60x" ] ; then \
|
||||
if [ "$${BMODE}" = "60x" ] ; then \
|
||||
echo "#define CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
|
||||
echo "... with 60x Bus Mode" ; \
|
||||
else \
|
||||
|
|
@ -1731,11 +1803,15 @@ M54455EVB_i66_config : unconfig
|
|||
M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
|
||||
esac; \
|
||||
>include/config.h ; \
|
||||
if [ "$${FLASH}" == "INTEL" ] ; then \
|
||||
if [ "$${FLASH}" = "INTEL" ] ; then \
|
||||
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
|
||||
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
|
||||
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
|
||||
echo "... with INTEL boot..." ; \
|
||||
else \
|
||||
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
|
||||
echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
|
||||
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
|
||||
echo "... with ATMEL boot..." ; \
|
||||
fi; \
|
||||
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
|
||||
|
|
@ -1846,6 +1922,16 @@ MPC8360EMDS_ATM_config: unconfig
|
|||
fi ;
|
||||
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
|
||||
|
||||
MPC837XEMDS_config \
|
||||
MPC837XEMDS_HOST_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _HOST_,$@)" ] ; then \
|
||||
echo -n "... PCI HOST " ; \
|
||||
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
|
||||
fi ;
|
||||
@$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
|
||||
|
||||
sbc8349_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
|
||||
|
||||
|
|
@ -1858,7 +1944,7 @@ TQM834x_config: unconfig
|
|||
#########################################################################
|
||||
|
||||
MPC8540ADS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
|
||||
|
||||
MPC8540EVAL_config \
|
||||
MPC8540EVAL_33_config \
|
||||
|
|
@ -1882,7 +1968,7 @@ MPC8540EVAL_66_slave_config: unconfig
|
|||
@$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
|
||||
|
||||
MPC8560ADS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale
|
||||
|
||||
MPC8541CDS_legacy_config \
|
||||
MPC8541CDS_config: unconfig
|
||||
|
|
@ -1892,7 +1978,7 @@ MPC8541CDS_config: unconfig
|
|||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||
echo "... legacy" ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
|
||||
@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale
|
||||
|
||||
MPC8544DS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
|
||||
|
|
@ -1905,7 +1991,7 @@ MPC8548CDS_config: unconfig
|
|||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||
echo "... legacy" ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
|
||||
@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale
|
||||
|
||||
MPC8555CDS_legacy_config \
|
||||
MPC8555CDS_config: unconfig
|
||||
|
|
@ -1915,10 +2001,10 @@ MPC8555CDS_config: unconfig
|
|||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||
echo "... legacy" ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
|
||||
@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale
|
||||
|
||||
MPC8568MDS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
|
||||
|
||||
PM854_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
|
||||
|
|
@ -1985,6 +2071,9 @@ TQM8560_config: unconfig
|
|||
## MPC86xx Systems
|
||||
#########################################################################
|
||||
|
||||
MPC8610HPCD_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
|
||||
|
||||
MPC8641HPCN_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
|
||||
|
||||
|
|
@ -2372,9 +2461,12 @@ zylonite_config :
|
|||
#########################################################################
|
||||
## ARM1136 Systems
|
||||
#########################################################################
|
||||
omap2420h4_config : unconfig
|
||||
omap2420h4_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
|
||||
|
||||
apollon_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
|
||||
|
||||
#========================================================================
|
||||
# i386
|
||||
#========================================================================
|
||||
|
|
@ -2603,7 +2695,30 @@ bf561-ezkit_config: unconfig
|
|||
#########################################################################
|
||||
|
||||
atstk1002_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
|
||||
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
|
||||
|
||||
atstk1003_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
|
||||
|
||||
atstk1004_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
|
||||
|
||||
#########################################################################
|
||||
#########################################################################
|
||||
#########################################################################
|
||||
|
||||
#########################################################################
|
||||
## sh4 (Renesas SuperH)
|
||||
#########################################################################
|
||||
ms7750se_config: unconfig
|
||||
@ >include/config.h
|
||||
@echo "#define CONFIG_MS7750SE 1" >> include/config.h
|
||||
@./mkconfig -a $(@:_config=) sh sh4 ms7750se
|
||||
|
||||
ms7722se_config : unconfig
|
||||
@ >include/config.h
|
||||
@echo "#define CONFIG_MS7722SE 1" >> include/config.h
|
||||
@./mkconfig -a $(@:_config=) sh sh4 ms7722se
|
||||
|
||||
#########################################################################
|
||||
#########################################################################
|
||||
|
|
|
|||
27
README
27
README
|
|
@ -235,9 +235,7 @@ The following options need to be configured:
|
|||
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
|
||||
|
||||
- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
|
||||
Define exactly one of
|
||||
CONFIG_ATSTK1002
|
||||
|
||||
Define exactly one, e.g. CONFIG_ATSTK1002
|
||||
|
||||
- CPU Module Type: (if CONFIG_COGENT is defined)
|
||||
Define exactly one of
|
||||
|
|
@ -1379,15 +1377,24 @@ The following options need to be configured:
|
|||
SPI configuration items (port pins to use, etc). For
|
||||
an example, see include/configs/sacsng.h.
|
||||
|
||||
- FPGA Support: CONFIG_FPGA_COUNT
|
||||
- FPGA Support: CONFIG_FPGA
|
||||
|
||||
Enables FPGA subsystem.
|
||||
|
||||
CONFIG_FPGA_<vendor>
|
||||
|
||||
Enables support for specific chip vendors.
|
||||
(ALTERA, XILINX)
|
||||
|
||||
CONFIG_FPGA_<family>
|
||||
|
||||
Enables support for FPGA family.
|
||||
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
|
||||
|
||||
CONFIG_FPGA_COUNT
|
||||
|
||||
Specify the number of FPGA devices to support.
|
||||
|
||||
CONFIG_FPGA
|
||||
|
||||
Used to specify the types of FPGA devices. For example,
|
||||
#define CONFIG_FPGA CFG_XILINX_VIRTEX2
|
||||
|
||||
CFG_FPGA_PROG_FEEDBACK
|
||||
|
||||
Enable printing of hash marks during FPGA configuration.
|
||||
|
|
@ -2123,7 +2130,7 @@ to save the current settings.
|
|||
to be a good choice since it makes it far enough from the
|
||||
start of the data area as well as from the stack pointer.
|
||||
|
||||
Please note that the environment is read-only as long as the monitor
|
||||
Please note that the environment is read-only until the monitor
|
||||
has been relocated to RAM and a RAM copy of the environment has been
|
||||
created; also, when using EEPROM you will have to use getenv_r()
|
||||
until then to read environment variables.
|
||||
|
|
|
|||
|
|
@ -21,4 +21,4 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ SECTIONS
|
|||
{
|
||||
cpu/mpc512x/start.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
|
|
|
|||
|
|
@ -67,13 +67,13 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
|
|||
0x00, /* Module data width continued: +0 */
|
||||
0x04, /* 2.5 Volt */
|
||||
0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
|
||||
0x00, /* SDRAM Access from clock */
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
0x02, /* ECC ON : 02 OFF : 00 */
|
||||
#else
|
||||
0x00, /* ECC ON : 02 OFF : 00 */
|
||||
#endif
|
||||
0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */
|
||||
0,
|
||||
0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
|
||||
0,
|
||||
0,
|
||||
0x01, /* wcsbc = 1 */
|
||||
|
|
|
|||
|
|
@ -62,19 +62,6 @@ SECTIONS
|
|||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -68,19 +68,6 @@ SECTIONS
|
|||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/ebony/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -24,21 +24,16 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
#include <asm-ppc/io.h>
|
||||
#include <asm-ppc/gpio.h>
|
||||
|
||||
#include "../cpu/ppc4xx/440spe_pcie.h"
|
||||
|
||||
#undef PCIE_ENDPOINT
|
||||
/* #define PCIE_ENDPOINT 1 */
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/4xx_pcie.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int ppc440spe_init_pcie_rootport(int port);
|
||||
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
unsigned long mfr;
|
||||
|
|
@ -224,10 +219,9 @@ int board_early_init_f (void)
|
|||
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
|
||||
|
||||
/* SDR0_MFR should be part of Ethernet init */
|
||||
mfsdr (sdr_mfr, mfr);
|
||||
mfr &= ~SDR0_MFR_ECS_MASK;
|
||||
/* mtsdr(sdr_mfr, mfr); */
|
||||
mfsdr(sdr_mfr, mfr);
|
||||
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
|
||||
mtsdr(sdr_mfr, mfr);
|
||||
|
||||
mtsdr(SDR0_PFC0, CFG_PFC0);
|
||||
|
||||
|
|
@ -252,6 +246,18 @@ int checkboard (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
|
||||
* board specific values.
|
||||
*/
|
||||
u32 ddr_wrdtr(u32 default_val) {
|
||||
return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
|
||||
}
|
||||
|
||||
u32 ddr_clktr(u32 default_val) {
|
||||
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
|
|
@ -396,6 +402,7 @@ void pcie_setup_hoses(int busno)
|
|||
{
|
||||
struct pci_controller *hose;
|
||||
int i, bus;
|
||||
int ret = 0;
|
||||
char *env;
|
||||
unsigned int delay;
|
||||
|
||||
|
|
@ -409,12 +416,13 @@ void pcie_setup_hoses(int busno)
|
|||
if (!katmai_pcie_card_present(i))
|
||||
continue;
|
||||
|
||||
#ifdef PCIE_ENDPOINT
|
||||
if (ppc440spe_init_pcie_endport(i)) {
|
||||
#else
|
||||
if (ppc440spe_init_pcie_rootport(i)) {
|
||||
#endif
|
||||
printf("PCIE%d: initialization failed\n", i);
|
||||
if (is_end_point(i))
|
||||
ret = ppc4xx_init_pcie_endport(i);
|
||||
else
|
||||
ret = ppc4xx_init_pcie_rootport(i);
|
||||
if (ret) {
|
||||
printf("PCIE%d: initialization as %s failed\n", i,
|
||||
is_end_point(i) ? "endpoint" : "root-complex");
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -428,35 +436,33 @@ void pcie_setup_hoses(int busno)
|
|||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMSIZE,
|
||||
PCI_REGION_MEM
|
||||
);
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count = 1;
|
||||
pci_register_hose(hose);
|
||||
|
||||
#ifdef PCIE_ENDPOINT
|
||||
ppc440spe_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
#else
|
||||
ppc440spe_setup_pcie_rootpoint(hose, i);
|
||||
if (is_end_point(i)) {
|
||||
ppc4xx_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
} else {
|
||||
ppc4xx_setup_pcie_rootpoint(hose, i);
|
||||
env = getenv ("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul(env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf("Warning, expect noticable delay before "
|
||||
"PCIe scan due to 'pciscandelay' value!\n");
|
||||
mdelay(delay * 1000);
|
||||
}
|
||||
|
||||
env = getenv ("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul (env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf ("Warning, expect noticable delay before PCIe"
|
||||
"scan due to 'pciscandelay' value!\n");
|
||||
mdelay (delay * 1000);
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
|
@ -541,3 +547,24 @@ int post_hotkeys_pressed(void)
|
|||
return (ctrlc());
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* Fixup NOR mapping */
|
||||
val[0] = 0; /* chip select number */
|
||||
val[1] = 0; /* always 0 */
|
||||
val[2] = gd->bd->bi_flashstart;
|
||||
val[3] = gd->bd->bi_flashsize;
|
||||
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||
val, sizeof(val), 1);
|
||||
if (rc)
|
||||
printf("Unable to update property NOR mapping, err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
|
|
|
|||
50
board/amcc/kilauea/Makefile
Normal file
50
board/amcc/kilauea/Makefile
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o cmd_pll.o memory.o
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend *~
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
297
board/amcc/kilauea/cmd_pll.c
Normal file
297
board/amcc/kilauea/cmd_pll.c
Normal file
|
|
@ -0,0 +1,297 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* ehnus: change pll frequency.
|
||||
* Wed Sep 5 11:45:17 CST 2007
|
||||
* hsun@udtech.com.cn
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <command.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#ifdef CONFIG_CMD_EEPROM
|
||||
|
||||
#define EEPROM_CONF_OFFSET 0
|
||||
#define EEPROM_TEST_OFFSET 16
|
||||
#define EEPROM_SDSTP_PARAM 16
|
||||
|
||||
#define PLL_NAME_MAX 12
|
||||
#define BUF_STEP 8
|
||||
|
||||
/* eeprom_wirtes 8Byte per op. */
|
||||
#define EEPROM_ALTER_FREQ(freq) \
|
||||
do { \
|
||||
int __i; \
|
||||
for (__i = 0; __i < 2; __i++) \
|
||||
eeprom_write (CFG_I2C_EEPROM_ADDR, \
|
||||
EEPROM_CONF_OFFSET + __i*BUF_STEP, \
|
||||
pll_select[freq], \
|
||||
BUF_STEP + __i*BUF_STEP); \
|
||||
} while (0)
|
||||
|
||||
#define PDEBUG
|
||||
#ifdef PDEBUG
|
||||
#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
|
||||
#else
|
||||
#define PLL_DEBUG
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PLL_ebc20,
|
||||
PLL_333,
|
||||
PLL_4001,
|
||||
PLL_4002,
|
||||
PLL_533,
|
||||
PLL_600,
|
||||
PLL_666, /* For now, kilauea can't support */
|
||||
RCONF,
|
||||
WTEST,
|
||||
PLL_TOTAL
|
||||
} pll_freq_t;
|
||||
|
||||
static const char
|
||||
pll_name[][PLL_NAME_MAX] = {
|
||||
"PLL_ebc20",
|
||||
"PLL_333",
|
||||
"PLL_400@1",
|
||||
"PLL_400@2",
|
||||
"PLL_533",
|
||||
"PLL_600",
|
||||
"PLL_666",
|
||||
"RCONF",
|
||||
"WTEST",
|
||||
""
|
||||
};
|
||||
|
||||
/*
|
||||
* ehnus:
|
||||
*/
|
||||
static uchar
|
||||
pll_select[][EEPROM_SDSTP_PARAM] = {
|
||||
/* 0: CPU 333MHz EBC 20MHz, for test only */
|
||||
{
|
||||
0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 0: 333 */
|
||||
{
|
||||
0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 1: 400_266 */
|
||||
{
|
||||
0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 2: 400 */
|
||||
{
|
||||
0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 3: 533 */
|
||||
{
|
||||
0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 4: 600 */
|
||||
{
|
||||
0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 5: 666 */
|
||||
{
|
||||
0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
{}
|
||||
};
|
||||
|
||||
static uchar
|
||||
testbuf[EEPROM_SDSTP_PARAM] = {
|
||||
0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
|
||||
0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
|
||||
};
|
||||
|
||||
static void
|
||||
pll_debug(int off)
|
||||
{
|
||||
int i;
|
||||
uchar buffer[EEPROM_SDSTP_PARAM];
|
||||
|
||||
memset(buffer, 0, sizeof(buffer));
|
||||
eeprom_read(CFG_I2C_EEPROM_ADDR, off,
|
||||
buffer, EEPROM_SDSTP_PARAM);
|
||||
|
||||
printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
|
||||
for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
|
||||
printf("%02x ", buffer[i]);
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static void
|
||||
test_write(void)
|
||||
{
|
||||
printf("Debug: test eeprom_write ... ");
|
||||
|
||||
/*
|
||||
* Write twice, 8 bytes per write
|
||||
*/
|
||||
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
|
||||
testbuf, 8);
|
||||
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
|
||||
testbuf, 16);
|
||||
printf("done\n");
|
||||
|
||||
pll_debug(EEPROM_TEST_OFFSET);
|
||||
}
|
||||
|
||||
int
|
||||
do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char c = '\0';
|
||||
pll_freq_t pll_freq;
|
||||
if (argc < 2) {
|
||||
printf("Usage: \n%s\n", cmdtp->usage);
|
||||
goto ret;
|
||||
}
|
||||
|
||||
for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
|
||||
if (!strcmp(pll_name[pll_freq], argv[1]))
|
||||
break;
|
||||
|
||||
switch (pll_freq) {
|
||||
case PLL_ebc20:
|
||||
case PLL_333:
|
||||
case PLL_4001:
|
||||
case PLL_4002:
|
||||
case PLL_533:
|
||||
case PLL_600:
|
||||
EEPROM_ALTER_FREQ(pll_freq);
|
||||
break;
|
||||
|
||||
case PLL_666: /* not support */
|
||||
printf("Choose this option will result in a boot failure."
|
||||
"\nContinue? (Y/N): ");
|
||||
|
||||
c = getc(); putc('\n');
|
||||
|
||||
if ((c == 'y') || (c == 'Y')) {
|
||||
EEPROM_ALTER_FREQ(pll_freq);
|
||||
break;
|
||||
}
|
||||
goto ret;
|
||||
|
||||
case RCONF:
|
||||
pll_debug(EEPROM_CONF_OFFSET);
|
||||
goto ret;
|
||||
case WTEST:
|
||||
printf("DEBUG: write test\n");
|
||||
test_write();
|
||||
goto ret;
|
||||
|
||||
default:
|
||||
printf("Invalid options"
|
||||
"\n\nUsage: \n%s\n", cmdtp->usage);
|
||||
goto ret;
|
||||
}
|
||||
|
||||
printf("PLL set to %s, "
|
||||
"reset the board to take effect\n", pll_name[pll_freq]);
|
||||
|
||||
PLL_DEBUG;
|
||||
ret:
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pllalter, CFG_MAXARGS, 1, do_pll_alter,
|
||||
"pllalter- change pll frequence \n",
|
||||
"pllalter <selection> - change pll frequence \n\n\
|
||||
** New freq take effect after reset. ** \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t Same as PLL_333 \n\
|
||||
\t except \n\
|
||||
\t EBC: 20 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 666 MHz \n\
|
||||
\t CPU: 333 MHz \n\
|
||||
\t PLB: 166 MHz \n\
|
||||
\t OPB: 83 MHz \n\
|
||||
\t DDR: 83 MHz \n\
|
||||
------------------------------------------------\n\
|
||||
PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 800 MHz \n\
|
||||
\t CPU: 400 MHz \n\
|
||||
\t PLB: 133 MHz \n\
|
||||
\t OPB: 66 MHz \n\
|
||||
\t DDR: 133 MHz \n\
|
||||
------------------------------------------------\n\
|
||||
PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 800 MHz \n\
|
||||
\t CPU: 400 MHz \n\
|
||||
\t PLB: 200 MHz \n\
|
||||
\t OPB: 100 MHz \n\
|
||||
\t DDR: 200 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1066 MHz \n\
|
||||
\t CPU: 533 MHz \n\
|
||||
\t PLB: 177 MHz \n\
|
||||
\t OPB: 88 MHz \n\
|
||||
\t DDR: 177 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1200 MHz \n\
|
||||
\t CPU: 600 MHz \n\
|
||||
\t PLB: 200 MHz \n\
|
||||
\t OPB: 100 MHz \n\
|
||||
\t DDR: 200 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1333 MHz \n\
|
||||
\t CPU: 666 MHz \n\
|
||||
\t PLB: 166 MHz \n\
|
||||
\t OPB: 83 MHz \n\
|
||||
\t DDR: 166 MHz \n\
|
||||
-----------------------------------------------\n\
|
||||
RCONF: Read current eeprom configuration. \n\
|
||||
-----------------------------------------------\n\
|
||||
WTEST: Test EEPROM write with predefined values\n\
|
||||
-----------------------------------------------\n"
|
||||
);
|
||||
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
|
||||
32
board/amcc/kilauea/config.mk
Normal file
32
board/amcc/kilauea/config.mk
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFFFA0000
|
||||
endif
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
154
board/amcc/kilauea/init.S
Normal file
154
board/amcc/kilauea/init.S
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on code provided from UDTech and AMCC
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <ppc4xx.h>
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
#define mtsdram_as(reg, value) \
|
||||
addi r4,0,reg ; \
|
||||
mtdcr memcfga,r4 ; \
|
||||
addis r4,0,value@h ; \
|
||||
ori r4,r4,value@l ; \
|
||||
mtdcr memcfgd,r4 ;
|
||||
|
||||
.globl ext_bus_cntlr_init
|
||||
ext_bus_cntlr_init:
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
|
||||
/*
|
||||
* DDR2 setup
|
||||
*/
|
||||
|
||||
/* Following the DDR Core Manual, here is the initialization */
|
||||
|
||||
/* Step 1 */
|
||||
|
||||
/* Step 2 */
|
||||
|
||||
/* Step 3 */
|
||||
|
||||
/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
|
||||
mtsdram_as(SDRAM_MB0CF, 0x00006701);
|
||||
|
||||
/* SET SDRAM_MB1CF - Not enabled */
|
||||
mtsdram_as(SDRAM_MB1CF, 0x00000000);
|
||||
|
||||
/* SET SDRAM_MB2CF - Not enabled */
|
||||
mtsdram_as(SDRAM_MB2CF, 0x00000000);
|
||||
|
||||
/* SET SDRAM_MB3CF - Not enabled */
|
||||
mtsdram_as(SDRAM_MB3CF, 0x00000000);
|
||||
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
||||
mtsdram_as(SDRAM_CLKTR, 0x80000000);
|
||||
|
||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
||||
mtsdram_as(SDRAM_RTR, 0x06180000);
|
||||
|
||||
/* SDRAM_SDTR1 */
|
||||
mtsdram_as(SDRAM_SDTR1, 0x80201000);
|
||||
|
||||
/* SDRAM_SDTR2 */
|
||||
mtsdram_as(SDRAM_SDTR2, 0x32204232);
|
||||
|
||||
/* SDRAM_SDTR3 */
|
||||
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
|
||||
|
||||
mtsdram_as(SDRAM_MMODE, 0x00000442);
|
||||
mtsdram_as(SDRAM_MEMODE, 0x00000404);
|
||||
|
||||
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
|
||||
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
|
||||
|
||||
/* NOP */
|
||||
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
|
||||
/* EMR2 twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
|
||||
/* EMR3 twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
|
||||
/* EMR DLL ENABLE twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
|
||||
/* MR w/ DLL reset
|
||||
* Note: 5 is CL. May need to be changed
|
||||
*/
|
||||
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
|
||||
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
|
||||
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
|
||||
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
|
||||
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
|
||||
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
|
||||
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
|
||||
|
||||
/* SET MCIF0_CODT Die Termination On */
|
||||
mtsdram_as(SDRAM_CODT, 0x0080f837);
|
||||
mtsdram_as(SDRAM_MODT0, 0x01800000);
|
||||
mtsdram_as(SDRAM_MODT1, 0x00000000);
|
||||
|
||||
mtsdram_as(SDRAM_WRDTR, 0x00000000);
|
||||
|
||||
/* SDRAM0_MCOPT2 (0X21) Start initialization */
|
||||
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
|
||||
|
||||
/* Step 5 */
|
||||
lis r3,0x1 /* 400000 = wait 100ms */
|
||||
mtctr r3
|
||||
|
||||
pll_wait:
|
||||
bdnz pll_wait
|
||||
|
||||
/* Step 6 */
|
||||
|
||||
/* SDRAM_DLCR */
|
||||
mtsdram_as(SDRAM_DLCR, 0x030000a5);
|
||||
|
||||
/* SDRAM_RDCC */
|
||||
mtsdram_as(SDRAM_RDCC, 0x40000000);
|
||||
|
||||
/* SDRAM_RQDC */
|
||||
mtsdram_as(SDRAM_RQDC, 0x80000038);
|
||||
|
||||
/* SDRAM_RFDC */
|
||||
mtsdram_as(SDRAM_RFDC, 0x00000209);
|
||||
|
||||
/* Enable memory controller */
|
||||
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
|
||||
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||
|
||||
blr
|
||||
392
board/amcc/kilauea/kilauea.c
Normal file
392
board/amcc/kilauea/kilauea.c
Normal file
|
|
@ -0,0 +1,392 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <ppc405.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#include <asm/4xx_pcie.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* Board early initialization function
|
||||
*/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
|
||||
+--------------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
|Interrupt| Source | Pol. | Sensi.| Crit. |
|
||||
+---------+-----------------------------------+-------+-------+-------+
|
||||
| IRQ 00 | UART0 | High | Level | Non |
|
||||
| IRQ 01 | UART1 | High | Level | Non |
|
||||
| IRQ 02 | IIC0 | High | Level | Non |
|
||||
| IRQ 03 | TBD | High | Level | Non |
|
||||
| IRQ 04 | TBD | High | Level | Non |
|
||||
| IRQ 05 | EBM | High | Level | Non |
|
||||
| IRQ 06 | BGI | High | Level | Non |
|
||||
| IRQ 07 | IIC1 | Rising| Edge | Non |
|
||||
| IRQ 08 | SPI | High | Lvl/ed| Non |
|
||||
| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
|
||||
| IRQ 10 | MAL TX EOB | High | Level | Non |
|
||||
| IRQ 11 | MAL RX EOB | High | Level | Non |
|
||||
| IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
|
||||
| IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
|
||||
| IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
|
||||
| IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
|
||||
| IRQ 16 | PCIE0 AL | high | Level | Non |
|
||||
| IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
|
||||
| IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
|
||||
| IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
|
||||
| IRQ 20 | PCIE0 TCR | High | Level | Non |
|
||||
| IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
|
||||
| IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
|
||||
| IRQ 23 | Security EIP-94 | High | Level | Non |
|
||||
| IRQ 24 | EMAC0 interrupt | High | Level | Non |
|
||||
| IRQ 25 | EMAC1 interrupt | High | Level | Non |
|
||||
| IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
|
||||
| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
|
||||
| IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
|
||||
| IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
|
||||
| IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
|
||||
| IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
|
||||
|----------------------------------------------------------------------
|
||||
| IRQ 32 | MAL Serr | High | Level | Non |
|
||||
| IRQ 33 | MAL Txde | High | Level | Non |
|
||||
| IRQ 34 | MAL Rxde | High | Level | Non |
|
||||
| IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
|
||||
| IRQ 36 | PCIE0 DCR Error | High | Level | Non |
|
||||
| IRQ 37 | EBC | High |Lvl Edg| Non |
|
||||
| IRQ 38 | NDFC | High | Level | Non |
|
||||
| IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
|
||||
| IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
|
||||
| IRQ 41 | PCIE1 AL | high | Level | Non |
|
||||
| IRQ 42 | PCIE1 VPD access | rising| edge | Non |
|
||||
| IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
|
||||
| IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
|
||||
| IRQ 45 | PCIE1 TCR | High | Level | Non |
|
||||
| IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
|
||||
| IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
|
||||
| IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
|
||||
| IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
|
||||
| IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
|
||||
| IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
|
||||
| IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
|
||||
| IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
|
||||
| IRQ 55 | Serial ROM | High | Level | Non |
|
||||
| IRQ 56 | GPT Decrement Pulse | High | Level | Non |
|
||||
| IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 60 | EMAC0 Wake-up | High | Level | Non |
|
||||
| IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 62 | EMAC1 Wake-up | High | Level | Non |
|
||||
|----------------------------------------------------------------------
|
||||
| IRQ 64 | PE0 AL | High | Level | Non |
|
||||
| IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 68 | PE0 TCR | High | Level | Non |
|
||||
| IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 70 | PE0 DCR Error | High | Level | Non |
|
||||
| IRQ 71 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 72 | PE1 AL | High | Level | Non |
|
||||
| IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 76 | PE1 TCR | High | Level | Non |
|
||||
| IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 78 | PE1 DCR Error | High | Level | Non |
|
||||
| IRQ 79 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 80 | PE2 AL | High | Level | Non |
|
||||
| IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 84 | PE2 TCR | High | Level | Non |
|
||||
| IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 86 | PE2 DCR Error | High | Level | Non |
|
||||
| IRQ 87 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 88 | External IRQ(5) | Progr | Progr | Non |
|
||||
| IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
|
||||
| IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 94 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 95 | Reserved | N/A | N/A | Non |
|
||||
|---------------------------------------------------------------------
|
||||
+---------+-----------------------------------+-------+-------+------*/
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialise UIC registers. Clear all interrupts. Disable all
|
||||
| interrupts.
|
||||
| Set critical interrupt values. Set interrupt polarities. Set
|
||||
| interrupt trigger levels. Make bit 0 High priority. Clear all
|
||||
| interrupts again.
|
||||
+-------------------------------------------------------------------*/
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
|
||||
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
|
||||
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
|
||||
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
|
||||
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
|
||||
/* Except cascade UIC0 and UIC1 */
|
||||
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
|
||||
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
/*
|
||||
* Note: Some cores are still in reset when the chip starts, so
|
||||
* take them out of reset
|
||||
*/
|
||||
mtsdr(SDR0_SRST, 0);
|
||||
|
||||
/*
|
||||
* Configure FPGA register with PCIe reset
|
||||
*/
|
||||
out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
|
||||
mdelay(50);
|
||||
out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
|
||||
|
||||
/* Configure 405EX for NAND usage */
|
||||
val = SDR0_CUST0_MUX_NDFC_SEL |
|
||||
SDR0_CUST0_NDFC_ENABLE |
|
||||
SDR0_CUST0_NDFC_BW_8_BIT |
|
||||
SDR0_CUST0_NRB_BUSY |
|
||||
(0x80000000 >> (28 + CFG_NAND_CS));
|
||||
mtsdr(SDR0_CUST0, val);
|
||||
|
||||
/*
|
||||
* Configure PFC (Pin Function Control) registers
|
||||
* -> Enable USB
|
||||
*/
|
||||
val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
|
||||
mtsdr(SDR0_PFC1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_emac_count(void)
|
||||
{
|
||||
u32 pvr = get_pvr();
|
||||
|
||||
/*
|
||||
* 405EXr only has one EMAC interface, 405EX has two
|
||||
*/
|
||||
if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
|
||||
return 1;
|
||||
else
|
||||
return 2;
|
||||
}
|
||||
|
||||
static int board_pcie_count(void)
|
||||
{
|
||||
u32 pvr = get_pvr();
|
||||
|
||||
/*
|
||||
* 405EXr only has one EMAC interface, 405EX has two
|
||||
*/
|
||||
if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
|
||||
return 1;
|
||||
else
|
||||
return 2;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
u32 pvr = get_pvr();
|
||||
|
||||
if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
|
||||
printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
|
||||
else
|
||||
printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller * hose )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller pcie_hose[2] = {{0},{0}};
|
||||
|
||||
void pcie_setup_hoses(int busno)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
int i, bus;
|
||||
int ret = 0;
|
||||
bus = busno;
|
||||
char *env;
|
||||
unsigned int delay;
|
||||
|
||||
for (i = 0; i < board_pcie_count(); i++) {
|
||||
|
||||
if (is_end_point(i))
|
||||
ret = ppc4xx_init_pcie_endport(i);
|
||||
else
|
||||
ret = ppc4xx_init_pcie_rootport(i);
|
||||
if (ret) {
|
||||
printf("PCIE%d: initialization as %s failed\n", i,
|
||||
is_end_point(i) ? "endpoint" : "root-complex");
|
||||
continue;
|
||||
}
|
||||
|
||||
hose = &pcie_hose[i];
|
||||
hose->first_busno = bus;
|
||||
hose->last_busno = bus;
|
||||
hose->current_busno = bus;
|
||||
|
||||
/* setup mem resource */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMSIZE,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count = 1;
|
||||
pci_register_hose(hose);
|
||||
|
||||
if (is_end_point(i)) {
|
||||
ppc4xx_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
} else {
|
||||
ppc4xx_setup_pcie_rootpoint(hose, i);
|
||||
env = getenv ("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul(env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf("Warning, expect noticable delay before "
|
||||
"PCIe scan due to 'pciscandelay' value!\n");
|
||||
mdelay(delay * 1000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* Fixup NOR mapping */
|
||||
val[0] = 0; /* chip select number */
|
||||
val[1] = 0; /* always 0 */
|
||||
val[2] = gd->bd->bi_flashstart;
|
||||
val[3] = gd->bd->bi_flashsize;
|
||||
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||
val, sizeof(val), 1);
|
||||
if (rc)
|
||||
printf("Unable to update property NOR mapping, err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
79
board/amcc/kilauea/memory.c
Normal file
79
board/amcc/kilauea/memory.c
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
printf ("testdram\n");
|
||||
#if defined (CONFIG_NAND_U_BOOT)
|
||||
return 0;
|
||||
#endif
|
||||
uint *pstart = (uint *) 0x00000000;
|
||||
uint *pend = (uint *) 0x00001000;
|
||||
uint *p;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
*p = 0xaaaaaaaa;
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
*p = 0x55555555;
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test passed!!!\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
137
board/amcc/kilauea/u-boot-nand.lds
Normal file
137
board/amcc/kilauea/u-boot-nand.lds
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
/* Align to next NAND block */
|
||||
. = ALIGN(0x4000);
|
||||
common/environment.o (.ppcenv)
|
||||
/* Keep some space here for redundant env and potential bad env blocks */
|
||||
. = ALIGN(0x10000);
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
137
board/amcc/kilauea/u-boot.lds
Normal file
137
board/amcc/kilauea/u-boot.lds
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* To compile successfully, uncomment the following section.
|
||||
* To go in ram, remove the section.
|
||||
* Added by SunHe.
|
||||
*/
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -39,6 +39,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
|||
************************************************************************/
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
u32 mfr;
|
||||
|
||||
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
|
||||
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
|
||||
mtebc( pb1ap, 0x03800000 );
|
||||
|
|
@ -64,6 +66,10 @@ int board_early_init_f(void)
|
|||
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
|
||||
mtdcr( uic0sr, 0xffffffff );
|
||||
|
||||
mfsdr(sdr_mfr, mfr);
|
||||
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
|
||||
mtsdr(sdr_mfr, mfr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
50
board/amcc/makalu/Makefile
Normal file
50
board/amcc/makalu/Makefile
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o cmd_pll.o memory.o
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend *~
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
297
board/amcc/makalu/cmd_pll.c
Normal file
297
board/amcc/makalu/cmd_pll.c
Normal file
|
|
@ -0,0 +1,297 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* ehnus: change pll frequency.
|
||||
* Wed Sep 5 11:45:17 CST 2007
|
||||
* hsun@udtech.com.cn
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <command.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#ifdef CONFIG_CMD_EEPROM
|
||||
|
||||
#define EEPROM_CONF_OFFSET 0
|
||||
#define EEPROM_TEST_OFFSET 16
|
||||
#define EEPROM_SDSTP_PARAM 16
|
||||
|
||||
#define PLL_NAME_MAX 12
|
||||
#define BUF_STEP 8
|
||||
|
||||
/* eeprom_wirtes 8Byte per op. */
|
||||
#define EEPROM_ALTER_FREQ(freq) \
|
||||
do { \
|
||||
int __i; \
|
||||
for (__i = 0; __i < 2; __i++) \
|
||||
eeprom_write (CFG_I2C_EEPROM_ADDR, \
|
||||
EEPROM_CONF_OFFSET + __i*BUF_STEP, \
|
||||
pll_select[freq], \
|
||||
BUF_STEP + __i*BUF_STEP); \
|
||||
} while (0)
|
||||
|
||||
#define PDEBUG
|
||||
#ifdef PDEBUG
|
||||
#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
|
||||
#else
|
||||
#define PLL_DEBUG
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PLL_ebc20,
|
||||
PLL_333,
|
||||
PLL_4001,
|
||||
PLL_4002,
|
||||
PLL_533,
|
||||
PLL_600,
|
||||
PLL_666, /* For now, kilauea can't support */
|
||||
RCONF,
|
||||
WTEST,
|
||||
PLL_TOTAL
|
||||
} pll_freq_t;
|
||||
|
||||
static const char
|
||||
pll_name[][PLL_NAME_MAX] = {
|
||||
"PLL_ebc20",
|
||||
"PLL_333",
|
||||
"PLL_400@1",
|
||||
"PLL_400@2",
|
||||
"PLL_533",
|
||||
"PLL_600",
|
||||
"PLL_666",
|
||||
"RCONF",
|
||||
"WTEST",
|
||||
""
|
||||
};
|
||||
|
||||
/*
|
||||
* ehnus:
|
||||
*/
|
||||
static uchar
|
||||
pll_select[][EEPROM_SDSTP_PARAM] = {
|
||||
/* 0: CPU 333MHz EBC 20MHz, for test only */
|
||||
{
|
||||
0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 0: 333 */
|
||||
{
|
||||
0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 1: 400_266 */
|
||||
{
|
||||
0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 2: 400 */
|
||||
{
|
||||
0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 3: 533 */
|
||||
{
|
||||
0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 4: 600 */
|
||||
{
|
||||
0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
/* 5: 666 */
|
||||
{
|
||||
0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
|
||||
0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
|
||||
},
|
||||
|
||||
{}
|
||||
};
|
||||
|
||||
static uchar
|
||||
testbuf[EEPROM_SDSTP_PARAM] = {
|
||||
0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
|
||||
0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
|
||||
};
|
||||
|
||||
static void
|
||||
pll_debug(int off)
|
||||
{
|
||||
int i;
|
||||
uchar buffer[EEPROM_SDSTP_PARAM];
|
||||
|
||||
memset(buffer, 0, sizeof(buffer));
|
||||
eeprom_read(CFG_I2C_EEPROM_ADDR, off,
|
||||
buffer, EEPROM_SDSTP_PARAM);
|
||||
|
||||
printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
|
||||
for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
|
||||
printf("%02x ", buffer[i]);
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static void
|
||||
test_write(void)
|
||||
{
|
||||
printf("Debug: test eeprom_write ... ");
|
||||
|
||||
/*
|
||||
* Write twice, 8 bytes per write
|
||||
*/
|
||||
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
|
||||
testbuf, 8);
|
||||
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
|
||||
testbuf, 16);
|
||||
printf("done\n");
|
||||
|
||||
pll_debug(EEPROM_TEST_OFFSET);
|
||||
}
|
||||
|
||||
int
|
||||
do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char c = '\0';
|
||||
pll_freq_t pll_freq;
|
||||
if (argc < 2) {
|
||||
printf("Usage: \n%s\n", cmdtp->usage);
|
||||
goto ret;
|
||||
}
|
||||
|
||||
for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
|
||||
if (!strcmp(pll_name[pll_freq], argv[1]))
|
||||
break;
|
||||
|
||||
switch (pll_freq) {
|
||||
case PLL_ebc20:
|
||||
case PLL_333:
|
||||
case PLL_4001:
|
||||
case PLL_4002:
|
||||
case PLL_533:
|
||||
case PLL_600:
|
||||
EEPROM_ALTER_FREQ(pll_freq);
|
||||
break;
|
||||
|
||||
case PLL_666: /* not support */
|
||||
printf("Choose this option will result in a boot failure."
|
||||
"\nContinue? (Y/N): ");
|
||||
|
||||
c = getc(); putc('\n');
|
||||
|
||||
if ((c == 'y') || (c == 'Y')) {
|
||||
EEPROM_ALTER_FREQ(pll_freq);
|
||||
break;
|
||||
}
|
||||
goto ret;
|
||||
|
||||
case RCONF:
|
||||
pll_debug(EEPROM_CONF_OFFSET);
|
||||
goto ret;
|
||||
case WTEST:
|
||||
printf("DEBUG: write test\n");
|
||||
test_write();
|
||||
goto ret;
|
||||
|
||||
default:
|
||||
printf("Invalid options"
|
||||
"\n\nUsage: \n%s\n", cmdtp->usage);
|
||||
goto ret;
|
||||
}
|
||||
|
||||
printf("PLL set to %s, "
|
||||
"reset the board to take effect\n", pll_name[pll_freq]);
|
||||
|
||||
PLL_DEBUG;
|
||||
ret:
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pllalter, CFG_MAXARGS, 1, do_pll_alter,
|
||||
"pllalter- change pll frequence \n",
|
||||
"pllalter <selection> - change pll frequence \n\n\
|
||||
** New freq take effect after reset. ** \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t Same as PLL_333 \n\
|
||||
\t except \n\
|
||||
\t EBC: 20 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 666 MHz \n\
|
||||
\t CPU: 333 MHz \n\
|
||||
\t PLB: 166 MHz \n\
|
||||
\t OPB: 83 MHz \n\
|
||||
\t DDR: 83 MHz \n\
|
||||
------------------------------------------------\n\
|
||||
PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 800 MHz \n\
|
||||
\t CPU: 400 MHz \n\
|
||||
\t PLB: 133 MHz \n\
|
||||
\t OPB: 66 MHz \n\
|
||||
\t DDR: 133 MHz \n\
|
||||
------------------------------------------------\n\
|
||||
PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 800 MHz \n\
|
||||
\t CPU: 400 MHz \n\
|
||||
\t PLB: 200 MHz \n\
|
||||
\t OPB: 100 MHz \n\
|
||||
\t DDR: 200 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1066 MHz \n\
|
||||
\t CPU: 533 MHz \n\
|
||||
\t PLB: 177 MHz \n\
|
||||
\t OPB: 88 MHz \n\
|
||||
\t DDR: 177 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1200 MHz \n\
|
||||
\t CPU: 600 MHz \n\
|
||||
\t PLB: 200 MHz \n\
|
||||
\t OPB: 100 MHz \n\
|
||||
\t DDR: 200 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1333 MHz \n\
|
||||
\t CPU: 666 MHz \n\
|
||||
\t PLB: 166 MHz \n\
|
||||
\t OPB: 83 MHz \n\
|
||||
\t DDR: 166 MHz \n\
|
||||
-----------------------------------------------\n\
|
||||
RCONF: Read current eeprom configuration. \n\
|
||||
-----------------------------------------------\n\
|
||||
WTEST: Test EEPROM write with predefined values\n\
|
||||
-----------------------------------------------\n"
|
||||
);
|
||||
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
|
||||
24
board/amcc/makalu/config.mk
Normal file
24
board/amcc/makalu/config.mk
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFA0000
|
||||
148
board/amcc/makalu/init.S
Normal file
148
board/amcc/makalu/init.S
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on code provided from Senao and AMCC
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <ppc4xx.h>
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
#define mtsdram_as(reg, value) \
|
||||
addi r4,0,reg ; \
|
||||
mtdcr memcfga,r4 ; \
|
||||
addis r4,0,value@h ; \
|
||||
ori r4,r4,value@l ; \
|
||||
mtdcr memcfgd,r4 ;
|
||||
|
||||
.globl ext_bus_cntlr_init
|
||||
ext_bus_cntlr_init:
|
||||
|
||||
/*
|
||||
* DDR2 setup
|
||||
*/
|
||||
|
||||
/* Following the DDR Core Manual, here is the initialization */
|
||||
|
||||
/* Step 1 */
|
||||
|
||||
/* Step 2 */
|
||||
|
||||
/* Step 3 */
|
||||
|
||||
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
|
||||
mtsdram_as(SDRAM_MB0CF, 0x00005201);
|
||||
|
||||
/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
|
||||
mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
|
||||
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
||||
mtsdram_as(SDRAM_CLKTR,0x80000000);
|
||||
|
||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
||||
mtsdram_as(SDRAM_RTR, 0x06180000);
|
||||
|
||||
/* SDRAM_SDTR1 */
|
||||
mtsdram_as(SDRAM_SDTR1, 0x80201000);
|
||||
|
||||
/* SDRAM_SDTR2 */
|
||||
mtsdram_as(SDRAM_SDTR2, 0x32204232);
|
||||
|
||||
/* SDRAM_SDTR3 */
|
||||
mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
|
||||
|
||||
mtsdram_as(SDRAM_MMODE, 0x00000442);
|
||||
mtsdram_as(SDRAM_MEMODE, 0x00000404);
|
||||
|
||||
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
|
||||
mtsdram_as(SDRAM_MCOPT1, 0x04322000);
|
||||
|
||||
/* NOP */
|
||||
mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram_as(SDRAM_INITPLR1, 0x81900400);
|
||||
/* EMR2 twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR2, 0x81020000);
|
||||
/* EMR3 twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR3, 0x81030000);
|
||||
/* EMR DLL ENABLE twr = 2tck */
|
||||
mtsdram_as(SDRAM_INITPLR4, 0x81010404);
|
||||
/* MR w/ DLL reset
|
||||
* Note: 5 is CL. May need to be changed
|
||||
*/
|
||||
mtsdram_as(SDRAM_INITPLR5, 0x81000542);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram_as(SDRAM_INITPLR6, 0x81900400);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
|
||||
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
|
||||
mtsdram_as(SDRAM_INITPLR11, 0x81000442);
|
||||
mtsdram_as(SDRAM_INITPLR12, 0x81010780);
|
||||
mtsdram_as(SDRAM_INITPLR13, 0x81010400);
|
||||
mtsdram_as(SDRAM_INITPLR14, 0x00000000);
|
||||
mtsdram_as(SDRAM_INITPLR15, 0x00000000);
|
||||
|
||||
/* SET MCIF0_CODT Die Termination On */
|
||||
mtsdram_as(SDRAM_CODT, 0x0080f837);
|
||||
mtsdram_as(SDRAM_MODT0, 0x01800000);
|
||||
#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
|
||||
mtsdram_as(SDRAM_MODT1, 0x00000000);
|
||||
#endif
|
||||
|
||||
mtsdram_as(SDRAM_WRDTR, 0x00000000);
|
||||
|
||||
/* SDRAM0_MCOPT2 (0X21) Start initialization */
|
||||
mtsdram_as(SDRAM_MCOPT2, 0x20000000);
|
||||
|
||||
/* Step 5 */
|
||||
lis r3,0x1 /* 400000 = wait 100ms */
|
||||
mtctr r3
|
||||
|
||||
pll_wait:
|
||||
bdnz pll_wait
|
||||
|
||||
/* Step 6 */
|
||||
|
||||
/* SDRAM_DLCR */
|
||||
mtsdram_as(SDRAM_DLCR, 0x030000a5);
|
||||
|
||||
/* SDRAM_RDCC */
|
||||
mtsdram_as(SDRAM_RDCC, 0x40000000);
|
||||
|
||||
/* SDRAM_RQDC */
|
||||
mtsdram_as(SDRAM_RQDC, 0x80000038);
|
||||
|
||||
/* SDRAM_RFDC */
|
||||
mtsdram_as(SDRAM_RFDC, 0x00000209);
|
||||
|
||||
/* Enable memory controller */
|
||||
mtsdram_as(SDRAM_MCOPT2, 0x28000000);
|
||||
|
||||
blr
|
||||
352
board/amcc/makalu/makalu.c
Normal file
352
board/amcc/makalu/makalu.c
Normal file
|
|
@ -0,0 +1,352 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <ppc405.h>
|
||||
#include <libfdt.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#include <asm/4xx_pcie.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* Board early initialization function
|
||||
*/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
|
||||
+--------------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
|Interrupt| Source | Pol. | Sensi.| Crit. |
|
||||
+---------+-----------------------------------+-------+-------+-------+
|
||||
| IRQ 00 | UART0 | High | Level | Non |
|
||||
| IRQ 01 | UART1 | High | Level | Non |
|
||||
| IRQ 02 | IIC0 | High | Level | Non |
|
||||
| IRQ 03 | TBD | High | Level | Non |
|
||||
| IRQ 04 | TBD | High | Level | Non |
|
||||
| IRQ 05 | EBM | High | Level | Non |
|
||||
| IRQ 06 | BGI | High | Level | Non |
|
||||
| IRQ 07 | IIC1 | Rising| Edge | Non |
|
||||
| IRQ 08 | SPI | High | Lvl/ed| Non |
|
||||
| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
|
||||
| IRQ 10 | MAL TX EOB | High | Level | Non |
|
||||
| IRQ 11 | MAL RX EOB | High | Level | Non |
|
||||
| IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
|
||||
| IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
|
||||
| IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
|
||||
| IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
|
||||
| IRQ 16 | PCIE0 AL | high | Level | Non |
|
||||
| IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
|
||||
| IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
|
||||
| IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
|
||||
| IRQ 20 | PCIE0 TCR | High | Level | Non |
|
||||
| IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
|
||||
| IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
|
||||
| IRQ 23 | Security EIP-94 | High | Level | Non |
|
||||
| IRQ 24 | EMAC0 interrupt | High | Level | Non |
|
||||
| IRQ 25 | EMAC1 interrupt | High | Level | Non |
|
||||
| IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
|
||||
| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
|
||||
| IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
|
||||
| IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
|
||||
| IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
|
||||
| IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
|
||||
|----------------------------------------------------------------------
|
||||
| IRQ 32 | MAL Serr | High | Level | Non |
|
||||
| IRQ 33 | MAL Txde | High | Level | Non |
|
||||
| IRQ 34 | MAL Rxde | High | Level | Non |
|
||||
| IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
|
||||
| IRQ 36 | PCIE0 DCR Error | High | Level | Non |
|
||||
| IRQ 37 | EBC | High |Lvl Edg| Non |
|
||||
| IRQ 38 | NDFC | High | Level | Non |
|
||||
| IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
|
||||
| IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
|
||||
| IRQ 41 | PCIE1 AL | high | Level | Non |
|
||||
| IRQ 42 | PCIE1 VPD access | rising| edge | Non |
|
||||
| IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
|
||||
| IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
|
||||
| IRQ 45 | PCIE1 TCR | High | Level | Non |
|
||||
| IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
|
||||
| IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
|
||||
| IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
|
||||
| IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
|
||||
| IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
|
||||
| IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
|
||||
| IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
|
||||
| IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
|
||||
| IRQ 55 | Serial ROM | High | Level | Non |
|
||||
| IRQ 56 | GPT Decrement Pulse | High | Level | Non |
|
||||
| IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 60 | EMAC0 Wake-up | High | Level | Non |
|
||||
| IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
|
||||
| IRQ 62 | EMAC1 Wake-up | High | Level | Non |
|
||||
|----------------------------------------------------------------------
|
||||
| IRQ 64 | PE0 AL | High | Level | Non |
|
||||
| IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 68 | PE0 TCR | High | Level | Non |
|
||||
| IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 70 | PE0 DCR Error | High | Level | Non |
|
||||
| IRQ 71 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 72 | PE1 AL | High | Level | Non |
|
||||
| IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 76 | PE1 TCR | High | Level | Non |
|
||||
| IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 78 | PE1 DCR Error | High | Level | Non |
|
||||
| IRQ 79 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 80 | PE2 AL | High | Level | Non |
|
||||
| IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
|
||||
| IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
|
||||
| IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
|
||||
| IRQ 84 | PE2 TCR | High | Level | Non |
|
||||
| IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
|
||||
| IRQ 86 | PE2 DCR Error | High | Level | Non |
|
||||
| IRQ 87 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 88 | External IRQ(5) | Progr | Progr | Non |
|
||||
| IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
|
||||
| IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
|
||||
| IRQ 94 | Reserved | N/A | N/A | Non |
|
||||
| IRQ 95 | Reserved | N/A | N/A | Non |
|
||||
|---------------------------------------------------------------------
|
||||
+---------+-----------------------------------+-------+-------+------*/
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialise UIC registers. Clear all interrupts. Disable all
|
||||
| interrupts.
|
||||
| Set critical interrupt values. Set interrupt polarities. Set
|
||||
| interrupt trigger levels. Make bit 0 High priority. Clear all
|
||||
| interrupts again.
|
||||
+-------------------------------------------------------------------*/
|
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
|
||||
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
|
||||
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
|
||||
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
|
||||
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
|
||||
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
|
||||
/* Except cascade UIC0 and UIC1 */
|
||||
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
|
||||
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
|
||||
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
|
||||
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
|
||||
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
/*
|
||||
* Note: Some cores are still in reset when the chip starts, so
|
||||
* take them out of reset
|
||||
*/
|
||||
mtsdr(SDR0_SRST, 0);
|
||||
|
||||
/* Reset PCIe slots */
|
||||
gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
|
||||
udelay(100);
|
||||
gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
|
||||
|
||||
/*
|
||||
* Configure PFC (Pin Function Control) registers
|
||||
* -> Enable USB
|
||||
*/
|
||||
val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
|
||||
mtsdr(SDR0_PFC1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller * hose )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller pcie_hose[2] = {{0},{0}};
|
||||
|
||||
void pcie_setup_hoses(int busno)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
int i, bus;
|
||||
int ret = 0;
|
||||
bus = busno;
|
||||
char *env;
|
||||
unsigned int delay;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
|
||||
if (is_end_point(i))
|
||||
ret = ppc4xx_init_pcie_endport(i);
|
||||
else
|
||||
ret = ppc4xx_init_pcie_rootport(i);
|
||||
if (ret) {
|
||||
printf("PCIE%d: initialization as %s failed\n", i,
|
||||
is_end_point(i) ? "endpoint" : "root-complex");
|
||||
continue;
|
||||
}
|
||||
|
||||
hose = &pcie_hose[i];
|
||||
hose->first_busno = bus;
|
||||
hose->last_busno = bus;
|
||||
hose->current_busno = bus;
|
||||
|
||||
/* setup mem resource */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMSIZE,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count = 1;
|
||||
pci_register_hose(hose);
|
||||
|
||||
if (is_end_point(i)) {
|
||||
ppc4xx_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
} else {
|
||||
ppc4xx_setup_pcie_rootpoint(hose, i);
|
||||
env = getenv ("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul(env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf("Warning, expect noticable delay before "
|
||||
"PCIe scan due to 'pciscandelay' value!\n");
|
||||
mdelay(delay * 1000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* Fixup NOR mapping */
|
||||
val[0] = 0; /* chip select number */
|
||||
val[1] = 0; /* always 0 */
|
||||
val[2] = gd->bd->bi_flashstart;
|
||||
val[3] = gd->bd->bi_flashsize;
|
||||
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||
val, sizeof(val), 1);
|
||||
if (rc)
|
||||
printf("Unable to update property NOR mapping, err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
188
board/amcc/makalu/memory.c
Normal file
188
board/amcc/makalu/memory.c
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
/*
|
||||
* Same as on Kilauea, Makalu generates exception 0x200
|
||||
* (machine check) after trap_init() in board_init_f,
|
||||
* when SDRAM is initialized here (late) and d-cache is
|
||||
* used earlier as INIT_RAM.
|
||||
* So for now, initialize DDR2 in init.S very early and
|
||||
* also use it for INIT_RAM. Then this exception doesn't
|
||||
* occur.
|
||||
*/
|
||||
#if 0
|
||||
u32 val;
|
||||
|
||||
/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
|
||||
mtsdram(SDRAM_MB0CF, 0x00005201);
|
||||
|
||||
/* SET SDRAM_MB1CF - Not enabled */
|
||||
mtsdram(SDRAM_MB1CF, 0x00000000);
|
||||
|
||||
/* SET SDRAM_MB2CF - Not enabled */
|
||||
mtsdram(SDRAM_MB2CF, 0x00000000);
|
||||
|
||||
/* SET SDRAM_MB3CF - Not enabled */
|
||||
mtsdram(SDRAM_MB3CF, 0x00000000);
|
||||
|
||||
/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
|
||||
mtsdram(SDRAM_CLKTR, 0x80000000);
|
||||
|
||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
||||
mtsdram(SDRAM_RTR, 0x06180000);
|
||||
|
||||
/* SDRAM_SDTR1 */
|
||||
mtsdram(SDRAM_SDTR1, 0x80201000);
|
||||
|
||||
/* SDRAM_SDTR2 */
|
||||
mtsdram(SDRAM_SDTR2, 0x32204232);
|
||||
|
||||
/* SDRAM_SDTR3 */
|
||||
mtsdram(SDRAM_SDTR3, 0x080b0d1a);
|
||||
|
||||
mtsdram(SDRAM_MMODE, 0x00000442);
|
||||
mtsdram(SDRAM_MEMODE, 0x00000404);
|
||||
|
||||
/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
|
||||
mtsdram(SDRAM_MCOPT1, 0x04322000);
|
||||
|
||||
/* NOP */
|
||||
mtsdram(SDRAM_INITPLR0, 0xa8380000);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram(SDRAM_INITPLR1, 0x81900400);
|
||||
/* EMR2 twr = 2tck */
|
||||
mtsdram(SDRAM_INITPLR2, 0x81020000);
|
||||
/* EMR3 twr = 2tck */
|
||||
mtsdram(SDRAM_INITPLR3, 0x81030000);
|
||||
/* EMR DLL ENABLE twr = 2tck */
|
||||
mtsdram(SDRAM_INITPLR4, 0x81010404);
|
||||
/* MR w/ DLL reset
|
||||
* Note: 5 is CL. May need to be changed
|
||||
*/
|
||||
mtsdram(SDRAM_INITPLR5, 0x81000542);
|
||||
/* precharge 3 DDR clock cycle */
|
||||
mtsdram(SDRAM_INITPLR6, 0x81900400);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram(SDRAM_INITPLR7, 0x8D080000);
|
||||
/* Auto-refresh trfc = 26tck */
|
||||
mtsdram(SDRAM_INITPLR8, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram(SDRAM_INITPLR9, 0x8D080000);
|
||||
/* Auto-refresh */
|
||||
mtsdram(SDRAM_INITPLR10, 0x8D080000);
|
||||
/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
|
||||
mtsdram(SDRAM_INITPLR11, 0x81000442);
|
||||
mtsdram(SDRAM_INITPLR12, 0x81010780);
|
||||
mtsdram(SDRAM_INITPLR13, 0x81010400);
|
||||
mtsdram(SDRAM_INITPLR14, 0x00000000);
|
||||
mtsdram(SDRAM_INITPLR15, 0x00000000);
|
||||
|
||||
/* SET MCIF0_CODT Die Termination On */
|
||||
mtsdram(SDRAM_CODT, 0x0080f837);
|
||||
mtsdram(SDRAM_MODT0, 0x01800000);
|
||||
mtsdram(SDRAM_MODT1, 0x00000000);
|
||||
|
||||
mtsdram(SDRAM_WRDTR, 0x00000000);
|
||||
|
||||
/* SDRAM0_MCOPT2 (0X21) Start initialization */
|
||||
mtsdram(SDRAM_MCOPT2, 0x20000000);
|
||||
|
||||
/* Step 5 */
|
||||
do {
|
||||
mfsdram(SDRAM_MCSTAT, val);
|
||||
} while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
|
||||
|
||||
/* Step 6 */
|
||||
|
||||
/* SDRAM_DLCR */
|
||||
mtsdram(SDRAM_DLCR, 0x030000a5);
|
||||
|
||||
/* SDRAM_RDCC */
|
||||
mtsdram(SDRAM_RDCC, 0x40000000);
|
||||
|
||||
/* SDRAM_RQDC */
|
||||
mtsdram(SDRAM_RQDC, 0x80000038);
|
||||
|
||||
/* SDRAM_RFDC */
|
||||
mtsdram(SDRAM_RFDC, 0x00000209);
|
||||
|
||||
/* Enable memory controller */
|
||||
mfsdram(SDRAM_MCOPT2, val);
|
||||
val |= SDRAM_MCOPT2_DCEN_ENABLE;
|
||||
mtsdram(SDRAM_MCOPT2, val);
|
||||
#endif
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
printf ("testdram\n");
|
||||
#if defined (CONFIG_NAND_U_BOOT)
|
||||
return 0;
|
||||
#endif
|
||||
uint *pstart = (uint *) 0x00000000;
|
||||
uint *pend = (uint *) 0x00001000;
|
||||
uint *p;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
*p = 0xaaaaaaaa;
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
*p = 0x55555555;
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#if !defined (CONFIG_NAND_SPL)
|
||||
printf ("SDRAM test passed!!!\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
137
board/amcc/makalu/u-boot.lds
Normal file
137
board/amcc/makalu/u-boot.lds
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* To compile successfully, uncomment the following section.
|
||||
* To go in ram, remove the section.
|
||||
* Added by SunHe.
|
||||
*/
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -68,19 +68,6 @@ SECTIONS
|
|||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/ocotea/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -20,57 +20,9 @@
|
|||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm-ppc/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
#define _256M 0x10000000
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_8M 0x00000060
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
|
|
@ -98,7 +50,11 @@ tlbtab:
|
|||
#endif
|
||||
|
||||
/* TLB-entry for DDR SDRAM (Up to 2GB) */
|
||||
#ifdef CONFIG_4xx_DCACHE
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
#else
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
#endif
|
||||
|
||||
#ifdef CFG_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
|
|
|
|||
|
|
@ -33,343 +33,11 @@
|
|||
#include <asm/io.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
#include "sdram.h"
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
|
||||
defined(CONFIG_DDR_DATA_EYE)
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* wait_for_dlllock.
|
||||
+----------------------------------------------------------------------------*/
|
||||
static int wait_for_dlllock(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int wait = 0;
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
|
||||
/* dlllockreg bit on */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||
debug("Waiting for dlllockreg bit to raise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_DATA_EYE)
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* wait_for_dram_init_complete.
|
||||
+----------------------------------------------------------------------------*/
|
||||
int wait_for_dram_init_complete(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int wait = 0;
|
||||
|
||||
/* --------------------------------------------------------------+
|
||||
* Wait for 'DRAM initialization complete' bit in status register
|
||||
* -------------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_00);
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
|
||||
/* 'DRAM initialization complete' bit */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
|
||||
debug("DRAM initialization complete bit in status register did not rise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define NUM_TRIES 64
|
||||
#define NUM_READS 10
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* denali_core_search_data_eye.
|
||||
+----------------------------------------------------------------------------*/
|
||||
void denali_core_search_data_eye(unsigned long memory_size)
|
||||
{
|
||||
int k, j;
|
||||
u32 val;
|
||||
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
|
||||
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
|
||||
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
|
||||
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
|
||||
volatile u32 *ram_pointer;
|
||||
u32 test[NUM_TRIES] = {
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
|
||||
|
||||
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
|
||||
|
||||
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
|
||||
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'wr_dqs_shift'
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
* ----------------------------------------------------------*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
passing_cases = 0;
|
||||
|
||||
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
|
||||
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
* ----------------------------------------------------------*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
|
||||
/* write values */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
ram_pointer[j] = test[j];
|
||||
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
}
|
||||
|
||||
/* read values back */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
for (k=0; k<NUM_READS; k++) {
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
|
||||
if (ram_pointer[j] != test[j])
|
||||
break;
|
||||
}
|
||||
|
||||
/* read error */
|
||||
if (k != NUM_READS)
|
||||
break;
|
||||
}
|
||||
|
||||
/* See if the dll_dqs_delay_X value passed.*/
|
||||
if (j < NUM_TRIES) {
|
||||
/* Failed */
|
||||
passing_cases = 0;
|
||||
/* break; */
|
||||
} else {
|
||||
/* Passed */
|
||||
if (passing_cases == 0)
|
||||
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
|
||||
passing_cases++;
|
||||
if (passing_cases >= max_passing_cases) {
|
||||
max_passing_cases = passing_cases;
|
||||
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
|
||||
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
|
||||
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
|
||||
}
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
|
||||
|
||||
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Largest passing window is now detected.
|
||||
* ----------------------------------------------------------*/
|
||||
|
||||
/* Compute dll_dqs_delay_X value */
|
||||
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
|
||||
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
|
||||
|
||||
debug("DQS calibration - Window detected:\n");
|
||||
debug("max_passing_cases = %d\n", max_passing_cases);
|
||||
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
|
||||
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
|
||||
debug("dll_dqs_delay_X window = %d - %d\n",
|
||||
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'wr_dqs_shift'
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_09=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
* ----------------------------------------------------------*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_22=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
* ----------------------------------------------------------*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_17=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_18=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_19=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
}
|
||||
#endif /* CONFIG_DDR_DATA_EYE */
|
||||
* Prototypes
|
||||
*-----------------------------------------------------------------------------*/
|
||||
extern int denali_wait_for_dlllock(void);
|
||||
extern void denali_core_search_data_eye(void);
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
|
||||
|
|
@ -428,14 +96,14 @@ long int initdram (int board_type)
|
|||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
|
||||
wait_for_dlllock();
|
||||
denali_wait_for_dlllock();
|
||||
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/* -----------------------------------------------------------+
|
||||
* Perform data eye search if requested.
|
||||
* ----------------------------------------------------------*/
|
||||
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
|
||||
denali_core_search_data_eye();
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
|
|
|
|||
|
|
@ -1,505 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SPD_SDRAM_DENALI_H_
|
||||
#define _SPD_SDRAM_DENALI_H_
|
||||
|
||||
#define ppcMsync sync
|
||||
#define ppcMbar eieio
|
||||
|
||||
/* General definitions */
|
||||
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||
|
||||
/* Supported PLB Frequencies */
|
||||
#define PLB_FREQ_133MHZ 133333333
|
||||
#define PLB_FREQ_152MHZ 152000000
|
||||
#define PLB_FREQ_160MHZ 160000000
|
||||
#define PLB_FREQ_166MHZ 166666666
|
||||
|
||||
/* Denali Core Registers */
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Values for ddrcfga register - indirect addressing of these regs
|
||||
+-----------------------------------------------------------------------------*/
|
||||
|
||||
#define DDR0_00 0x00
|
||||
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
/* Status */
|
||||
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||
/* Bit2. Single correctable ECC event detected */
|
||||
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||
/* Bit3. Multiple correctable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||
/* Bit4. Single uncorrectable ECC event detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||
/* Bit6. DRAM initialization complete. */
|
||||
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||
/* Bit7. Logical OR of all lower bits. */
|
||||
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||
|
||||
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_01 0x01
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_02 0x02
|
||||
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_02_START_MASK 0x00000001
|
||||
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
#define DDR0_02_START_OFF 0x00000000
|
||||
#define DDR0_02_START_ON 0x00000001
|
||||
|
||||
#define DDR0_03 0x03
|
||||
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_04 0x04
|
||||
#define DDR0_04_TRC_MASK 0x1F000000
|
||||
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_04_TRRD_MASK 0x00070000
|
||||
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_04_TRTP_MASK 0x00000700
|
||||
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
|
||||
#define DDR0_05 0x05
|
||||
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_05_TRP_MASK 0x00000F00
|
||||
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#define DDR0_06 0x06
|
||||
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_06_TWTR_MASK 0x00070000
|
||||
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_07 0x07
|
||||
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_08 0x08
|
||||
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_09 0x09
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_10 0x0A
|
||||
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||
|
||||
#define DDR0_11 0x0B
|
||||
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
|
||||
#define DDR0_12 0x0C
|
||||
#define DDR0_12_TCKE_MASK 0x0000007
|
||||
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||
|
||||
#define DDR0_13 0x0D
|
||||
|
||||
#define DDR0_14 0x0E
|
||||
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_14_REDUC_MASK 0x00010000
|
||||
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
|
||||
#define DDR0_15 0x0F
|
||||
|
||||
#define DDR0_16 0x10
|
||||
|
||||
#define DDR0_17 0x11
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
|
||||
#define DDR0_18 0x12
|
||||
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_19 0x13
|
||||
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_20 0x14
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_21 0x15
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_23 0x17
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_24 0x18
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||
|
||||
#define DDR0_25 0x19
|
||||
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_26 0x1A
|
||||
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_27 0x1B
|
||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_28 0x1C
|
||||
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_29 0x1D
|
||||
|
||||
#define DDR0_30 0x1E
|
||||
|
||||
#define DDR0_31 0x1F
|
||||
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_32 0x20
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_33 0x21
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_34 0x22
|
||||
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_35 0x23
|
||||
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_36 0x24
|
||||
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_37 0x25
|
||||
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_38 0x26
|
||||
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_39 0x27
|
||||
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_40 0x28
|
||||
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_41 0x29
|
||||
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_42 0x2A
|
||||
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_43 0x2B
|
||||
#define DDR0_43_TWR_MASK 0x07000000
|
||||
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_44 0x2C
|
||||
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#endif /* _SPD_SDRAM_DENALI_H_ */
|
||||
|
|
@ -23,9 +23,13 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <ppc440.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <ppc440.h>
|
||||
#include <asm/ppc4xx-intvec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -42,36 +46,6 @@ int board_early_init_f(void)
|
|||
mtdcr(ebccfga, xbcfg);
|
||||
mtdcr(ebccfgd, 0xb8400000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the GPIO pins
|
||||
*-------------------------------------------------------------------*/
|
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||
out32(GPIO0_OR, 0x00000000);
|
||||
out32(GPIO0_TCR, 0x0000000f);
|
||||
out32(GPIO0_OSRL, 0x50015400);
|
||||
out32(GPIO0_OSRH, 0x550050aa);
|
||||
out32(GPIO0_TSRL, 0x50015400);
|
||||
out32(GPIO0_TSRH, 0x55005000);
|
||||
out32(GPIO0_ISR1L, 0x50000000);
|
||||
out32(GPIO0_ISR1H, 0x00000000);
|
||||
out32(GPIO0_ISR2L, 0x00000000);
|
||||
out32(GPIO0_ISR2H, 0x00000100);
|
||||
out32(GPIO0_ISR3L, 0x00000000);
|
||||
out32(GPIO0_ISR3H, 0x00000000);
|
||||
|
||||
out32(GPIO1_OR, 0x00000000);
|
||||
out32(GPIO1_TCR, 0xc2000000);
|
||||
out32(GPIO1_OSRL, 0x5c280000);
|
||||
out32(GPIO1_OSRH, 0x00000000);
|
||||
out32(GPIO1_TSRL, 0x0c000000);
|
||||
out32(GPIO1_TSRH, 0x00000000);
|
||||
out32(GPIO1_ISR1L, 0x00005550);
|
||||
out32(GPIO1_ISR1H, 0x00000000);
|
||||
out32(GPIO1_ISR2L, 0x00050000);
|
||||
out32(GPIO1_ISR2H, 0x00000000);
|
||||
out32(GPIO1_ISR3L, 0x01400000);
|
||||
out32(GPIO1_ISR3H, 0x00000000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
|
|
@ -100,16 +74,16 @@ int board_early_init_f(void)
|
|||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
|
||||
/* 50MHz tmrclk */
|
||||
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
|
||||
out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
|
||||
|
||||
/* clear write protects */
|
||||
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
|
||||
out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
|
||||
|
||||
/* enable Ethernet */
|
||||
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
|
||||
out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
|
||||
|
||||
/* enable USB device */
|
||||
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
|
||||
out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
|
||||
|
||||
/* select Ethernet pins */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
|
|
@ -414,6 +388,16 @@ int testdram(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
|
||||
/*
|
||||
* Assign interrupts to PCI devices.
|
||||
*/
|
||||
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||
{
|
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
|
|
@ -465,6 +449,9 @@ int pci_pre_init(struct pci_controller *hose)
|
|||
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
||||
mtdcr(plb1_acr, addr);
|
||||
|
||||
#ifdef CONFIG_PCI_PNP
|
||||
hose->fixup_irq = sequoia_pci_fixup_irq;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
|
@ -583,3 +570,24 @@ int post_hotkeys_pressed(void)
|
|||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* Fixup NOR mapping */
|
||||
val[0] = 0; /* chip select number */
|
||||
val[1] = 0; /* always 0 */
|
||||
val[2] = gd->bd->bi_flashstart;
|
||||
val[3] = gd->bd->bi_flashsize;
|
||||
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||
val, sizeof(val), 1);
|
||||
if (rc)
|
||||
printf("Unable to update property NOR mapping, err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
|
|
|
|||
|
|
@ -62,19 +62,6 @@ SECTIONS
|
|||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -33,25 +33,25 @@ void show_reset_reg(void)
|
|||
|
||||
/* read clock regsiter */
|
||||
printf("===== Display reset and initialize register Start =========\n");
|
||||
mfclk(clk_pllc,reg);
|
||||
mfcpr(clk_pllc,reg);
|
||||
printf("cpr_pllc = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_plld,reg);
|
||||
mfcpr(clk_plld,reg);
|
||||
printf("cpr_plld = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_primad,reg);
|
||||
mfcpr(clk_primad,reg);
|
||||
printf("cpr_primad = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_primbd,reg);
|
||||
mfcpr(clk_primbd,reg);
|
||||
printf("cpr_primbd = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_opbd,reg);
|
||||
mfcpr(clk_opbd,reg);
|
||||
printf("cpr_opbd = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_perd,reg);
|
||||
mfcpr(clk_perd,reg);
|
||||
printf("cpr_perd = %#010x\n",reg);
|
||||
|
||||
mfclk(clk_mald,reg);
|
||||
mfcpr(clk_mald,reg);
|
||||
printf("cpr_mald = %#010x\n",reg);
|
||||
|
||||
/* read sdr register */
|
||||
|
|
|
|||
|
|
@ -68,19 +68,6 @@ SECTIONS
|
|||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/taishan/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -62,19 +62,6 @@ SECTIONS
|
|||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -68,19 +68,6 @@ SECTIONS
|
|||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/yosemite/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -68,19 +68,6 @@ SECTIONS
|
|||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/yucca/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
|
|||
|
|
@ -1,146 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/amcc/yucca/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* common/environment.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -27,29 +27,17 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
#include <asm-ppc/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/4xx_pcie.h>
|
||||
|
||||
#include "yucca.h"
|
||||
#include "../cpu/ppc4xx/440spe_pcie.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#undef PCIE_ENDPOINT
|
||||
/* #define PCIE_ENDPOINT 1 */
|
||||
|
||||
void fpga_init (void);
|
||||
|
||||
void get_sys_info(PPC440_SYS_INFO *board_cfg );
|
||||
int compare_to_true(char *str );
|
||||
char *remove_l_w_space(char *in_str );
|
||||
char *remove_t_w_space(char *in_str );
|
||||
int get_console_port(void);
|
||||
|
||||
int ppc440spe_init_pcie_rootport(int port);
|
||||
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
|
||||
|
||||
#define DEBUG_ENV
|
||||
#ifdef DEBUG_ENV
|
||||
#define DEBUGF(fmt,args...) printf(fmt ,##args)
|
||||
|
|
@ -541,10 +529,10 @@ int board_early_init_f (void)
|
|||
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
|
||||
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
|
||||
|
||||
/* SDR0_MFR should be part of Ethernet init */
|
||||
mfsdr (sdr_mfr, mfr);
|
||||
mfr &= ~SDR0_MFR_ECS_MASK;
|
||||
/*mtsdr(sdr_mfr, mfr);*/
|
||||
mfsdr(sdr_mfr, mfr);
|
||||
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
|
||||
mtsdr(sdr_mfr, mfr);
|
||||
|
||||
fpga_init();
|
||||
|
||||
return 0;
|
||||
|
|
@ -850,6 +838,7 @@ void pcie_setup_hoses(int busno)
|
|||
{
|
||||
struct pci_controller *hose;
|
||||
int i, bus;
|
||||
int ret = 0;
|
||||
char *env;
|
||||
unsigned int delay;
|
||||
|
||||
|
|
@ -863,14 +852,16 @@ void pcie_setup_hoses(int busno)
|
|||
if (!yucca_pcie_card_present(i))
|
||||
continue;
|
||||
|
||||
#ifdef PCIE_ENDPOINT
|
||||
yucca_setup_pcie_fpga_endpoint(i);
|
||||
if (ppc440spe_init_pcie_endport(i)) {
|
||||
#else
|
||||
yucca_setup_pcie_fpga_rootpoint(i);
|
||||
if (ppc440spe_init_pcie_rootport(i)) {
|
||||
#endif
|
||||
printf("PCIE%d: initialization failed\n", i);
|
||||
if (is_end_point(i)) {
|
||||
yucca_setup_pcie_fpga_endpoint(i);
|
||||
ret = ppc4xx_init_pcie_endport(i);
|
||||
} else {
|
||||
yucca_setup_pcie_fpga_rootpoint(i);
|
||||
ret = ppc4xx_init_pcie_rootport(i);
|
||||
}
|
||||
if (ret) {
|
||||
printf("PCIE%d: initialization as %s failed\n", i,
|
||||
is_end_point(i) ? "endpoint" : "root-complex");
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -884,35 +875,33 @@ void pcie_setup_hoses(int busno)
|
|||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
||||
CFG_PCIE_MEMSIZE,
|
||||
PCI_REGION_MEM
|
||||
);
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count = 1;
|
||||
pci_register_hose(hose);
|
||||
|
||||
#ifdef PCIE_ENDPOINT
|
||||
ppc440spe_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
#else
|
||||
ppc440spe_setup_pcie_rootpoint(hose, i);
|
||||
if (is_end_point(i)) {
|
||||
ppc4xx_setup_pcie_endpoint(hose, i);
|
||||
/*
|
||||
* Reson for no scanning is endpoint can not generate
|
||||
* upstream configuration accesses.
|
||||
*/
|
||||
} else {
|
||||
ppc4xx_setup_pcie_rootpoint(hose, i);
|
||||
env = getenv("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul(env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf("Warning, expect noticable delay before "
|
||||
"PCIe scan due to 'pciscandelay' value!\n");
|
||||
mdelay(delay * 1000);
|
||||
}
|
||||
|
||||
env = getenv ("pciscandelay");
|
||||
if (env != NULL) {
|
||||
delay = simple_strtoul (env, NULL, 10);
|
||||
if (delay > 5)
|
||||
printf ("Warning, expect noticable delay before PCIe"
|
||||
"scan due to 'pciscandelay' value!\n");
|
||||
mdelay (delay * 1000);
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Config access can only go down stream
|
||||
*/
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
bus = hose->last_busno + 1;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ SECTIONS
|
|||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
48
board/apollon/Makefile
Normal file
48
board/apollon/Makefile
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := apollon.o mem.o sys_info.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
472
board/apollon/apollon.c
Normal file
472
board/apollon/apollon.c
Normal file
|
|
@ -0,0 +1,472 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2007
|
||||
* Samsung Electronics.
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
*
|
||||
* Derived from omap2420
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/arch/omap2420.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
void wait_for_command_complete(unsigned int wd_base);
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define write_config_reg(reg, value) \
|
||||
do { \
|
||||
writeb(value, reg); \
|
||||
} while (0)
|
||||
|
||||
#define mask_config_reg(reg, mask) \
|
||||
do { \
|
||||
char value = readb(reg) & ~(mask); \
|
||||
writeb(value, reg); \
|
||||
} while (0)
|
||||
|
||||
/*******************************************************
|
||||
* Routine: delay
|
||||
* Description: spinning delay to use before udelay works
|
||||
******************************************************/
|
||||
static inline void delay(unsigned long loops)
|
||||
{
|
||||
__asm__("1:\n" "subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0"(loops));
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
|
||||
|
||||
gd->bd->bi_arch_number = 919;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* Routine: s_init
|
||||
* Description: Does early system init of muxing and clocks.
|
||||
* - Called path is with sram stack.
|
||||
**********************************************************/
|
||||
void s_init(void)
|
||||
{
|
||||
watchdog_init();
|
||||
set_muxconf_regs();
|
||||
delay(100);
|
||||
|
||||
peripheral_enable();
|
||||
icache_enable();
|
||||
}
|
||||
|
||||
/*******************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Init ethernet (done here so udelay works)
|
||||
********************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
ether_init(); /* better done here so timers are init'ed */
|
||||
return (0);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: watchdog_init
|
||||
* Description: Shut down watch dogs
|
||||
*****************************************/
|
||||
void watchdog_init(void)
|
||||
{
|
||||
/* There are 4 watch dogs. 1 secure, and 3 general purpose.
|
||||
* The ROM takes care of the secure one. Of the 3 GP ones,
|
||||
* 1 can reset us directly, the other 2 only generate MPU interrupts.
|
||||
*/
|
||||
__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
|
||||
wait_for_command_complete(WD2_BASE);
|
||||
__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
|
||||
|
||||
#define MPU_WD_CLOCKED 1
|
||||
#if MPU_WD_CLOCKED
|
||||
/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
|
||||
__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
|
||||
wait_for_command_complete(WD3_BASE);
|
||||
__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
|
||||
|
||||
__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
|
||||
wait_for_command_complete(WD4_BASE);
|
||||
__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
|
||||
#endif
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
* Routine: wait_for_command_complete
|
||||
* Description: Wait for posting to finish on watchdog
|
||||
******************************************************/
|
||||
void wait_for_command_complete(unsigned int wd_base)
|
||||
{
|
||||
int pending = 1;
|
||||
do {
|
||||
pending = __raw_readl(wd_base + WWPS);
|
||||
} while (pending);
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* Routine:ether_init
|
||||
* Description: take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete.
|
||||
******************************************************************/
|
||||
void ether_init(void)
|
||||
{
|
||||
#ifdef CONFIG_DRIVER_LAN91C96
|
||||
int cnt = 20;
|
||||
|
||||
__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
|
||||
|
||||
__raw_writew(0x0, LAN_RESET_REGISTER);
|
||||
do {
|
||||
__raw_writew(0x1, LAN_RESET_REGISTER);
|
||||
udelay(100);
|
||||
if (cnt == 0) {
|
||||
printf("1. eth reset err\n");
|
||||
goto eth_reset_err_out;
|
||||
}
|
||||
--cnt;
|
||||
} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
|
||||
|
||||
cnt = 20;
|
||||
|
||||
do {
|
||||
__raw_writew(0x0, LAN_RESET_REGISTER);
|
||||
udelay(100);
|
||||
if (cnt == 0) {
|
||||
printf("2. eth reset err\n");
|
||||
goto eth_reset_err_out;
|
||||
}
|
||||
--cnt;
|
||||
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
|
||||
udelay(1000);
|
||||
|
||||
mask_config_reg(ETH_CONTROL_REG, 0x01);
|
||||
udelay(1000);
|
||||
|
||||
eth_reset_err_out:
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* Routine: dram_init
|
||||
* Description: sets uboots idea of sdram size
|
||||
**********************************************/
|
||||
int dram_init(void)
|
||||
{
|
||||
unsigned int size0 = 0, size1 = 0;
|
||||
u32 mtype, btype, rev = 0, cpu = 0;
|
||||
#define NOT_EARLY 0
|
||||
|
||||
btype = get_board_type();
|
||||
mtype = get_mem_type();
|
||||
rev = get_cpu_rev();
|
||||
cpu = get_cpu_type();
|
||||
|
||||
display_board_info(btype);
|
||||
|
||||
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
|
||||
/* init other chip select */
|
||||
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
|
||||
}
|
||||
|
||||
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
|
||||
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = size0;
|
||||
#if CONFIG_NR_DRAM_BANKS > 1
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
|
||||
gd->bd->bi_dram[1].size = size1;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers
|
||||
* specific to the hardware
|
||||
*********************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
muxSetupSDRC();
|
||||
muxSetupGPMC();
|
||||
muxSetupUsb0(); /* USB Device */
|
||||
muxSetupUsbHost(); /* USB Host */
|
||||
muxSetupUART1();
|
||||
muxSetupLCD();
|
||||
muxSetupMMCSD();
|
||||
muxSetupTouchScreen();
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* Routine: peripheral_enable
|
||||
* Description: Enable the clks & power for perifs (GPT2, UART1,...)
|
||||
******************************************************************/
|
||||
void peripheral_enable(void)
|
||||
{
|
||||
unsigned int v, if_clks = 0, func_clks = 0;
|
||||
|
||||
/* Enable GP2 timer. */
|
||||
if_clks |= BIT4 | BIT3;
|
||||
func_clks |= BIT4 | BIT3;
|
||||
/* Sys_clk input OMAP2420_GPT2 */
|
||||
v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
|
||||
__raw_writel(v, CM_CLKSEL2_CORE);
|
||||
__raw_writel(0x1, CM_CLKSEL_WKUP);
|
||||
|
||||
#ifdef CFG_NS16550
|
||||
/* Enable UART1 clock */
|
||||
func_clks |= BIT21;
|
||||
if_clks |= BIT21;
|
||||
#endif
|
||||
/* Interface clocks on */
|
||||
v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
|
||||
__raw_writel(v, CM_ICLKEN1_CORE);
|
||||
/* Functional Clocks on */
|
||||
v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
|
||||
__raw_writel(v, CM_FCLKEN1_CORE);
|
||||
delay(1000);
|
||||
|
||||
#ifndef KERNEL_UPDATED
|
||||
{
|
||||
#define V1 0xffffffff
|
||||
#define V2 0x00000007
|
||||
|
||||
__raw_writel(V1, CM_FCLKEN1_CORE);
|
||||
__raw_writel(V2, CM_FCLKEN2_CORE);
|
||||
__raw_writel(V1, CM_ICLKEN1_CORE);
|
||||
__raw_writel(V1, CM_ICLKEN2_CORE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupUsb0 (ostboot)
|
||||
* Description: Setup usb muxing
|
||||
*****************************************/
|
||||
void muxSetupUsb0(void)
|
||||
{
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
|
||||
mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupUSBHost (ostboot)
|
||||
* Description: Setup USB Host muxing
|
||||
*****************************************/
|
||||
void muxSetupUsbHost(void)
|
||||
{
|
||||
/* V19 */
|
||||
write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
|
||||
/* W20 */
|
||||
write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
|
||||
/* N14 */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO69, 3);
|
||||
/* P15 */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO70, 3);
|
||||
/* L18 */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO102, 3);
|
||||
/* L19 */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO103, 3);
|
||||
/* K15 */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO104, 3);
|
||||
/* K14 */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO105, 3);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupUART1 (ostboot)
|
||||
* Description: Set up uart1 muxing
|
||||
*****************************************/
|
||||
void muxSetupUART1(void)
|
||||
{
|
||||
/* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
|
||||
/* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
|
||||
/* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
|
||||
/* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupLCD (ostboot)
|
||||
* Description: Setup lcd muxing
|
||||
*****************************************/
|
||||
void muxSetupLCD(void)
|
||||
{
|
||||
/* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
|
||||
/* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
|
||||
/* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
|
||||
/* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
|
||||
/* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
|
||||
/* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
|
||||
/* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
|
||||
/* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
|
||||
/* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
|
||||
/* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
|
||||
/* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
|
||||
/* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
|
||||
/* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
|
||||
/* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
|
||||
/* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
|
||||
/* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
|
||||
/* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
|
||||
/* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
|
||||
/* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
|
||||
/* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
|
||||
/* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
|
||||
/* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupMMCSD (ostboot)
|
||||
* Description: set up MMC muxing
|
||||
*****************************************/
|
||||
void muxSetupMMCSD(void)
|
||||
{
|
||||
/* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
|
||||
/* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
|
||||
/* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
|
||||
/* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
|
||||
/* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
|
||||
/* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
|
||||
/* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
|
||||
/* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
|
||||
/* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
|
||||
/* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
|
||||
/* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
|
||||
/* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
|
||||
}
|
||||
|
||||
/******************************************
|
||||
* Routine: muxSetupTouchScreen (ostboot)
|
||||
* Description: Set up touch screen muxing
|
||||
*******************************************/
|
||||
void muxSetupTouchScreen(void)
|
||||
{
|
||||
/* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
|
||||
/* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
|
||||
/* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
|
||||
/* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
|
||||
#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
|
||||
/* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
|
||||
write_config_reg(CONTROL_PADCONF_GPIO85, 3);
|
||||
}
|
||||
|
||||
/***************************************************************
|
||||
* Routine: muxSetupGPMC (ostboot)
|
||||
* Description: Configures balls which cam up in protected mode
|
||||
***************************************************************/
|
||||
void muxSetupGPMC(void)
|
||||
{
|
||||
/* gpmc_io_dir, MCR */
|
||||
writel(0x4800008C, 0x19000000);
|
||||
|
||||
/* NOR FLASH CS0 */
|
||||
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
|
||||
/* MPDB(Multi Port Debug Port) CS1 */
|
||||
/* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
|
||||
/* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
|
||||
/* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
|
||||
/* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
|
||||
/* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
|
||||
/* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
|
||||
/* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
|
||||
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
|
||||
}
|
||||
|
||||
/****************************************************************
|
||||
* Routine: muxSetupSDRC (ostboot)
|
||||
* Description: Configures balls which come up in protected mode
|
||||
****************************************************************/
|
||||
void muxSetupSDRC(void)
|
||||
{
|
||||
/* It's set by IPL */
|
||||
}
|
||||
25
board/apollon/config.mk
Normal file
25
board/apollon/config.mk
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2005-2007
|
||||
# Samsung Electronics
|
||||
#
|
||||
# Samsung December board with OMAP2420 (ARM1136) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# December has 1 bank of 128MB mDDR-SDRAM on CS0
|
||||
# December has 1 bank of 00MB mDDR-SDRAM on CS1
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1) ES2 will be configurable
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
||||
|
||||
# Used with full SRAM boot.
|
||||
# This is either with a GP system or a signed boot image.
|
||||
# easiest, and safest way to go if you can.
|
||||
#TEXT_BASE = 0x40270000
|
||||
|
||||
# Handy to get symbols to debug ROM version.
|
||||
#TEXT_BASE = 0x0
|
||||
#TEXT_BASE = 0x08000000
|
||||
337
board/apollon/lowlevel_init.S
Normal file
337
board/apollon/lowlevel_init.S
Normal file
|
|
@ -0,0 +1,337 @@
|
|||
/*
|
||||
* Board specific setup info
|
||||
*
|
||||
* (C) Copyright 2005-2007
|
||||
* Samsung Electronics,
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/omap2420.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include "mem.h"
|
||||
|
||||
#define APOLLON_CS0_BASE 0x00000000
|
||||
|
||||
#ifdef PRCM_CONFIG_I
|
||||
#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
|
||||
#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
|
||||
#define SDRC_RFR_CTRL_0_VAL 0x00044C01
|
||||
#elif defined(PRCM_CONFIG_II)
|
||||
#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
|
||||
#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
|
||||
#define SDRC_RFR_CTRL_0_VAL 0x00030001
|
||||
#endif
|
||||
|
||||
#define SDRAM_BASE_ADDRESS 0x80008000
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE /* sdram load addr from config.mk */
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
#ifdef CFG_NOR_BOOT
|
||||
/* Check running in SDRAM */
|
||||
mov r0, pc, lsr #28
|
||||
cmp r0, #8
|
||||
beq prcm_setup
|
||||
|
||||
flash_setup:
|
||||
/* In Flash */
|
||||
ldr r0, =WD2_BASE
|
||||
ldr r1, =WD_UNLOCK1
|
||||
str r1, [r0, #WSPR]
|
||||
|
||||
ldr r1, =WD_UNLOCK2
|
||||
str r1, [r0, #WSPR]
|
||||
|
||||
/* Pin muxing for SDRC */
|
||||
mov r1, #0x00
|
||||
ldr r0, =0x480000A1 /* ball C12, mode 0 */
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x48000032 /* ball D11, mode 0 */
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x480000A3 /* ball B13, mode 0 */
|
||||
strb r1, [r0]
|
||||
|
||||
/* SDRC setting */
|
||||
ldr r0, =OMAP2420_SDRC_BASE
|
||||
ldr r1, =0x00000010
|
||||
str r1, [r0, #0x10]
|
||||
|
||||
ldr r1, =0x00000100
|
||||
str r1, [r0, #0x44]
|
||||
|
||||
/* SDRC CS0 configuration */
|
||||
ldr r1, =0x00d04011
|
||||
str r1, [r0, #0x80]
|
||||
|
||||
ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
|
||||
str r1, [r0, #0x9C]
|
||||
|
||||
ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
|
||||
str r1, [r0, #0xA0]
|
||||
|
||||
ldr r1, =SDRC_RFR_CTRL_0_VAL
|
||||
str r1, [r0, #0xA4]
|
||||
|
||||
ldr r1, =0x00000041
|
||||
str r1, [r0, #0x70]
|
||||
|
||||
/* Manual command sequence */
|
||||
ldr r1, =0x00000007
|
||||
str r1, [r0, #0xA8]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0xA8]
|
||||
|
||||
ldr r1, =0x00000001
|
||||
str r1, [r0, #0xA8]
|
||||
|
||||
ldr r1, =0x00000002
|
||||
str r1, [r0, #0xA8]
|
||||
str r1, [r0, #0xA8]
|
||||
|
||||
/*
|
||||
* CS0 SDRC Mode register
|
||||
* Burst length = 4 - DDR memory
|
||||
* Serial mode
|
||||
* CAS latency = 3
|
||||
*/
|
||||
ldr r1, =0x00000032
|
||||
str r1, [r0, #0x84]
|
||||
|
||||
/* Note: You MUST set EMR values */
|
||||
/* EMR1 & EMR2 */
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x88]
|
||||
str r1, [r0, #0x8C]
|
||||
|
||||
#ifdef OLD_SDRC_DLLA_CTRL
|
||||
/* SDRC_DLLA_CTRL */
|
||||
ldr r1, =0x00007306
|
||||
str r1, [r0, #0x60]
|
||||
|
||||
ldr r1, =0x00007303
|
||||
str r1, [r0, #0x60]
|
||||
#else
|
||||
/* SDRC_DLLA_CTRL */
|
||||
ldr r1, =0x00000506
|
||||
str r1, [r0, #0x60]
|
||||
|
||||
ldr r1, =0x00000503
|
||||
str r1, [r0, #0x60]
|
||||
#endif
|
||||
|
||||
#ifdef __BROKEN_FEATURE__
|
||||
/* SDRC_DLLB_CTRL */
|
||||
ldr r1, =0x00000506
|
||||
str r1, [r0, #0x68]
|
||||
|
||||
ldr r1, =0x00000503
|
||||
str r1, [r0, #0x68]
|
||||
#endif
|
||||
|
||||
/* little delay after init */
|
||||
mov r2, #0x1800
|
||||
1:
|
||||
subs r2, r2, #0x1
|
||||
bne 1b
|
||||
|
||||
/* Setup base address */
|
||||
ldr r0, =0x00000000 /* NOR address */
|
||||
ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
|
||||
ldr r2, =0x20000 /* Size: 128KB */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10}
|
||||
stmia r1!, {r3-r10}
|
||||
cmp r0, r2
|
||||
ble copy_loop
|
||||
|
||||
ldr r1, =SDRAM_BASE_ADDRESS
|
||||
mov lr, pc
|
||||
mov pc, r1
|
||||
#endif
|
||||
|
||||
prcm_setup:
|
||||
ldr r0, =OMAP2420_CM_BASE
|
||||
ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
|
||||
bic r1, r1, #0x03
|
||||
orr r1, r1, #0x02
|
||||
str r1, [r0, #0x544]
|
||||
|
||||
ldr r1, [r0, #0x500]
|
||||
bic r1, r1, #0x03
|
||||
orr r1, r1, #0x01
|
||||
str r1, [r0, #0x500]
|
||||
|
||||
ldr r1, [r0, #0x140]
|
||||
bic r1, r1, #0x1f
|
||||
orr r1, r1, #0x02
|
||||
str r1, [r0, #0x140]
|
||||
|
||||
#ifdef PRCM_CONFIG_I
|
||||
ldr r1, =0x000003C3
|
||||
#else
|
||||
ldr r1, =0x00000343
|
||||
#endif
|
||||
str r1, [r0, #0x840]
|
||||
|
||||
ldr r1, =0x00000002
|
||||
str r1, [r0, #0x340]
|
||||
|
||||
ldr r1, =CM_CLKSEL1_CORE
|
||||
#ifdef PRCM_CONFIG_I
|
||||
ldr r2, =0x08300C44
|
||||
#else
|
||||
ldr r2, =0x04600C26
|
||||
#endif
|
||||
str r2, [r1]
|
||||
|
||||
ldr r0, =OMAP2420_CM_BASE
|
||||
ldr r1, [r0, #0x084]
|
||||
and r1, r1, #0x01
|
||||
cmp r1, #0x01
|
||||
bne clkvalid
|
||||
|
||||
b .
|
||||
|
||||
clkvalid:
|
||||
mov r1, #0x01
|
||||
str r1, [r0, #0x080]
|
||||
|
||||
waitvalid:
|
||||
ldr r1, [r0, #0x084]
|
||||
and r1, r1, #0x01
|
||||
cmp r1, #0x00
|
||||
bne waitvalid
|
||||
|
||||
ldr r0, =CM_CLKSEL1_PLL
|
||||
#ifdef PRCM_CONFIG_I
|
||||
ldr r1, =0x01837100
|
||||
#else
|
||||
ldr r1, =0x01832100
|
||||
#endif
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =PRCM_CLKCFG_CTRL
|
||||
mov r1, #0x01
|
||||
str r1, [r0]
|
||||
mov r6, #0x50
|
||||
loop1:
|
||||
subs r6, r6, #0x01
|
||||
cmp r6, #0x01
|
||||
bne loop1
|
||||
|
||||
ldr r0, =CM_CLKEN_PLL
|
||||
mov r1, #0x0f
|
||||
str r1, [r0]
|
||||
|
||||
mov r6, #0x100
|
||||
loop2:
|
||||
subs r6, r6, #0x01
|
||||
cmp r6, #0x01
|
||||
bne loop2
|
||||
|
||||
ldr r0, =0x48008200
|
||||
ldr r1, =0xbfffffff
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x48008210
|
||||
ldr r1, =0xfffffff9
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a004
|
||||
ldr r1, =0x00
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a020
|
||||
ldr r1, =0x07
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a00c
|
||||
ldr r1, =0x83
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a000
|
||||
ldr r1, =0x1a
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a004
|
||||
ldr r1, =0x00
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a00c
|
||||
ldr r1, =0x03
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a010
|
||||
ldr r1, =0x03
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a008
|
||||
ldr r1, =0x04
|
||||
strb r1, [r0]
|
||||
|
||||
ldr r0, =0x4806a020
|
||||
ldr r1, =0x00
|
||||
strb r1, [r0]
|
||||
|
||||
#if 0
|
||||
ldr r0, =0x4806a000
|
||||
mov r1, #'u'
|
||||
strb r1, [r0]
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* LED0 OFF */
|
||||
ldr r3, =0x480000E5
|
||||
mov r4, #0x0b
|
||||
strb r4, [r3]
|
||||
#endif
|
||||
|
||||
ldr sp, SRAM_STACK
|
||||
str ip, [sp] /* stash old link register */
|
||||
mov ip, lr /* save link reg across call */
|
||||
bl s_init /* go setup pll,mux,memory */
|
||||
ldr ip, [sp] /* restore save ip */
|
||||
mov lr, ip /* restore link reg */
|
||||
|
||||
/* map interrupt controller */
|
||||
ldr r0, VAL_INTH_SETUP
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
|
||||
/* back to arch calling code */
|
||||
mov pc, lr
|
||||
|
||||
/* the literal pools origin */
|
||||
.ltorg
|
||||
|
||||
VAL_INTH_SETUP:
|
||||
.word PERIFERAL_PORT_BASE
|
||||
SRAM_STACK:
|
||||
.word LOW_LEVEL_SRAM_STACK
|
||||
235
board/apollon/mem.c
Normal file
235
board/apollon/mem.c
Normal file
|
|
@ -0,0 +1,235 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2007
|
||||
* Samsung Electronics,
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
*
|
||||
* Derived from omap2420
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/omap2420.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
|
||||
#include "mem.h"
|
||||
|
||||
/************************************************************
|
||||
* sdelay() - simple spin loop. Will be constant time as
|
||||
* its generally used in 12MHz bypass conditions only. This
|
||||
* is necessary until timers are accessible.
|
||||
*
|
||||
* not inline to increase chances its in cache when called
|
||||
*************************************************************/
|
||||
void sdelay(unsigned long loops)
|
||||
{
|
||||
__asm__("1:\n" "subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0"(loops));
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* prcm_init() - inits clocks for PRCM as defined in clocks.h
|
||||
* (config II default).
|
||||
* -- called from SRAM, or Flash (using temp SRAM stack).
|
||||
********************************************************************/
|
||||
void prcm_init(void) { }
|
||||
|
||||
/**************************************************************************
|
||||
* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
|
||||
* command line mem=xyz use all memory with out discontigious support
|
||||
* compiled in. Could do it at the ATAG, but there really is two banks...
|
||||
* Called as part of 2nd phase DDR init.
|
||||
**************************************************************************/
|
||||
void make_cs1_contiguous(void)
|
||||
{
|
||||
u32 size, a_add_low, a_add_high;
|
||||
|
||||
size = get_sdr_cs_size(SDRC_CS0_OSET);
|
||||
size /= SZ_32M; /* find size to offset CS1 */
|
||||
a_add_high = (size & 3) << 8; /* set up low field */
|
||||
a_add_low = (size & 0x3C) >> 2; /* set up high field */
|
||||
__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
|
||||
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* mem_ok() - test used to see if timings are correct
|
||||
* for a part. Helps in gussing which part
|
||||
* we are currently using.
|
||||
*******************************************************/
|
||||
u32 mem_ok(void)
|
||||
{
|
||||
u32 val1, val2;
|
||||
u32 pattern = 0x12345678;
|
||||
|
||||
/* clear pos A */
|
||||
__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
|
||||
/* pattern to pos B */
|
||||
__raw_writel(pattern, OMAP2420_SDRC_CS0);
|
||||
/* remove pattern off the bus */
|
||||
__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
|
||||
/* get pos A value */
|
||||
val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
|
||||
val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
|
||||
|
||||
/* see if pos A value changed */
|
||||
if ((val1 != 0) || (val2 != pattern))
|
||||
return (0);
|
||||
else
|
||||
return (1);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* sdrc_init() - init the sdrc chip selects CS0 and CS1
|
||||
* - early init routines, called from flash or
|
||||
* SRAM.
|
||||
*******************************************************/
|
||||
void sdrc_init(void)
|
||||
{
|
||||
#define EARLY_INIT 1
|
||||
/* only init up first bank here */
|
||||
do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* do_sdrc_init(): initialize the SDRAM for use.
|
||||
* -called from low level code with stack only.
|
||||
* -code sets up SDRAM timing and muxing for 2422 or 2420.
|
||||
* -optimal settings can be placed here, or redone after i2c
|
||||
* inspection of board info
|
||||
*
|
||||
* This is a bit ugly, but should handle all memory moduels
|
||||
* used with the APOLLON. The first time though this code from s_init()
|
||||
* we configure the first chip select. Later on we come back and
|
||||
* will configure the 2nd chip select if it exists.
|
||||
*
|
||||
**************************************************************************/
|
||||
void do_sdrc_init(u32 offset, u32 early)
|
||||
{
|
||||
}
|
||||
|
||||
/*****************************************************
|
||||
* gpmc_init(): init gpmc bus
|
||||
* Init GPMC for x16, MuxMode (SDRAM in x32).
|
||||
* This code can only be executed from SRAM or SDRAM.
|
||||
*****************************************************/
|
||||
void gpmc_init(void)
|
||||
{
|
||||
u32 mux = 0, mtype, mwidth, rev, tval;
|
||||
|
||||
rev = get_cpu_rev();
|
||||
if (rev == CPU_2420_2422_ES1)
|
||||
tval = 1;
|
||||
else
|
||||
tval = 0; /* disable bit switched meaning */
|
||||
|
||||
/* global settings */
|
||||
__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
|
||||
__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
|
||||
__raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
|
||||
#ifdef CFG_NAND_BOOT
|
||||
/* set nWP, disable limited addr */
|
||||
__raw_writel(0x001, GPMC_CONFIG);
|
||||
#else
|
||||
/* set nWP, disable limited addr */
|
||||
__raw_writel(0x111, GPMC_CONFIG);
|
||||
#endif
|
||||
|
||||
/* discover bus connection from sysboot */
|
||||
if (is_gpmc_muxed() == GPMC_MUXED)
|
||||
mux = BIT9;
|
||||
mtype = get_gpmc0_type();
|
||||
mwidth = get_gpmc0_width();
|
||||
|
||||
/* setup cs0 */
|
||||
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
|
||||
sdelay(1000);
|
||||
|
||||
#ifdef CFG_NOR_BOOT
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
|
||||
#else
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
|
||||
GPMC_CONFIG1_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
|
||||
#endif
|
||||
sdelay(2000);
|
||||
|
||||
/* setup cs1 */
|
||||
__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
|
||||
sdelay(1000);
|
||||
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
|
||||
sdelay(2000);
|
||||
|
||||
/* setup cs2 */
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
|
||||
GPMC_CONFIG1_2);
|
||||
/* It's same as cs 0 */
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
|
||||
#ifdef CFG_NOR_BOOT
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
|
||||
#else
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
|
||||
#endif
|
||||
|
||||
#ifndef CFG_NOR_BOOT
|
||||
/* setup cs3 */
|
||||
__raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
|
||||
sdelay(1000);
|
||||
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
|
||||
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
|
||||
#endif
|
||||
|
||||
#ifndef ASYNC_NOR
|
||||
__raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
|
||||
__raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
|
||||
__raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
|
||||
#endif
|
||||
sdelay(2000);
|
||||
}
|
||||
170
board/apollon/mem.h
Normal file
170
board/apollon/mem.h
Normal file
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2007
|
||||
* Samsung Electronics,
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _APOLLON_OMAP24XX_MEM_H_
|
||||
#define _APOLLON_OMAP24XX_MEM_H_
|
||||
|
||||
/* Slower full frequency range default timings for x32 operation*/
|
||||
#define APOLLON_2420_SDRC_SHARING 0x00000100
|
||||
#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
|
||||
#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
|
||||
|
||||
/* optimized timings good for current shipping parts */
|
||||
#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
|
||||
#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
|
||||
|
||||
#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
|
||||
#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
|
||||
|
||||
#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
|
||||
#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
|
||||
|
||||
#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
|
||||
#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
|
||||
|
||||
#ifdef PRCM_CONFIG_I
|
||||
#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
|
||||
#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
|
||||
#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
|
||||
#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
|
||||
#elif PRCM_CONFIG_II
|
||||
#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
|
||||
#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
|
||||
#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
|
||||
#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
|
||||
#endif
|
||||
|
||||
/* GPMC settings */
|
||||
#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
|
||||
/* CS0: OneNAND */
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
|
||||
|
||||
/* CS1: Ethernet */
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
|
||||
|
||||
/* CS2: OneNAND */
|
||||
/* It's same as CS0 */
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
|
||||
|
||||
/* CS3: NOR */
|
||||
#ifdef ASYNC_NOR
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
|
||||
#else
|
||||
# define SYNC_NOR_VALUE 0x24aaa
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
|
||||
#endif /* ASYNC_NOR */
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
|
||||
#endif /* endif PRCM_CONFIG_I */
|
||||
|
||||
#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
|
||||
/* CS0: OneNAND */
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
|
||||
|
||||
/* CS1: ethernet */
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
|
||||
|
||||
/* CS2: OneNAND */
|
||||
/* It's same as CS0 */
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
|
||||
|
||||
/* CS3: NOR */
|
||||
#define ASYNC_NOR
|
||||
#ifdef ASYNC_NOR
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
|
||||
#else
|
||||
# define SYNC_NOR_VALUE 0x24aaa
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
|
||||
#endif /* ASYNC_NOR */
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
|
||||
#endif /* endif PRCM_CONFIG_II */
|
||||
|
||||
#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
|
||||
# ifdef CFG_NAND_BOOT
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
|
||||
# else /* NOR boot */
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
|
||||
# endif /* endif CFG_NAND_BOOT */
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
|
||||
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
|
||||
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
|
||||
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
|
||||
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
|
||||
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
|
||||
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
|
||||
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
|
||||
#endif /* endif CFG_PRCM_III */
|
||||
|
||||
#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
|
||||
403
board/apollon/sys_info.c
Normal file
403
board/apollon/sys_info.c
Normal file
|
|
@ -0,0 +1,403 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2007
|
||||
* Samsung Electronics,
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
*
|
||||
* Derived from omap2420
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/omap2420.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mem.h> /* get mem tables */
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
#include <i2c.h>
|
||||
|
||||
/**************************************************************************
|
||||
* get_prod_id() - get id info from chips
|
||||
***************************************************************************/
|
||||
static u32 get_prod_id(void)
|
||||
{
|
||||
u32 p;
|
||||
p = __raw_readl(PRODUCTION_ID); /* get production ID */
|
||||
return ((p & CPU_242X_PID_MASK) >> 16);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* get_cpu_type() - low level get cpu type
|
||||
* - no C globals yet.
|
||||
* - just looking to say if this is a 2422 or 2420 or ...
|
||||
* - to start with we will look at switch settings..
|
||||
* - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
|
||||
* (mux for 2420, non-mux for 2422).
|
||||
***************************************************************************/
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
switch (get_prod_id()) {
|
||||
case 1:; /* 2420 */
|
||||
case 2:
|
||||
return (CPU_2420);
|
||||
break; /* 2420 pop */
|
||||
case 4:
|
||||
return (CPU_2422);
|
||||
break;
|
||||
case 8:
|
||||
return (CPU_2423);
|
||||
break;
|
||||
default:
|
||||
break; /* early 2420/2422's unmarked */
|
||||
}
|
||||
|
||||
v = __raw_readl(TAP_IDCODE_REG);
|
||||
v &= CPU_24XX_ID_MASK;
|
||||
/* currently 2420 and 2422 have same id */
|
||||
if (v == CPU_2420_CHIPID) {
|
||||
if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
|
||||
return (CPU_2420);
|
||||
else
|
||||
return (CPU_2422);
|
||||
} else
|
||||
return (CPU_2420); /* don't know, say 2420 */
|
||||
}
|
||||
|
||||
/******************************************
|
||||
* get_cpu_rev(void) - extract version info
|
||||
******************************************/
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
u32 v;
|
||||
v = __raw_readl(TAP_IDCODE_REG);
|
||||
v = v >> 28;
|
||||
return (v + 1); /* currently 2422 and 2420 match up */
|
||||
}
|
||||
|
||||
/****************************************************
|
||||
* is_mem_sdr() - return 1 if mem type in use is SDR
|
||||
****************************************************/
|
||||
u32 is_mem_sdr(void)
|
||||
{
|
||||
volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
|
||||
if (*burst == H4_2420_SDRC_MR_0_SDR)
|
||||
return (1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/***********************************************************
|
||||
* get_mem_type() - identify type of mDDR part used.
|
||||
* 2422 uses stacked DDR, 2 parts CS0/CS1.
|
||||
* 2420 may have 1 or 2, no good way to know...only init 1...
|
||||
* when eeprom data is up we can select 1 more.
|
||||
*************************************************************/
|
||||
u32 get_mem_type(void)
|
||||
{
|
||||
u32 cpu, sdr = is_mem_sdr();
|
||||
|
||||
cpu = get_cpu_type();
|
||||
if (cpu == CPU_2422 || cpu == CPU_2423)
|
||||
return (DDR_STACKED);
|
||||
|
||||
if (get_prod_id() == 0x2)
|
||||
return (XDR_POP);
|
||||
|
||||
if (get_board_type() == BOARD_H4_MENELAUS)
|
||||
if (sdr)
|
||||
return (SDR_DISCRETE);
|
||||
else
|
||||
return (DDR_COMBO);
|
||||
else if (sdr) /* SDP + SDR kit */
|
||||
return (SDR_DISCRETE);
|
||||
else
|
||||
return (DDR_DISCRETE); /* origional SDP */
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_cs0_size() - get size of chip select 0/1
|
||||
************************************************************************/
|
||||
u32 get_sdr_cs_size(u32 offset)
|
||||
{
|
||||
u32 size;
|
||||
size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */
|
||||
size &= 0x2FF; /* remove unwanted bits */
|
||||
size *= SZ_2M; /* find size in MB */
|
||||
return (size);
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_board_type() - get board type based on current production stats.
|
||||
* --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
|
||||
* when they are available we can get info from there. This should
|
||||
* be correct of all known boards up until today.
|
||||
************************************************************************/
|
||||
u32 get_board_type(void)
|
||||
{
|
||||
return (BOARD_H4_SDP);
|
||||
}
|
||||
|
||||
/******************************************************************
|
||||
* get_sysboot_value() - get init word settings (dip switch on h4)
|
||||
******************************************************************/
|
||||
inline u32 get_sysboot_value(void)
|
||||
{
|
||||
return (0x00000FFF & __raw_readl(CONTROL_STATUS));
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* get_gpmc0_base() - Return current address hardware will be
|
||||
* fetching from. The below effectively gives what is correct, its a bit
|
||||
* mis-leading compared to the TRM. For the most general case the mask
|
||||
* needs to be also taken into account this does work in practice.
|
||||
* - for u-boot we currently map:
|
||||
* -- 0 to nothing,
|
||||
* -- 4 to flash
|
||||
* -- 8 to enent
|
||||
* -- c to wifi
|
||||
****************************************************************************/
|
||||
u32 get_gpmc0_base(void)
|
||||
{
|
||||
u32 b;
|
||||
|
||||
b = __raw_readl(GPMC_CONFIG7_0);
|
||||
b &= 0x1F; /* keep base [5:0] */
|
||||
b = b << 24; /* ret 0x0b000000 */
|
||||
return (b);
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* is_gpmc_muxed() - tells if address/data lines are multiplexed
|
||||
*****************************************************************/
|
||||
u32 is_gpmc_muxed(void)
|
||||
{
|
||||
u32 mux;
|
||||
mux = get_sysboot_value();
|
||||
if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
|
||||
return (GPMC_MUXED); /* NAND Boot mode */
|
||||
if (mux & BIT1) /* if mux'ed */
|
||||
return (GPMC_MUXED);
|
||||
else
|
||||
return (GPMC_NONMUXED);
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* get_gpmc0_type() - read sysboot lines to see type of memory attached
|
||||
************************************************************************/
|
||||
u32 get_gpmc0_type(void)
|
||||
{
|
||||
u32 type;
|
||||
type = get_sysboot_value();
|
||||
if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
|
||||
return (TYPE_NAND);
|
||||
else
|
||||
return (TYPE_NOR);
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
|
||||
*******************************************************************/
|
||||
u32 get_gpmc0_width(void)
|
||||
{
|
||||
u32 width;
|
||||
width = get_sysboot_value();
|
||||
if ((width & 0xF) == (BIT3 | BIT2))
|
||||
return (WIDTH_8BIT);
|
||||
else
|
||||
return (WIDTH_16BIT);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* wait_on_value() - common routine to allow waiting for changes in
|
||||
* volatile regs.
|
||||
*********************************************************************/
|
||||
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
|
||||
{
|
||||
u32 i = 0, val;
|
||||
do {
|
||||
++i;
|
||||
val = __raw_readl(read_addr) & read_bit_mask;
|
||||
if (val == match_value)
|
||||
return (1);
|
||||
if (i == bound)
|
||||
return (0);
|
||||
} while (1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* display_board_info() - print banner with board info.
|
||||
*********************************************************************/
|
||||
void display_board_info(u32 btype)
|
||||
{
|
||||
char cpu_2420[] = "2420"; /* cpu type */
|
||||
char cpu_2422[] = "2422";
|
||||
char cpu_2423[] = "2423";
|
||||
char db_men[] = "Menelaus"; /* board type */
|
||||
char db_ip[] = "IP";
|
||||
char mem_sdr[] = "mSDR"; /* memory type */
|
||||
char mem_ddr[] = "mDDR";
|
||||
char t_tst[] = "TST"; /* security level */
|
||||
char t_emu[] = "EMU";
|
||||
char t_hs[] = "HS";
|
||||
char t_gp[] = "GP";
|
||||
char unk[] = "?";
|
||||
|
||||
char *cpu_s, *db_s, *mem_s, *sec_s;
|
||||
u32 cpu, rev, sec;
|
||||
|
||||
rev = get_cpu_rev();
|
||||
cpu = get_cpu_type();
|
||||
sec = get_device_type();
|
||||
|
||||
if (is_mem_sdr())
|
||||
mem_s = mem_sdr;
|
||||
else
|
||||
mem_s = mem_ddr;
|
||||
|
||||
if (cpu == CPU_2423)
|
||||
cpu_s = cpu_2423;
|
||||
else if (cpu == CPU_2422)
|
||||
cpu_s = cpu_2422;
|
||||
else
|
||||
cpu_s = cpu_2420;
|
||||
|
||||
if (btype == BOARD_H4_MENELAUS)
|
||||
db_s = db_men;
|
||||
else
|
||||
db_s = db_ip;
|
||||
|
||||
switch (sec) {
|
||||
case TST_DEVICE:
|
||||
sec_s = t_tst;
|
||||
break;
|
||||
case EMU_DEVICE:
|
||||
sec_s = t_emu;
|
||||
break;
|
||||
case HS_DEVICE:
|
||||
sec_s = t_hs;
|
||||
break;
|
||||
case GP_DEVICE:
|
||||
sec_s = t_gp;
|
||||
break;
|
||||
default:
|
||||
sec_s = unk;
|
||||
}
|
||||
|
||||
printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
|
||||
printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* get_board_rev() - setup to pass kernel board revision information
|
||||
* 0 = 242x IP platform (first 2xx boards)
|
||||
* 1 = 242x Menelaus platfrom.
|
||||
*************************************************************************/
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
u32 rev = 0;
|
||||
u32 btype = get_board_type();
|
||||
|
||||
if (btype == BOARD_H4_MENELAUS)
|
||||
rev = 1;
|
||||
return (rev);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* get_base(); get upper addr of current execution
|
||||
*******************************************************/
|
||||
u32 get_base(void)
|
||||
{
|
||||
u32 val;
|
||||
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
|
||||
val &= 0xF0000000;
|
||||
val >>= 28;
|
||||
return (val);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* get_base2(); get 2upper addr of current execution
|
||||
*******************************************************/
|
||||
u32 get_base2(void)
|
||||
{
|
||||
u32 val;
|
||||
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
|
||||
val &= 0xFF000000;
|
||||
val >>= 24;
|
||||
return (val);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* running_in_flash() - tell if currently running in
|
||||
* flash.
|
||||
*******************************************************/
|
||||
u32 running_in_flash(void)
|
||||
{
|
||||
if (get_base() < 4)
|
||||
return (1); /* in flash */
|
||||
return (0); /* running in SRAM or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* running_in_sram() - tell if currently running in
|
||||
* sram.
|
||||
*******************************************************/
|
||||
u32 running_in_sram(void)
|
||||
{
|
||||
if (get_base() == 4)
|
||||
return (1); /* in SRAM */
|
||||
return (0); /* running in FLASH or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* running_in_sdram() - tell if currently running in
|
||||
* flash.
|
||||
*******************************************************/
|
||||
u32 running_in_sdram(void)
|
||||
{
|
||||
if (get_base() > 4)
|
||||
return (1); /* in sdram */
|
||||
return (0); /* running in SRAM or FLASH */
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* running_from_internal_boot() - am I a signed NOR image.
|
||||
*************************************************************/
|
||||
u32 running_from_internal_boot(void)
|
||||
{
|
||||
u32 v, base;
|
||||
|
||||
v = get_sysboot_value() & BIT3;
|
||||
base = get_base2();
|
||||
/* if running at mask rom flash address and
|
||||
* sysboot3 says this was an internal boot
|
||||
*/
|
||||
if ((base == 0x08) && v)
|
||||
return (1);
|
||||
else
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* get_device_type(): tell if GP/HS/EMU/TST
|
||||
*************************************************************/
|
||||
u32 get_device_type(void)
|
||||
{
|
||||
int mode;
|
||||
mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
|
||||
return (mode >>= 8);
|
||||
}
|
||||
63
board/apollon/u-boot.lds
Normal file
63
board/apollon/u-boot.lds
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2005-2007 Samsung Electronics
|
||||
* Kyungin Park <kyugnmin.park@samsung.com>
|
||||
*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm1136/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -263,7 +263,6 @@ static void ft_blob_update(void *blob, bd_t *bd)
|
|||
{
|
||||
int len, ret, nodeoffset = 0;
|
||||
char module_name[MODULE_NAME_MAXLEN] = {0};
|
||||
ulong memory_data[2] = {0};
|
||||
|
||||
compose_module_name(hw_id, module_name);
|
||||
len = strlen(module_name) + 1;
|
||||
|
|
@ -273,22 +272,12 @@ static void ft_blob_update(void *blob, bd_t *bd)
|
|||
printf("ft_blob_update(): cannot set /model property err:%s\n",
|
||||
fdt_strerror(ret));
|
||||
|
||||
memory_data[0] = cpu_to_be32(bd->bi_memstart);
|
||||
memory_data[1] = cpu_to_be32(bd->bi_memsize);
|
||||
ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
|
||||
|
||||
nodeoffset = fdt_find_node_by_path (blob, "/memory");
|
||||
if (nodeoffset >= 0) {
|
||||
ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
|
||||
sizeof(memory_data));
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
printf("ft_blob_update): cannot set /memory/reg "
|
||||
"property err:%s\n", fdt_strerror(ret));
|
||||
}
|
||||
else {
|
||||
/* memory node is required in dts */
|
||||
printf("ft_blob_update(): cannot find /memory node "
|
||||
"err:%s\n", fdt_strerror(nodeoffset));
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ SECTIONS
|
|||
{
|
||||
*(.text)
|
||||
common/environment.o(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ SECTIONS
|
|||
board/cray/L1/init.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ SECTIONS
|
|||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ SECTIONS
|
|||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <command.h>
|
||||
#include <asm/au1x00.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
|
|
@ -77,6 +78,9 @@ int checkboard (void)
|
|||
default:
|
||||
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
|
||||
}
|
||||
|
||||
set_io_port_base(0);
|
||||
|
||||
#ifdef CONFIG_IDE_PCMCIA
|
||||
/* Enable 3.3 V on slot 0 ( VCC )
|
||||
No 5V */
|
||||
|
|
|
|||
|
|
@ -43,21 +43,22 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
|
||||
.got : {
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ SECTIONS
|
|||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include "asm/io.h"
|
||||
#include "lcd.h"
|
||||
|
||||
|
||||
|
|
@ -36,43 +37,41 @@ int lcd_depth;
|
|||
unsigned char *glob_lcd_reg;
|
||||
unsigned char *glob_lcd_mem;
|
||||
|
||||
#ifdef CFG_LCD_ENDIAN
|
||||
#if defined(CFG_LCD_ENDIAN)
|
||||
void lcd_setup(int lcd, int config)
|
||||
{
|
||||
if (lcd == 0) {
|
||||
/*
|
||||
* Set endianess and reset lcd controller 0 (small)
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
|
||||
udelay(10); /* wait 10us */
|
||||
if (config == 1) {
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
} else {
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
}
|
||||
if (config == 1)
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
else
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
|
||||
} else {
|
||||
/*
|
||||
* Set endianess and reset lcd controller 1 (big)
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
|
||||
udelay(10); /* wait 10us */
|
||||
if (config == 1) {
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
} else {
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
}
|
||||
if (config == 1)
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
else
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
|
||||
}
|
||||
|
||||
/*
|
||||
* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
|
||||
}
|
||||
#endif /* #ifdef CFG_LCD_ENDIAN */
|
||||
#endif /* CFG_LCD_ENDIAN */
|
||||
|
||||
|
||||
void lcd_bmp(uchar *logo_bmp)
|
||||
|
|
@ -94,7 +93,6 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
* Check for bmp mark 'BM'
|
||||
*/
|
||||
if (*(ushort *)logo_bmp != 0x424d) {
|
||||
|
||||
/*
|
||||
* Decompress bmp image
|
||||
*/
|
||||
|
|
@ -104,12 +102,10 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
printf("Error: malloc in gunzip failed!\n");
|
||||
return;
|
||||
}
|
||||
if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
|
||||
if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0)
|
||||
return;
|
||||
}
|
||||
if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
|
||||
if (len == CFG_VIDEO_LOGO_MAX_SIZE)
|
||||
printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Check for bmp mark 'BM'
|
||||
|
|
@ -152,9 +148,8 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
break;
|
||||
default:
|
||||
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||
free(dst);
|
||||
}
|
||||
return;
|
||||
}
|
||||
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
|
||||
|
|
@ -164,7 +159,7 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
*/
|
||||
if ((colors <= 256) && (lcd_depth <= 8)) {
|
||||
ptr = (unsigned char *)(dst + 14 + 40);
|
||||
for (i=0; i<colors; i++) {
|
||||
for (i = 0; i < colors; i++) {
|
||||
b = *ptr++;
|
||||
g = *ptr++;
|
||||
r = *ptr++;
|
||||
|
|
@ -179,11 +174,11 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
ptr = glob_lcd_mem;
|
||||
ptr2 = (ushort *)glob_lcd_mem;
|
||||
header_size = 14 + 40 + 4*colors; /* skip bmp header */
|
||||
for (y=0; y<height; y++) {
|
||||
for (y = 0; y < height; y++) {
|
||||
bmp = &dst[(height-1-y)*line_size + header_size];
|
||||
if (lcd_depth == 16) {
|
||||
if (bpp == 24) {
|
||||
for (x=0; x<width; x++) {
|
||||
for (x = 0; x < width; x++) {
|
||||
/*
|
||||
* Generate epson 16bpp fb-format from 24bpp image
|
||||
*/
|
||||
|
|
@ -194,7 +189,7 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
*ptr2++ = val;
|
||||
}
|
||||
} else if (bpp == 8) {
|
||||
for (x=0; x<line_size; x++) {
|
||||
for (x = 0; x < line_size; x++) {
|
||||
/* query rgb value from palette */
|
||||
ptr = (unsigned char *)(dst + 14 + 40) ;
|
||||
ptr += (*bmp++) << 2;
|
||||
|
|
@ -206,15 +201,13 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
}
|
||||
}
|
||||
} else {
|
||||
for (x=0; x<line_size; x++) {
|
||||
for (x = 0; x < line_size; x++)
|
||||
*ptr++ = *bmp++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||
free(dst);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -229,10 +222,10 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
/*
|
||||
* Detect epson
|
||||
*/
|
||||
lcd_reg[0] = 0x00;
|
||||
lcd_reg[1] = 0x00;
|
||||
out_8(&lcd_reg[0], 0x00);
|
||||
out_8(&lcd_reg[1], 0x00);
|
||||
|
||||
if (lcd_reg[0] == 0x1c) {
|
||||
if (in_8(&lcd_reg[0]) == 0x1c) {
|
||||
/*
|
||||
* Big epson detected
|
||||
*/
|
||||
|
|
@ -241,7 +234,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
palette_value = 0x1e4;
|
||||
lcd_depth = 16;
|
||||
puts("LCD: S1D13806");
|
||||
} else if (lcd_reg[1] == 0x1c) {
|
||||
} else if (in_8(&lcd_reg[1]) == 0x1c) {
|
||||
/*
|
||||
* Big epson detected (with register swap bug)
|
||||
*/
|
||||
|
|
@ -250,7 +243,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
palette_value = 0x1e5;
|
||||
lcd_depth = 16;
|
||||
puts("LCD: S1D13806S");
|
||||
} else if (lcd_reg[0] == 0x18) {
|
||||
} else if (in_8(&lcd_reg[0]) == 0x18) {
|
||||
/*
|
||||
* Small epson detected (704)
|
||||
*/
|
||||
|
|
@ -259,7 +252,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
palette_value = 0x17;
|
||||
lcd_depth = 8;
|
||||
puts("LCD: S1D13704");
|
||||
} else if (lcd_reg[0x10000] == 0x24) {
|
||||
} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
|
||||
/*
|
||||
* Small epson detected (705)
|
||||
*/
|
||||
|
|
@ -277,7 +270,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
/*
|
||||
* Setup lcd controller regs
|
||||
*/
|
||||
for (i = 0; i<reg_count; i++) {
|
||||
for (i = 0; i < reg_count; i++) {
|
||||
s1dReg = regs[i].Index;
|
||||
if (reg_byte_swap) {
|
||||
if ((s1dReg & 0x0001) == 0)
|
||||
|
|
@ -301,7 +294,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
lcd_bmp(logo_bmp);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_VIDEO_SM501
|
||||
#if defined(CONFIG_VIDEO_SM501)
|
||||
int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong addr;
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -1,152 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
|
||||
long int fixed_sdram( void );
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
uint reg;
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr( ebccfga, xbcfg );
|
||||
reg = mfdcr( ebccfgd );
|
||||
mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
|
||||
|
||||
mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
|
||||
mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
|
||||
/* test-only: other regs still missing... */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr( uic0sr, 0xffffffff ); /* clear all */
|
||||
mtdcr( uic0er, 0x00000000 ); /* disable all */
|
||||
mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
|
||||
mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
|
||||
mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
|
||||
mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
|
||||
mtdcr( uic0sr, 0xffffffff ); /* clear all */
|
||||
|
||||
mtdcr( uic1sr, 0xffffffff ); /* clear all */
|
||||
mtdcr( uic1er, 0x00000000 ); /* disable all */
|
||||
mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
|
||||
mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
|
||||
mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
|
||||
mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
|
||||
mtdcr( uic1sr, 0xffffffff ); /* clear all */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
get_sys_info(&sysinfo);
|
||||
|
||||
printf("Board: esd CPCI-440\n");
|
||||
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
|
||||
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
|
||||
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
|
||||
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
|
||||
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
dram_size = fixed_sdram();
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
*
|
||||
* Assumes: 64 MB, non-ECC, non-registered
|
||||
* PLB @ 133 MHz
|
||||
*
|
||||
************************************************************************/
|
||||
long int fixed_sdram( void )
|
||||
{
|
||||
uint reg;
|
||||
|
||||
#if 1 /* test-only */
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default
|
||||
*------------------------------------------------------------------*/
|
||||
mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
|
||||
mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
|
||||
mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
|
||||
mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */
|
||||
mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem
|
||||
*------------------------------------------------------------------*/
|
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
|
||||
mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
|
||||
/* RA=10 RD=3 */
|
||||
mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
|
||||
mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
|
||||
mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
|
||||
udelay( 400 ); /* Delay 200 usecs (min) */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete
|
||||
*------------------------------------------------------------------*/
|
||||
mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
|
||||
for(;;)
|
||||
{
|
||||
mfsdram( mem_mcsts, reg );
|
||||
if( reg & 0x80000000 )
|
||||
break;
|
||||
}
|
||||
|
||||
return( 64 * 1024 * 1024 ); /* 64 MB */
|
||||
#else
|
||||
return( 32 * 1024 * 1024 ); /* 64 MB */
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbtab_end
|
||||
|
|
@ -1,755 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#undef DEBUG_FLASH
|
||||
/*
|
||||
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
|
||||
* The width of the port and the width of the chips are determined at initialization.
|
||||
* These widths are used to calculate the address for access CFI data structures.
|
||||
* It has been tested on an Intel Strataflash implementation.
|
||||
*
|
||||
* References
|
||||
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
|
||||
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
|
||||
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
|
||||
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
|
||||
*
|
||||
* TODO
|
||||
* Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
|
||||
* Add support for other command sets Use the PRI and ALT to determine command set
|
||||
* Verify erase and program timeouts.
|
||||
*/
|
||||
|
||||
#define FLASH_CMD_CFI 0x98
|
||||
#define FLASH_CMD_READ_ID 0x90
|
||||
#define FLASH_CMD_RESET 0xff
|
||||
#define FLASH_CMD_BLOCK_ERASE 0x20
|
||||
#define FLASH_CMD_ERASE_CONFIRM 0xD0
|
||||
#define FLASH_CMD_WRITE 0x40
|
||||
#define FLASH_CMD_PROTECT 0x60
|
||||
#define FLASH_CMD_PROTECT_SET 0x01
|
||||
#define FLASH_CMD_PROTECT_CLEAR 0xD0
|
||||
#define FLASH_CMD_CLEAR_STATUS 0x50
|
||||
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
|
||||
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
|
||||
|
||||
#define FLASH_STATUS_DONE 0x80
|
||||
#define FLASH_STATUS_ESS 0x40
|
||||
#define FLASH_STATUS_ECLBS 0x20
|
||||
#define FLASH_STATUS_PSLBS 0x10
|
||||
#define FLASH_STATUS_VPENS 0x08
|
||||
#define FLASH_STATUS_PSS 0x04
|
||||
#define FLASH_STATUS_DPS 0x02
|
||||
#define FLASH_STATUS_R 0x01
|
||||
#define FLASH_STATUS_PROTECT 0x01
|
||||
|
||||
#define FLASH_OFFSET_CFI 0x55
|
||||
#define FLASH_OFFSET_CFI_RESP 0x10
|
||||
#define FLASH_OFFSET_WTOUT 0x1F
|
||||
#define FLASH_OFFSET_WBTOUT 0x20
|
||||
#define FLASH_OFFSET_ETOUT 0x21
|
||||
#define FLASH_OFFSET_CETOUT 0x22
|
||||
#define FLASH_OFFSET_WMAX_TOUT 0x23
|
||||
#define FLASH_OFFSET_WBMAX_TOUT 0x24
|
||||
#define FLASH_OFFSET_EMAX_TOUT 0x25
|
||||
#define FLASH_OFFSET_CEMAX_TOUT 0x26
|
||||
#define FLASH_OFFSET_SIZE 0x27
|
||||
#define FLASH_OFFSET_INTERFACE 0x28
|
||||
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
|
||||
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
|
||||
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
|
||||
#define FLASH_OFFSET_PROTECT 0x02
|
||||
#define FLASH_OFFSET_USER_PROTECTION 0x85
|
||||
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
|
||||
|
||||
|
||||
#define FLASH_MAN_CFI 0x01000000
|
||||
|
||||
|
||||
typedef union {
|
||||
unsigned char c;
|
||||
unsigned short w;
|
||||
unsigned long l;
|
||||
} cfiword_t;
|
||||
|
||||
typedef union {
|
||||
unsigned char * cp;
|
||||
unsigned short *wp;
|
||||
unsigned long *lp;
|
||||
} cfiptr_t;
|
||||
|
||||
#define NUM_ERASE_REGIONS 4
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
|
||||
|
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
||||
static int flash_detect_cfi(flash_info_t * info);
|
||||
static ulong flash_get_size (ulong base, int banknum);
|
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
* create an address based on the offset and the port width
|
||||
*/
|
||||
inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
|
||||
{
|
||||
return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a character at a port width address
|
||||
*/
|
||||
inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
|
||||
{
|
||||
uchar *cp;
|
||||
cp = flash_make_addr(info, 0, offset);
|
||||
return (cp[info->portwidth - 1]);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a short word by swapping for ppc format.
|
||||
*/
|
||||
ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
|
||||
{
|
||||
uchar * addr;
|
||||
|
||||
addr = flash_make_addr(info, sect, offset);
|
||||
return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* read a long word by picking the least significant byte of each maiximum
|
||||
* port size word. Swap for ppc format.
|
||||
*/
|
||||
ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
|
||||
{
|
||||
uchar * addr;
|
||||
|
||||
addr = flash_make_addr(info, sect, offset);
|
||||
return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
|
||||
(addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size;
|
||||
int i;
|
||||
unsigned long address;
|
||||
|
||||
|
||||
/* The flash is positioned back to back, with the demultiplexing of the chip
|
||||
* based on the A24 address line.
|
||||
*
|
||||
*/
|
||||
|
||||
address = CFG_FLASH_BASE;
|
||||
size = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
size += flash_info[i].size = flash_get_size(address, i);
|
||||
address += CFG_FLASH_INCREMENT;
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
|
||||
flash_info[0].size, flash_info[i].size<<20);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0 /* test-only */
|
||||
/* Monitor protection ON by default */
|
||||
#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
|
||||
for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
|
||||
(void)flash_real_protect(&flash_info[0], i, 1);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
int rcode = 0;
|
||||
int prot;
|
||||
int sect;
|
||||
|
||||
if( info->flash_id != FLASH_MAN_CFI) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
printf ("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
|
||||
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
|
||||
|
||||
if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
|
||||
rcode = 1;
|
||||
} else
|
||||
printf(".");
|
||||
}
|
||||
}
|
||||
printf (" done\n");
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id != FLASH_MAN_CFI) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printf("CFI conformant FLASH (%d x %d)",
|
||||
(info->portwidth << 3 ), (info->chipwidth << 3 ));
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
|
||||
info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n");
|
||||
printf (" %08lX%5s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp;
|
||||
ulong cp;
|
||||
int aln;
|
||||
cfiword_t cword;
|
||||
int i, rc;
|
||||
|
||||
/* get lower aligned address */
|
||||
wp = (addr & ~(info->portwidth - 1));
|
||||
|
||||
/* handle unaligned start */
|
||||
if((aln = addr - wp) != 0) {
|
||||
cword.l = 0;
|
||||
cp = wp;
|
||||
for(i=0;i<aln; ++i, ++cp)
|
||||
flash_add_byte(info, &cword, (*(uchar *)cp));
|
||||
|
||||
for(; (i< info->portwidth) && (cnt > 0) ; i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
cnt--;
|
||||
cp++;
|
||||
}
|
||||
for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
|
||||
flash_add_byte(info, &cword, (*(uchar *)cp));
|
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp = cp;
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
||||
while(cnt >= info->portwidth) {
|
||||
i = info->buffer_size > cnt? cnt: info->buffer_size;
|
||||
if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
|
||||
return rc;
|
||||
wp += i;
|
||||
src += i;
|
||||
cnt -=i;
|
||||
}
|
||||
#else
|
||||
/* handle the aligned part */
|
||||
while(cnt >= info->portwidth) {
|
||||
cword.l = 0;
|
||||
for(i = 0; i < info->portwidth; i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
}
|
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp += info->portwidth;
|
||||
cnt -= info->portwidth;
|
||||
}
|
||||
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
cword.l = 0;
|
||||
for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
--cnt;
|
||||
}
|
||||
for (; i<info->portwidth; ++i, ++cp) {
|
||||
flash_add_byte(info, & cword, (*(uchar *)cp));
|
||||
}
|
||||
|
||||
return flash_write_cfiword(info, wp, cword);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_real_protect(flash_info_t *info, long sector, int prot)
|
||||
{
|
||||
int retcode = 0;
|
||||
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
|
||||
if(prot)
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
|
||||
else
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
|
||||
|
||||
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
|
||||
prot?"protect":"unprotect")) == 0) {
|
||||
|
||||
info->protect[sector] = prot;
|
||||
/* Intel's unprotect unprotects all locking */
|
||||
if(prot == 0) {
|
||||
int i;
|
||||
for(i = 0 ; i<info->sector_count; i++) {
|
||||
if(info->protect[i])
|
||||
flash_real_protect(info, i, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return retcode;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* wait for XSR.7 to be set. Time out with an error if it does not.
|
||||
* This routine does not set the flash to read-array mode.
|
||||
*/
|
||||
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
||||
{
|
||||
ulong start;
|
||||
|
||||
/* Wait for command completion */
|
||||
start = get_timer (0);
|
||||
while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
|
||||
if (get_timer(start) > info->erase_blk_tout) {
|
||||
printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return ERR_TIMOUT;
|
||||
}
|
||||
}
|
||||
return ERR_OK;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
|
||||
* This routine sets the flash to read-array mode.
|
||||
*/
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
||||
{
|
||||
int retcode;
|
||||
retcode = flash_status_check(info, sector, tout, prompt);
|
||||
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
|
||||
retcode = ERR_INVAL;
|
||||
printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
|
||||
printf("Command Sequence Error.\n");
|
||||
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
|
||||
printf("Block Erase Error.\n");
|
||||
retcode = ERR_NOT_ERASED;
|
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
|
||||
printf("Locking Error\n");
|
||||
}
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
|
||||
printf("Block locked.\n");
|
||||
retcode = ERR_PROTECTED;
|
||||
}
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
|
||||
printf("Vpp Low Error.\n");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return retcode;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
|
||||
{
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cword->c = c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cword->w = (cword->w << 8) | c;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cword->l = (cword->l << 8) | c;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* make a proper sized command based on the port and chip widths
|
||||
*/
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
|
||||
{
|
||||
int i;
|
||||
uchar *cp = (uchar *)cmdbuf;
|
||||
for(i=0; i< info->portwidth; i++)
|
||||
*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a proper sized command to the correct address
|
||||
*/
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
|
||||
volatile cfiptr_t addr;
|
||||
cfiword_t cword;
|
||||
addr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*addr.cp = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*addr.wp = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*addr.lp = cword.l;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = (cptr.cp[0] == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = (cptr.wp[0] == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = (cptr.lp[0] == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* detect if flash is compatible with the Common Flash Interface (CFI)
|
||||
* http://www.jedec.org/download/search/jesd68.pdf
|
||||
*
|
||||
*/
|
||||
static int flash_detect_cfi(flash_info_t * info)
|
||||
{
|
||||
|
||||
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
|
||||
info->portwidth <<= 1) {
|
||||
for(info->chipwidth =FLASH_CFI_BY8;
|
||||
info->chipwidth <= info->portwidth;
|
||||
info->chipwidth <<= 1) {
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
|
||||
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
|
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
|
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*
|
||||
*/
|
||||
static ulong flash_get_size (ulong base, int banknum)
|
||||
{
|
||||
flash_info_t * info = &flash_info[banknum];
|
||||
int i, j;
|
||||
int sect_cnt;
|
||||
unsigned long sector;
|
||||
unsigned long tmp;
|
||||
int size_ratio;
|
||||
uchar num_erase_regions;
|
||||
int erase_region_size;
|
||||
int erase_region_count;
|
||||
|
||||
info->start[0] = base;
|
||||
|
||||
if(flash_detect_cfi(info)){
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
|
||||
#endif
|
||||
size_ratio = info->portwidth / info->chipwidth;
|
||||
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("found %d erase regions\n", num_erase_regions);
|
||||
#endif
|
||||
sect_cnt = 0;
|
||||
sector = base;
|
||||
for(i = 0 ; i < num_erase_regions; i++) {
|
||||
if(i > NUM_ERASE_REGIONS) {
|
||||
printf("%d erase regions found, only %d used\n",
|
||||
num_erase_regions, NUM_ERASE_REGIONS);
|
||||
break;
|
||||
}
|
||||
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
|
||||
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
|
||||
tmp >>= 16;
|
||||
erase_region_count = (tmp & 0xffff) +1;
|
||||
for(j = 0; j< erase_region_count; j++) {
|
||||
info->start[sect_cnt] = sector;
|
||||
sector += (erase_region_size * size_ratio);
|
||||
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
|
||||
sect_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
info->sector_count = sect_cnt;
|
||||
/* multiply the size by the number of chips */
|
||||
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
|
||||
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
|
||||
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
|
||||
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
|
||||
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
|
||||
info->flash_id = FLASH_MAN_CFI;
|
||||
}
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
return(info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
|
||||
{
|
||||
|
||||
cfiptr_t ctladdr;
|
||||
cfiptr_t cptr;
|
||||
int flag;
|
||||
|
||||
ctladdr.cp = flash_make_addr(info, 0, 0);
|
||||
cptr.cp = (uchar *)dest;
|
||||
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
flag = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
flag = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
flag = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
return 2;
|
||||
}
|
||||
if(!flag)
|
||||
return 2;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
|
||||
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cptr.cp[0] = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cptr.wp[0] = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cptr.lp[0] = cword.l;
|
||||
break;
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if(flag)
|
||||
enable_interrupts();
|
||||
|
||||
return flash_full_status_check(info, 0, info->write_tout, "write");
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/* loop through the sectors from the highest address
|
||||
* when the passed address is greater or equal to the sector address
|
||||
* we have a match
|
||||
*/
|
||||
static int find_sector(flash_info_t *info, ulong addr)
|
||||
{
|
||||
int sector;
|
||||
for(sector = info->sector_count - 1; sector >= 0; sector--) {
|
||||
if(addr >= info->start[sector])
|
||||
break;
|
||||
}
|
||||
return sector;
|
||||
}
|
||||
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
|
||||
{
|
||||
|
||||
int sector;
|
||||
int cnt;
|
||||
int retcode;
|
||||
volatile cfiptr_t src;
|
||||
volatile cfiptr_t dst;
|
||||
|
||||
src.cp = cp;
|
||||
dst.cp = (uchar *)dest;
|
||||
sector = find_sector(info, dest);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
|
||||
if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
|
||||
"write to buffer")) == ERR_OK) {
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cnt = len;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cnt = len >> 1;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cnt = len >> 2;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, (uchar)cnt-1);
|
||||
while(cnt-- > 0) {
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*dst.cp++ = *src.cp++;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*dst.wp++ = *src.wp++;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*dst.lp++ = *src.lp++;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
|
||||
retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
|
||||
"buffer write");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
return retcode;
|
||||
}
|
||||
#endif /* CFG_USE_FLASH_BUFFER_WRITE */
|
||||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/iop480_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <405gp_pci.h>
|
||||
#include <asm/4xx_pci.h>
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_BSP)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#include <net.h>
|
||||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
#include <405gp_pci.h>
|
||||
#include <asm/4xx_pci.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include "pci405.h"
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <pci.h>
|
||||
#include <405gp_pci.h>
|
||||
#include <asm/4xx_pci.h>
|
||||
|
||||
#include "pci405.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -109,8 +109,8 @@ int misc_init_f (void)
|
|||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||
volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||
unsigned char *dst;
|
||||
ulong len = sizeof(fpgadata);
|
||||
int status;
|
||||
|
|
@ -184,16 +184,28 @@ int misc_init_r (void)
|
|||
/*
|
||||
* Reset external DUARTs
|
||||
*/
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||
udelay(10); /* wait 10us */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Setup EEPROM write protection
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
*duart0_mcr = 0x08;
|
||||
*duart1_mcr = 0x08;
|
||||
out_8(duart0_mcr, 0x08);
|
||||
out_8(duart1_mcr, 0x08);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -259,3 +271,74 @@ void reset_phy(void)
|
|||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable (unsigned dev_addr, int state)
|
||||
{
|
||||
if (CFG_I2C_EEPROM_ADDR != dev_addr) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts ("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts ("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||
NULL);
|
||||
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -22,13 +22,12 @@
|
|||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o strataflash.o ../common/misc.o
|
||||
COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
|
||||
../common/cmd_loadpci.o
|
||||
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
|
@ -36,7 +35,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
|
|||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
558
board/esd/pmc440/cmd_pmc440.c
Normal file
558
board/esd/pmc440/cmd_pmc440.c
Normal file
|
|
@ -0,0 +1,558 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include "pmc440.h"
|
||||
|
||||
int is_monarch(void);
|
||||
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
|
||||
int eeprom_write_enable(unsigned dev_addr, int state);
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_BSP)
|
||||
|
||||
static int got_fifoirq;
|
||||
static int got_hcirq;
|
||||
|
||||
int fpga_interrupt(u32 arg)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
|
||||
int rc = -1; /* not for us */
|
||||
u32 status = FPGA_IN32(&fpga->status);
|
||||
|
||||
/* check for interrupt from fifo module */
|
||||
if (status & STATUS_FIFO_ISF) {
|
||||
/* disable this int source */
|
||||
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
|
||||
rc = 0;
|
||||
got_fifoirq = 1; /* trigger backend */
|
||||
}
|
||||
|
||||
if (status & STATUS_HOST_ISF) {
|
||||
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
|
||||
rc = 0;
|
||||
got_hcirq = 1;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
got_hcirq = 0;
|
||||
|
||||
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
|
||||
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
|
||||
|
||||
irq_install_handler(IRQ0_FPGA,
|
||||
(interrupt_handler_t *)fpga_interrupt,
|
||||
fpga);
|
||||
|
||||
FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
|
||||
|
||||
while (!got_hcirq) {
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (got_hcirq)
|
||||
printf("Got interrupt!\n");
|
||||
|
||||
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
|
||||
irq_free_handler(IRQ0_FPGA);
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
waithci, 1, 1, do_waithci,
|
||||
"waithci - Wait for host control interrupt\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
|
||||
void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
|
||||
{
|
||||
u32 ctrl;
|
||||
|
||||
while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
|
||||
printf("%5d %d %3d %08x",
|
||||
(*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
|
||||
FPGA_IN32(&fpga->fifo[f].data));
|
||||
if (ctrl & FIFO_OVERFLOW) {
|
||||
printf(" OVERFLOW\n");
|
||||
FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
|
||||
} else
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
int i;
|
||||
int n = 0;
|
||||
u32 ctrl, data, f;
|
||||
char str[] = "\\|/-";
|
||||
int abort = 0;
|
||||
int count = 0;
|
||||
int count2 = 0;
|
||||
|
||||
switch (argc) {
|
||||
case 1:
|
||||
/* print all fifos status information */
|
||||
printf("fifo level status\n");
|
||||
printf("______________________________\n");
|
||||
for (i=0; i<FIFO_COUNT; i++) {
|
||||
ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
|
||||
printf(" %d %3d %s%s%s %s\n",
|
||||
i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
|
||||
ctrl & FIFO_FULL ? "FULL " : "",
|
||||
ctrl & FIFO_EMPTY ? "EMPTY " : "",
|
||||
ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
|
||||
ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
|
||||
}
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/* completely read out fifo 'n' */
|
||||
if (!strcmp(argv[1],"read")) {
|
||||
printf(" # fifo level data\n");
|
||||
printf("______________________________\n");
|
||||
|
||||
for (i=0; i<FIFO_COUNT; i++)
|
||||
dump_fifo(fpga, i, &n);
|
||||
|
||||
} else if (!strcmp(argv[1],"wait")) {
|
||||
got_fifoirq = 0;
|
||||
|
||||
irq_install_handler(IRQ0_FPGA,
|
||||
(interrupt_handler_t *)fpga_interrupt,
|
||||
fpga);
|
||||
|
||||
printf(" # fifo level data\n");
|
||||
printf("______________________________\n");
|
||||
|
||||
/* enable all fifo interrupts */
|
||||
FPGA_OUT32(&fpga->hostctrl,
|
||||
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
|
||||
for (i=0; i<FIFO_COUNT; i++) {
|
||||
/* enable interrupts from all fifos */
|
||||
FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
|
||||
}
|
||||
|
||||
while (1) {
|
||||
/* wait loop */
|
||||
while (!got_fifoirq) {
|
||||
count++;
|
||||
if (!(count % 100)) {
|
||||
count2++;
|
||||
putc(0x08); /* backspace */
|
||||
putc(str[count2 % 4]);
|
||||
}
|
||||
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if ((abort = ctrlc())) {
|
||||
puts("\nAbort\n");
|
||||
break;
|
||||
}
|
||||
udelay(1000);
|
||||
}
|
||||
if (abort)
|
||||
break;
|
||||
|
||||
/* simple fifo backend */
|
||||
if (got_fifoirq) {
|
||||
for (i=0; i<FIFO_COUNT; i++)
|
||||
dump_fifo(fpga, i, &n);
|
||||
|
||||
got_fifoirq = 0;
|
||||
/* unmask global fifo irq */
|
||||
FPGA_OUT32(&fpga->hostctrl,
|
||||
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
|
||||
}
|
||||
}
|
||||
|
||||
/* disable all fifo interrupts */
|
||||
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
|
||||
for (i=0; i<FIFO_COUNT; i++)
|
||||
FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
|
||||
|
||||
irq_free_handler(IRQ0_FPGA);
|
||||
|
||||
} else {
|
||||
printf("Usage:\nfifo %s\n", cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 4:
|
||||
case 5:
|
||||
if (!strcmp(argv[1],"write")) {
|
||||
/* get fifo number or fifo address */
|
||||
f = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
/* data paramter */
|
||||
data = simple_strtoul(argv[3], NULL, 16);
|
||||
|
||||
/* get optional count parameter */
|
||||
n = 1;
|
||||
if (argc >= 5)
|
||||
n = (int)simple_strtoul(argv[4], NULL, 10);
|
||||
|
||||
if (f < FIFO_COUNT) {
|
||||
printf("writing %d x %08x to fifo %d\n",
|
||||
n, data, f);
|
||||
for (i=0; i<n; i++)
|
||||
FPGA_OUT32(&fpga->fifo[f].data, data);
|
||||
} else {
|
||||
printf("writing %d x %08x to fifo port at address %08x\n",
|
||||
n, data, f);
|
||||
for (i=0; i<n; i++)
|
||||
out32(f, data);
|
||||
}
|
||||
} else {
|
||||
printf("Usage:\nfifo %s\n", cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Usage:\nfifo %s\n", cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
fifo, 5, 1, do_fifo,
|
||||
"fifo - Fifo module operations\n",
|
||||
"wait\nfifo read\n"
|
||||
"fifo write fifo(0..3) data [cnt=1]\n"
|
||||
"fifo write address(>=4) data [cnt=1]\n"
|
||||
" - without arguments: print all fifo's status\n"
|
||||
" - with 'wait' argument: interrupt driven read from all fifos\n"
|
||||
" - with 'read' argument: read current contents from all fifos\n"
|
||||
" - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
|
||||
);
|
||||
|
||||
|
||||
int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong sdsdp[5];
|
||||
ulong delay;
|
||||
int count=16;
|
||||
|
||||
if (argc < 2) {
|
||||
printf("Usage:\nsbe %s\n", cmdtp->help);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (argc > 1) {
|
||||
if (!strcmp(argv[1], "400")) {
|
||||
/* PLB=133MHz, PLB/PCI=3 */
|
||||
printf("Bootstrapping for 400MHz\n");
|
||||
sdsdp[0]=0x8678624e;
|
||||
sdsdp[1]=0x095fa030;
|
||||
sdsdp[2]=0x40082350;
|
||||
sdsdp[3]=0x0d050000;
|
||||
} else if (!strcmp(argv[1], "533")) {
|
||||
/* PLB=133MHz, PLB/PCI=3 */
|
||||
printf("Bootstrapping for 533MHz\n");
|
||||
sdsdp[0]=0x87788252;
|
||||
sdsdp[1]=0x095fa030;
|
||||
sdsdp[2]=0x40082350;
|
||||
sdsdp[3]=0x0d050000;
|
||||
} else if (!strcmp(argv[1], "667")) {
|
||||
/* PLB=133MHz, PLB/PCI=4 */
|
||||
printf("Bootstrapping for 667MHz\n");
|
||||
sdsdp[0]=0x8778a256;
|
||||
sdsdp[1]=0x0947a030;
|
||||
sdsdp[2]=0x40082350;
|
||||
sdsdp[3]=0x0d050000;
|
||||
} else if (!strcmp(argv[1], "test")) {
|
||||
/* TODO: this will replace the 667 MHz config above.
|
||||
* But it needs some more testing on a real 667 MHz CPU.
|
||||
*/
|
||||
printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
|
||||
sdsdp[0]=0x8778a256;
|
||||
sdsdp[1]=0x095fa030;
|
||||
sdsdp[2]=0x40082350;
|
||||
sdsdp[3]=0x0d050000;
|
||||
} else {
|
||||
printf("Usage:\nsbe %s\n", cmdtp->help);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (argc > 2) {
|
||||
sdsdp[4] = 0;
|
||||
if (argv[2][0]=='1')
|
||||
sdsdp[4]=0x19750100;
|
||||
else if (argv[2][0]=='0')
|
||||
sdsdp[4]=0x19750000;
|
||||
if (sdsdp[4])
|
||||
count += 4;
|
||||
}
|
||||
|
||||
if (argc > 3) {
|
||||
delay = simple_strtoul(argv[3], NULL, 10);
|
||||
if (delay > 20)
|
||||
delay = 20;
|
||||
sdsdp[4] |= delay;
|
||||
}
|
||||
|
||||
printf("Writing boot EEPROM ...\n");
|
||||
if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
|
||||
0, (uchar*)sdsdp, count) != 0)
|
||||
printf("bootstrap_eeprom_write failed\n");
|
||||
else
|
||||
printf("done (dump via 'i2c md 52 0.1 14')\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
sbe, 4, 0, do_setup_bootstrap_eeprom,
|
||||
"sbe - setup bootstrap eeprom\n",
|
||||
"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
|
||||
);
|
||||
|
||||
|
||||
#if defined(CONFIG_PRAM)
|
||||
#include <environment.h>
|
||||
extern env_t *env_ptr;
|
||||
|
||||
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u32 memsize;
|
||||
u32 pram, env_base;
|
||||
char *v;
|
||||
u32 param;
|
||||
ulong *lptr;
|
||||
|
||||
memsize = gd->bd->bi_memsize;
|
||||
|
||||
v = getenv("pram");
|
||||
if (v)
|
||||
pram = simple_strtoul(v, NULL, 10);
|
||||
else {
|
||||
printf("Error: pram undefined. Please define pram in KiB\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
param = memsize - (pram << 10);
|
||||
printf("PARAM: @%08x\n", param);
|
||||
|
||||
memset((void*)param, 0, (pram << 10));
|
||||
env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
|
||||
memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
|
||||
|
||||
lptr = (ulong*)memsize;
|
||||
*(--lptr) = CFG_ENV_SIZE;
|
||||
*(--lptr) = memsize - env_base;
|
||||
*(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
|
||||
*(--lptr) = 0;
|
||||
|
||||
/* make sure data can be accessed through PCI */
|
||||
flush_dcache_range(param, param + (pram << 10) - 1);
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
painit, 1, 1, do_painit,
|
||||
"painit - prepare PciAccess system\n",
|
||||
NULL
|
||||
);
|
||||
#endif /* CONFIG_PRAM */
|
||||
|
||||
|
||||
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
if (argc > 1) {
|
||||
if (argv[1][0] == '0') {
|
||||
/* assert */
|
||||
printf("self-reset# asserted\n");
|
||||
out_be32((void*)GPIO0_TCR,
|
||||
in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
|
||||
} else {
|
||||
/* deassert */
|
||||
printf("self-reset# deasserted\n");
|
||||
out_be32((void*)GPIO0_TCR,
|
||||
in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
|
||||
}
|
||||
} else {
|
||||
printf("self-reset# is %s\n",
|
||||
in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
|
||||
"active" : "inactive");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
selfreset, 2, 1, do_selfreset,
|
||||
"selfreset- assert self-reset# signal\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
|
||||
int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
/* requiers bootet FPGA and PLD_IOEN_N active */
|
||||
if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
|
||||
printf("Error: resetout requires a bootet FPGA\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (argc > 1) {
|
||||
if (argv[1][0] == '0') {
|
||||
/* assert */
|
||||
printf("PMC-RESETOUT# asserted\n");
|
||||
FPGA_OUT32(&fpga->hostctrl,
|
||||
HOSTCTRL_PMCRSTOUT_GATE);
|
||||
} else {
|
||||
/* deassert */
|
||||
printf("PMC-RESETOUT# deasserted\n");
|
||||
FPGA_OUT32(&fpga->hostctrl,
|
||||
HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
|
||||
}
|
||||
} else {
|
||||
printf("PMC-RESETOUT# is %s\n",
|
||||
FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
|
||||
"inactive" : "active");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
resetout, 2, 1, do_resetout,
|
||||
"resetout - assert PMC-RESETOUT# signal\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
|
||||
int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
if (is_monarch()) {
|
||||
printf("This command is only supported in non-monarch mode\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (argc > 1) {
|
||||
if (argv[1][0] == '0') {
|
||||
/* assert */
|
||||
printf("inta# asserted\n");
|
||||
out_be32((void*)GPIO1_TCR,
|
||||
in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
|
||||
} else {
|
||||
/* deassert */
|
||||
printf("inta# deasserted\n");
|
||||
out_be32((void*)GPIO1_TCR,
|
||||
in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
|
||||
}
|
||||
} else {
|
||||
printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
inta, 2, 1, do_inta,
|
||||
"inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
|
||||
/* test-only */
|
||||
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong pciaddr;
|
||||
|
||||
if (argc > 1) {
|
||||
pciaddr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
pciaddr &= 0xf0000000;
|
||||
|
||||
/* map PCI address at 0xc0000000 in PLB space */
|
||||
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
|
||||
out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
|
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
|
||||
out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
|
||||
} else {
|
||||
printf("Usage:\npmm %s\n", cmdtp->help);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
pmm, 2, 1, do_pmm,
|
||||
"pmm - Setup pmm[1] registers\n",
|
||||
"<pciaddr> (pciaddr will be aligned to 256MB)\n"
|
||||
);
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf("Write access for device 0x%0x is %sabled.\n",
|
||||
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||
NULL);
|
||||
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||
|
||||
#endif /* CONFIG_CMD_BSP */
|
||||
|
|
@ -20,18 +20,14 @@
|
|||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# esd ADCIOP boards
|
||||
# AMCC 440EPx Reference Platform (Sequoia) board
|
||||
#
|
||||
|
||||
#TEXT_BASE = 0xFFFE0000
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifeq ($(ramsym),1)
|
||||
TEXT_BASE = 0x07FD0000
|
||||
else
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
#TEXT_BASE = 0x01fc0000
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFFFA0000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
461
board/esd/pmc440/fpga.c
Normal file
461
board/esd/pmc440/fpga.c
Normal file
|
|
@ -0,0 +1,461 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <spartan2.h>
|
||||
#include <spartan3.h>
|
||||
#include <command.h>
|
||||
#include "fpga.h"
|
||||
#include "pmc440.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_FPGA)
|
||||
|
||||
#define USE_SP_CODE
|
||||
|
||||
#ifdef USE_SP_CODE
|
||||
Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
|
||||
fpga_pre_config_fn,
|
||||
fpga_pgm_fn,
|
||||
fpga_init_fn,
|
||||
NULL, /* err */
|
||||
fpga_done_fn,
|
||||
fpga_clk_fn,
|
||||
fpga_cs_fn,
|
||||
fpga_wr_fn,
|
||||
NULL, /* rdata */
|
||||
fpga_wdata_fn,
|
||||
fpga_busy_fn,
|
||||
fpga_abort_fn,
|
||||
fpga_post_config_fn,
|
||||
};
|
||||
#else
|
||||
Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
|
||||
fpga_pre_config_fn,
|
||||
fpga_pgm_fn,
|
||||
fpga_clk_fn,
|
||||
fpga_init_fn,
|
||||
fpga_done_fn,
|
||||
fpga_wr_fn,
|
||||
fpga_post_config_fn,
|
||||
};
|
||||
#endif
|
||||
|
||||
Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
|
||||
ngcc_fpga_pre_config_fn,
|
||||
ngcc_fpga_pgm_fn,
|
||||
ngcc_fpga_clk_fn,
|
||||
ngcc_fpga_init_fn,
|
||||
ngcc_fpga_done_fn,
|
||||
ngcc_fpga_wr_fn,
|
||||
ngcc_fpga_post_config_fn
|
||||
};
|
||||
|
||||
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||
XILINX_XC3S1200E_DESC(
|
||||
#ifdef USE_SP_CODE
|
||||
slave_parallel,
|
||||
#else
|
||||
slave_serial,
|
||||
#endif
|
||||
(void *)&pmc440_fpga_fns,
|
||||
0),
|
||||
XILINX_XC2S200_DESC(
|
||||
slave_serial,
|
||||
(void *)&ngcc_fpga_fns,
|
||||
0)
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Set the active-low FPGA reset signal.
|
||||
*/
|
||||
void fpga_reset(int assert)
|
||||
{
|
||||
debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
||||
if (assert) {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize the SelectMap interface. We assume that the mode and the
|
||||
* initial state of all of the port pins have already been set!
|
||||
*/
|
||||
void fpga_serialslave_init(void)
|
||||
{
|
||||
debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
|
||||
__LINE__);
|
||||
fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||
*/
|
||||
int fpga_pgm_fn(int assert, int flush, int cookie)
|
||||
{
|
||||
debug("%s:%d: FPGA PROGRAM ",
|
||||
__FUNCTION__, __LINE__);
|
||||
|
||||
if (assert) {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
return assert;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||
* asserted (low).
|
||||
*/
|
||||
int fpga_init_fn(int cookie)
|
||||
{
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef USE_SP_CODE
|
||||
int fpga_abort_fn(int cookie)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int fpga_cs_fn(int assert_cs, int flush, int cookie)
|
||||
{
|
||||
return assert_cs;
|
||||
}
|
||||
|
||||
|
||||
int fpga_busy_fn(int cookie)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-high FPGA DONE pin
|
||||
*/
|
||||
int fpga_done_fn(int cookie)
|
||||
{
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA pre-configuration function. Just make sure that
|
||||
* FPGA reset is asserted to keep the FPGA from starting up after
|
||||
* configuration.
|
||||
*/
|
||||
int fpga_pre_config_fn(int cookie)
|
||||
{
|
||||
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
||||
fpga_reset(TRUE);
|
||||
|
||||
/* release init# */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
|
||||
/* disable PLD IOs */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||
* the FPGA appears to be running.
|
||||
*/
|
||||
int fpga_post_config_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
int rc=0;
|
||||
char *s;
|
||||
|
||||
debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
|
||||
|
||||
/* enable PLD0..7 pins */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
|
||||
|
||||
fpga_reset(TRUE);
|
||||
udelay (100);
|
||||
fpga_reset(FALSE);
|
||||
udelay (100);
|
||||
|
||||
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
|
||||
|
||||
/* NGCC only: enable ledlink */
|
||||
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc"))
|
||||
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
if (assert_clk)
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
|
||||
else
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
|
||||
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
|
||||
int fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||
{
|
||||
if (assert_write)
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
|
||||
else
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
|
||||
|
||||
return assert_write;
|
||||
}
|
||||
|
||||
#ifdef USE_SP_CODE
|
||||
int fpga_wdata_fn(uchar data, int flush, int cookie)
|
||||
{
|
||||
uchar val = data;
|
||||
ulong or = in_be32((void*)GPIO1_OR);
|
||||
int i = 7;
|
||||
do {
|
||||
/* Write data */
|
||||
if (val & 0x80)
|
||||
or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
|
||||
else
|
||||
or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
|
||||
|
||||
out_be32((void*)GPIO1_OR, or);
|
||||
|
||||
/* Assert the clock */
|
||||
or |= GPIO1_FPGA_CLK;
|
||||
out_be32((void*)GPIO1_OR, or);
|
||||
val <<= 1;
|
||||
i --;
|
||||
} while (i > 0);
|
||||
|
||||
/* Write last data bit (the 8th clock comes from the sp_load() code */
|
||||
if (val & 0x80)
|
||||
or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
|
||||
else
|
||||
or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
|
||||
|
||||
out_be32((void*)GPIO1_OR, or);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define NGCC_FPGA_PRG CLOCK_EN
|
||||
#define NGCC_FPGA_DATA RESET_OUT
|
||||
#define NGCC_FPGA_DONE CLOCK_IN
|
||||
#define NGCC_FPGA_INIT IRIGB_R_IN
|
||||
#define NGCC_FPGA_CLK CLOCK_OUT
|
||||
|
||||
void ngcc_fpga_serialslave_init(void)
|
||||
{
|
||||
debug("%s:%d: Initialize serial slave interface\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
|
||||
/* make sure program pin is inactive */
|
||||
ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the active-low FPGA reset signal.
|
||||
*/
|
||||
void ngcc_fpga_reset(int assert)
|
||||
{
|
||||
debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
||||
|
||||
if (assert) {
|
||||
FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||
*/
|
||||
int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
|
||||
|
||||
if (assert) {
|
||||
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
|
||||
debug("asserted\n");
|
||||
} else {
|
||||
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
|
||||
debug("deasserted\n");
|
||||
}
|
||||
|
||||
return assert;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||
* asserted (low).
|
||||
*/
|
||||
int ngcc_fpga_init_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
|
||||
if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
|
||||
debug("high\n");
|
||||
return 0;
|
||||
} else {
|
||||
debug("low\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test the state of the active-high FPGA DONE pin
|
||||
*/
|
||||
int ngcc_fpga_done_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
|
||||
if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
|
||||
debug("DONE high\n");
|
||||
return 1;
|
||||
} else {
|
||||
debug("low\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA pre-configuration function.
|
||||
*/
|
||||
int ngcc_fpga_pre_config_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
||||
|
||||
ngcc_fpga_reset(TRUE);
|
||||
FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
|
||||
|
||||
ngcc_fpga_reset(TRUE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||
* the FPGA appears to be running.
|
||||
*/
|
||||
int ngcc_fpga_post_config_fn(int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
|
||||
|
||||
udelay (100);
|
||||
ngcc_fpga_reset(FALSE);
|
||||
|
||||
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
if (assert_clk)
|
||||
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
|
||||
else
|
||||
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
|
||||
|
||||
return assert_clk;
|
||||
}
|
||||
|
||||
|
||||
int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||
{
|
||||
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||
|
||||
if (assert_write)
|
||||
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
|
||||
else
|
||||
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
|
||||
|
||||
return assert_write;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize the fpga. Return 1 on success, 0 on failure.
|
||||
*/
|
||||
int pmc440_init_fpga(void)
|
||||
{
|
||||
char *s;
|
||||
|
||||
debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
|
||||
__FUNCTION__, __LINE__, gd->reloc_off);
|
||||
fpga_init(gd->reloc_off);
|
||||
|
||||
fpga_serialslave_init ();
|
||||
debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
|
||||
fpga_add (fpga_xilinx, &fpga[0]);
|
||||
|
||||
/* NGCC only */
|
||||
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
|
||||
ngcc_fpga_serialslave_init ();
|
||||
debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
|
||||
fpga_add (fpga_xilinx, &fpga[1]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_FPGA */
|
||||
47
board/esd/pmc440/fpga.h
Normal file
47
board/esd/pmc440/fpga.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
extern int pmc440_init_fpga(void);
|
||||
|
||||
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
|
||||
extern int fpga_init_fn(int cookie);
|
||||
extern int fpga_err_fn(int cookie);
|
||||
extern int fpga_done_fn(int cookie);
|
||||
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
|
||||
extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
|
||||
extern int fpga_wr_fn(int assert_write, int flush, int cookie);
|
||||
extern int fpga_wdata_fn (uchar data, int flush, int cookie);
|
||||
extern int fpga_read_data_fn(unsigned char *data, int cookie);
|
||||
extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
|
||||
extern int fpga_busy_fn(int cookie);
|
||||
extern int fpga_abort_fn(int cookie );
|
||||
extern int fpga_pre_config_fn(int cookie );
|
||||
extern int fpga_post_config_fn(int cookie );
|
||||
|
||||
extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
|
||||
extern int ngcc_fpga_init_fn(int cookie);
|
||||
extern int ngcc_fpga_done_fn(int cookie);
|
||||
extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
|
||||
extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
|
||||
extern int ngcc_fpga_pre_config_fn(int cookie );
|
||||
extern int ngcc_fpga_post_config_fn(int cookie );
|
||||
122
board/esd/pmc440/init.S
Normal file
122
board/esd/pmc440/init.S
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm-ppc/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
#else
|
||||
tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB-entry for DDR SDRAM (Up to 2GB) */
|
||||
#ifdef CONFIG_4xx_DCACHE
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
#else
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
#endif
|
||||
|
||||
#ifdef CFG_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* TLB-entries for EBC */
|
||||
/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
|
||||
* tlb entry.
|
||||
* This dummy entry is only for convinience in order not to modify the
|
||||
* amount of entries. Currently OS/9 relies on this :-)
|
||||
*/
|
||||
tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for NAND */
|
||||
tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* TLB-entry PCI IO space */
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* TODO: what about high IO space */
|
||||
tlbtab_end
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
/*
|
||||
* For NAND booting the first TLB has to be reconfigured to full size
|
||||
* and with caching disabled after running from RAM!
|
||||
*/
|
||||
#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
|
||||
#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
|
||||
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
.globl reconfig_tlb0
|
||||
reconfig_tlb0:
|
||||
sync
|
||||
isync
|
||||
addi r4,r0,0x0000 /* TLB entry #0 */
|
||||
lis r5,TLB00@h
|
||||
ori r5,r5,TLB00@l
|
||||
tlbwe r5,r4,0x0000 /* Save it out */
|
||||
lis r5,TLB01@h
|
||||
ori r5,r5,TLB01@l
|
||||
tlbwe r5,r4,0x0001 /* Save it out */
|
||||
lis r5,TLB02@h
|
||||
ori r5,r5,TLB02@l
|
||||
tlbwe r5,r4,0x0002 /* Save it out */
|
||||
sync
|
||||
isync
|
||||
blr
|
||||
#endif
|
||||
898
board/esd/pmc440/pmc440.c
Normal file
898
board/esd/pmc440/pmc440.c
Normal file
|
|
@ -0,0 +1,898 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||
* Based on board/amcc/sequoia/sequoia.c
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <ppc440.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <i2c.h>
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
#include <miiphy.h>
|
||||
#endif
|
||||
#include <serial.h>
|
||||
#include "fpga.h"
|
||||
#include "pmc440.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
ulong flash_get_size(ulong base, int banknum);
|
||||
int pci_is_66mhz(void);
|
||||
int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
|
||||
|
||||
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
uchar buf[4];
|
||||
ulong delay;
|
||||
int i;
|
||||
ulong val;
|
||||
|
||||
/*
|
||||
* Use default console on P4 when strapping jumper
|
||||
* is installed (bootstrap option != 'H').
|
||||
*/
|
||||
mfsdr(SDR_PINSTP, val);
|
||||
if (((val & 0xf0000000) >> 29) != 7)
|
||||
return &serial1_device;
|
||||
|
||||
ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
|
||||
if (!(scratchreg & 0x80)) {
|
||||
/* mark scratchreg valid */
|
||||
scratchreg = (scratchreg & 0xffffff00) | 0x80;
|
||||
|
||||
i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
|
||||
if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
|
||||
scratchreg |= buf[2];
|
||||
|
||||
/* bringup delay for console */
|
||||
for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
|
||||
udelay(1000);
|
||||
}
|
||||
} else
|
||||
scratchreg |= 0x01;
|
||||
out_be32((void*)GPIO0_ISR3L, scratchreg);
|
||||
}
|
||||
|
||||
if (scratchreg & 0x01)
|
||||
return &serial1_device;
|
||||
else
|
||||
return &serial0_device;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
u32 sdr0_cust0;
|
||||
u32 sdr0_pfc1, sdr0_pfc2;
|
||||
u32 reg;
|
||||
|
||||
/* general EBC configuration (disable EBC timeouts) */
|
||||
mtdcr(ebccfga, xbcfg);
|
||||
mtdcr(ebccfgd, 0xf8400000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the GPIO pins
|
||||
* TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
|
||||
*-------------------------------------------------------------------*/
|
||||
out32(GPIO0_OR, 0x40000002);
|
||||
out32(GPIO0_TCR, 0x4c90011f);
|
||||
out32(GPIO0_OSRL, 0x28011400);
|
||||
out32(GPIO0_OSRH, 0x55005000);
|
||||
out32(GPIO0_TSRL, 0x08011400);
|
||||
out32(GPIO0_TSRH, 0x55005000);
|
||||
out32(GPIO0_ISR1L, 0x54000000);
|
||||
out32(GPIO0_ISR1H, 0x00000000);
|
||||
out32(GPIO0_ISR2L, 0x44000000);
|
||||
out32(GPIO0_ISR2H, 0x00000100);
|
||||
out32(GPIO0_ISR3L, 0x00000000);
|
||||
out32(GPIO0_ISR3H, 0x00000000);
|
||||
|
||||
out32(GPIO1_OR, 0x80002408);
|
||||
out32(GPIO1_TCR, 0xd6003c08);
|
||||
out32(GPIO1_OSRL, 0x0a5a0000);
|
||||
out32(GPIO1_OSRH, 0x00000000);
|
||||
out32(GPIO1_TSRL, 0x00000000);
|
||||
out32(GPIO1_TSRH, 0x00000000);
|
||||
out32(GPIO1_ISR1L, 0x00005555);
|
||||
out32(GPIO1_ISR1H, 0x40000000);
|
||||
out32(GPIO1_ISR2L, 0x04010000);
|
||||
out32(GPIO1_ISR2H, 0x00000000);
|
||||
out32(GPIO1_ISR3L, 0x01400000);
|
||||
out32(GPIO1_ISR3H, 0x00000000);
|
||||
|
||||
/* patch PLB:PCI divider for 66MHz PCI */
|
||||
mfcpr(clk_spcid, reg);
|
||||
if (pci_is_66mhz() && (reg != 0x02000000)) {
|
||||
mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
|
||||
|
||||
mfcpr(clk_icfg, reg);
|
||||
reg |= CPR0_ICFG_RLI_MASK;
|
||||
mtcpr(clk_icfg, reg);
|
||||
|
||||
mtspr(dbcr0, 0x20000000); /* do chip reset */
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
|
||||
mtdcr(uic0pr, 0xfffff7ef);
|
||||
mtdcr(uic0tr, 0x00000000);
|
||||
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic1pr, 0xffffc7f5);
|
||||
mtdcr(uic1tr, 0x00000000);
|
||||
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic2er, 0x00000000); /* disable all */
|
||||
mtdcr(uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic2pr, 0x27ffffff);
|
||||
mtdcr(uic2tr, 0x00000000);
|
||||
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
|
||||
/* select Ethernet pins */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
|
||||
mfsdr(SDR0_PFC2, sdr0_pfc2);
|
||||
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
|
||||
|
||||
/* enable 2nd IIC */
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
|
||||
|
||||
mtsdr(SDR0_PFC2, sdr0_pfc2);
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
|
||||
/* setup NAND FLASH */
|
||||
mfsdr(SDR0_CUST0, sdr0_cust0);
|
||||
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
|
||||
SDR0_CUST0_NDFC_ENABLE |
|
||||
SDR0_CUST0_NDFC_BW_8_BIT |
|
||||
SDR0_CUST0_NDFC_ARE_MASK |
|
||||
(0x80000000 >> (28 + CFG_NAND_CS));
|
||||
mtsdr(SDR0_CUST0, sdr0_cust0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
| misc_init_r.
|
||||
+---------------------------------------------------------------------------*/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
uint pbcr;
|
||||
int size_val = 0;
|
||||
u32 reg;
|
||||
unsigned long usb2d0cr = 0;
|
||||
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||
unsigned long sdr0_pfc1;
|
||||
char *act = getenv("usbact");
|
||||
|
||||
/*
|
||||
* FLASH stuff...
|
||||
*/
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
mtdcr(ebccfga, pb2cr);
|
||||
#else
|
||||
mtdcr(ebccfga, pb0cr);
|
||||
#endif
|
||||
pbcr = mfdcr(ebccfgd);
|
||||
switch (gd->bd->bi_flashsize) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
case 32 << 20:
|
||||
size_val = 5;
|
||||
break;
|
||||
case 64 << 20:
|
||||
size_val = 6;
|
||||
break;
|
||||
case 128 << 20:
|
||||
size_val = 7;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
mtdcr(ebccfga, pb2cr);
|
||||
#else
|
||||
mtdcr(ebccfga, pb0cr);
|
||||
#endif
|
||||
mtdcr(ebccfgd, pbcr);
|
||||
|
||||
/*
|
||||
* Re-check to get correct base address
|
||||
*/
|
||||
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB suff...
|
||||
*/
|
||||
if ((act == NULL || strcmp(act, "hostdev") == 0) &&
|
||||
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
|
||||
/* SDR Setting */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
|
||||
|
||||
/* An 8-bit/60MHz interface is the only possible alternative
|
||||
when connecting the Device to the PHY */
|
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||
|
||||
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
||||
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
/*clear resets*/
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST1, 0x00000000);
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST0, 0x00000000);
|
||||
|
||||
printf("USB: Host\n");
|
||||
|
||||
} else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
|
||||
/*-------------------PATCH-------------------------------*/
|
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
|
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
|
||||
udelay (1000);
|
||||
mtsdr(SDR0_SRST1, 0x672c6000);
|
||||
|
||||
udelay (1000);
|
||||
mtsdr(SDR0_SRST0, 0x00000080);
|
||||
|
||||
udelay (1000);
|
||||
mtsdr(SDR0_SRST1, 0x60206000);
|
||||
|
||||
*(unsigned int *)(0xe0000350) = 0x00000001;
|
||||
|
||||
udelay (1000);
|
||||
mtsdr(SDR0_SRST1, 0x60306000);
|
||||
/*-------------------PATCH-------------------------------*/
|
||||
|
||||
/* SDR Setting */
|
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
|
||||
|
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
|
||||
|
||||
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||
|
||||
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
||||
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
|
||||
|
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
|
||||
/*clear resets*/
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST1, 0x00000000);
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST0, 0x00000000);
|
||||
|
||||
printf("USB: Device\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear PLB4A0_ACR[WRP]
|
||||
* This fix will make the MAL burst disabling patch for the Linux
|
||||
* EMAC driver obsolete.
|
||||
*/
|
||||
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
|
||||
mtdcr(plb4_acr, reg);
|
||||
|
||||
#ifdef CONFIG_FPGA
|
||||
pmc440_init_fpga();
|
||||
#endif
|
||||
|
||||
/* turn off POST LED */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
|
||||
/* turn on RUN LED */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int is_monarch(void)
|
||||
{
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int pci_is_66mhz(void)
|
||||
{
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_revision(void)
|
||||
{
|
||||
return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: esd GmbH - PMC440");
|
||||
|
||||
gd->board_type = board_revision();
|
||||
printf(", Rev 1.%ld, ", gd->board_type);
|
||||
|
||||
if (!is_monarch()) {
|
||||
puts("non-");
|
||||
}
|
||||
|
||||
printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
|
||||
/*
|
||||
* Assign interrupts to PCI devices. Some OSs rely on this.
|
||||
*/
|
||||
void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||
{
|
||||
unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
|
||||
|
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
|
||||
int_line[PCI_DEV(dev) & 0x03]);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0.
|
||||
| Set PLB3 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp1, addr);
|
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb3_acr);
|
||||
mtdcr(plb3_acr, addr | 0x80000000);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp0, addr);
|
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||
mtdcr(plb4_acr, addr);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------------*/
|
||||
/* Segment0 */
|
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
|
||||
mtdcr(plb0_acr, addr);
|
||||
|
||||
/* Segment1 */
|
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
||||
mtdcr(plb1_acr, addr);
|
||||
|
||||
#ifdef CONFIG_PCI_PNP
|
||||
hose->fixup_irq = pmc440_pci_fixup_irq;
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller *hose)
|
||||
{
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers
|
||||
*--------------------------------------------------------------------------*/
|
||||
/*--------------------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration.
|
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
| PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
|
||||
| Use byte reversed out routines to handle endianess.
|
||||
| Make this region non-prefetchable.
|
||||
+--------------------------------------------------------------------------*/
|
||||
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */
|
||||
|
||||
if (!is_monarch()) {
|
||||
/* BAR1: top 64MB of RAM */
|
||||
out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */
|
||||
} else {
|
||||
/* BAR1: complete 256MB RAM (TODO: make dynamic) */
|
||||
out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */
|
||||
}
|
||||
|
||||
/* BAR2: 16 MB FPGA registers */
|
||||
out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
|
||||
|
||||
if (is_monarch()) {
|
||||
/* BAR2: map FPGA registers behind system memory at 1GB */
|
||||
pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Configuration registers
|
||||
*--------------------------------------------------------------------------*/
|
||||
|
||||
/* Program the board's vendor id */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CFG_PCI_SUBSYS_VENDORID);
|
||||
|
||||
#if 0 /* disabled for PMC405 backward compatibility */
|
||||
/* Configure command register as bus master */
|
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
#endif
|
||||
|
||||
/* 240nS PCI clock */
|
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||
|
||||
/* No error reporting */
|
||||
pci_write_config_word(0, PCI_ERREN, 0);
|
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
|
||||
if (!is_monarch()) {
|
||||
/* Program the board's subsystem id/classcode */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
|
||||
CFG_PCI_SUBSYS_ID_NONMONARCH);
|
||||
pci_write_config_word(0, PCI_CLASS_SUB_CODE,
|
||||
CFG_PCI_CLASSCODE_NONMONARCH);
|
||||
|
||||
/* PCI configuration done: release ERREADY */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
|
||||
out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
|
||||
} else {
|
||||
/* Program the board's subsystem id/classcode */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
|
||||
CFG_PCI_SUBSYS_ID_MONARCH);
|
||||
pci_write_config_word(0, PCI_CLASS_SUB_CODE,
|
||||
CFG_PCI_CLASSCODE_MONARCH);
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||
void pci_master_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned short temp_short;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs.
|
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
+--------------------------------------------------------------------------*/
|
||||
if (is_monarch()) {
|
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
temp_short | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY);
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
||||
|
||||
|
||||
static void wait_for_pci_ready(void)
|
||||
{
|
||||
int i;
|
||||
char *s = getenv("pcidelay");
|
||||
if (s) {
|
||||
int ms = simple_strtoul(s, NULL, 10);
|
||||
printf("PCI: Waiting for %d ms\n", ms);
|
||||
for (i=0; i<ms; i++)
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
|
||||
printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
|
||||
while (1) {
|
||||
if (ctrlc()) {
|
||||
puts("abort\n");
|
||||
break;
|
||||
}
|
||||
if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
|
||||
printf("done\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
char *s = getenv("pciscan");
|
||||
if (s == NULL)
|
||||
if (is_monarch()) {
|
||||
wait_for_pci_ready();
|
||||
return 1;
|
||||
} else
|
||||
return 0;
|
||||
else if (!strcmp(s, "yes"))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
void reset_phy(void)
|
||||
{
|
||||
if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
|
||||
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
|
||||
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
|
||||
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
|
||||
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
|
||||
}
|
||||
|
||||
if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
|
||||
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
|
||||
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
|
||||
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
|
||||
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable(unsigned dev_addr, int state)
|
||||
{
|
||||
if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO_SINT2. */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO_SINT2. */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||
|
||||
|
||||
#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
|
||||
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
|
||||
{
|
||||
unsigned end = offset + cnt;
|
||||
unsigned blk_off;
|
||||
int rcode = 0;
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
eeprom_write_enable(dev_addr, 1);
|
||||
#endif
|
||||
/* Write data until done or would cross a write page boundary.
|
||||
* We must write the address again when changing pages
|
||||
* because the address counter only increments within a page.
|
||||
*/
|
||||
|
||||
while (offset < end) {
|
||||
unsigned alen, len;
|
||||
unsigned maxlen;
|
||||
uchar addr[2];
|
||||
|
||||
blk_off = offset & 0xFF; /* block offset */
|
||||
|
||||
addr[0] = offset >> 8; /* block number */
|
||||
addr[1] = blk_off; /* block offset */
|
||||
alen = 2;
|
||||
addr[0] |= dev_addr; /* insert device address */
|
||||
|
||||
len = end - offset;
|
||||
|
||||
#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
|
||||
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
|
||||
|
||||
maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
|
||||
if (maxlen > I2C_RXTX_LEN)
|
||||
maxlen = I2C_RXTX_LEN;
|
||||
|
||||
if (len > maxlen)
|
||||
len = maxlen;
|
||||
|
||||
if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
|
||||
rcode = 1;
|
||||
|
||||
buffer += len;
|
||||
offset += len;
|
||||
|
||||
#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
|
||||
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
|
||||
#endif
|
||||
}
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
eeprom_write_enable(dev_addr, 0);
|
||||
#endif
|
||||
return rcode;
|
||||
}
|
||||
|
||||
|
||||
int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
|
||||
{
|
||||
unsigned end = offset + cnt;
|
||||
unsigned blk_off;
|
||||
int rcode = 0;
|
||||
|
||||
/* Read data until done or would cross a page boundary.
|
||||
* We must write the address again when changing pages
|
||||
* because the next page may be in a different device.
|
||||
*/
|
||||
while (offset < end) {
|
||||
unsigned alen, len;
|
||||
unsigned maxlen;
|
||||
uchar addr[2];
|
||||
|
||||
blk_off = offset & 0xFF; /* block offset */
|
||||
|
||||
addr[0] = offset >> 8; /* block number */
|
||||
addr[1] = blk_off; /* block offset */
|
||||
alen = 2;
|
||||
|
||||
addr[0] |= dev_addr; /* insert device address */
|
||||
|
||||
len = end - offset;
|
||||
|
||||
maxlen = 0x100 - blk_off;
|
||||
if (maxlen > I2C_RXTX_LEN)
|
||||
maxlen = I2C_RXTX_LEN;
|
||||
if (len > maxlen)
|
||||
len = maxlen;
|
||||
|
||||
if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
|
||||
rcode = 1;
|
||||
buffer += len;
|
||||
offset += len;
|
||||
}
|
||||
|
||||
return rcode;
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
|
||||
int usb_board_init(void)
|
||||
{
|
||||
char *act = getenv("usbact");
|
||||
int i;
|
||||
|
||||
if ((act == NULL || strcmp(act, "hostdev") == 0) &&
|
||||
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
|
||||
/* enable power on USB socket */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
|
||||
|
||||
for (i=0; i<1000; i++)
|
||||
udelay(1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_stop(void)
|
||||
{
|
||||
/* disable power on USB socket */
|
||||
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_board_init_fail(void)
|
||||
{
|
||||
usb_board_stop();
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* Fixup NOR mapping */
|
||||
val[0] = 0; /* chip select number */
|
||||
val[1] = 0; /* always 0 */
|
||||
val[2] = gd->bd->bi_flashstart;
|
||||
val[3] = gd->bd->bi_flashsize;
|
||||
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||
val, sizeof(val), 1);
|
||||
if (rc)
|
||||
printf("Unable to update property NOR mapping, err=%s\n",
|
||||
fdt_strerror(rc));
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
154
board/esd/pmc440/pmc440.h
Normal file
154
board/esd/pmc440/pmc440.h
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __PMC440_H__
|
||||
#define __PMC440_H__
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIOs
|
||||
*/
|
||||
#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
|
||||
#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
|
||||
#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
|
||||
#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
|
||||
#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
|
||||
#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
|
||||
#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
|
||||
|
||||
#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
|
||||
#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
|
||||
#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
|
||||
#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
|
||||
#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
|
||||
#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
|
||||
|
||||
/* FPGA programming pin configuration */
|
||||
#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
|
||||
#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
|
||||
#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
|
||||
#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
|
||||
#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
|
||||
#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA interface
|
||||
*/
|
||||
#define FPGA_BA CFG_FPGA_BASE0
|
||||
#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
|
||||
#define FPGA_IN32(p) in_be32((void*)(p))
|
||||
#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
|
||||
#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
|
||||
|
||||
struct pmc440_fifo_s {
|
||||
u32 data;
|
||||
u32 ctrl;
|
||||
};
|
||||
|
||||
/* fifo ctrl register */
|
||||
#define FIFO_IE (1 << 15)
|
||||
#define FIFO_OVERFLOW (1 << 10)
|
||||
#define FIFO_EMPTY (1 << 9)
|
||||
#define FIFO_FULL (1 << 8)
|
||||
#define FIFO_LEVEL_MASK 0x000000ff
|
||||
|
||||
#define FIFO_COUNT 4
|
||||
|
||||
struct pmc440_fpga_s {
|
||||
u32 ctrla;
|
||||
u32 status;
|
||||
u32 ctrlb;
|
||||
u32 pad1[0x40 / sizeof(u32) - 3];
|
||||
u32 irig_time; /* offset: 0x0040 */
|
||||
u32 irig_tod;
|
||||
u32 irig_cf;
|
||||
u32 pad2;
|
||||
u32 irig_rx_time; /* offset: 0x0050 */
|
||||
u32 pad3[3];
|
||||
u32 hostctrl; /* offset: 0x0060 */
|
||||
u32 pad4[0x20 / sizeof(u32) - 1];
|
||||
struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
|
||||
};
|
||||
|
||||
typedef struct pmc440_fpga_s pmc440_fpga_t;
|
||||
|
||||
/* ctrl register */
|
||||
#define CTRL_HOST_IE (1 << 8)
|
||||
|
||||
/* outputs */
|
||||
#define RESET_EN (1 << 31)
|
||||
#define CLOCK_EN (1 << 30)
|
||||
#define RESET_OUT (1 << 19)
|
||||
#define CLOCK_OUT (1 << 22)
|
||||
#define RESET_OUT (1 << 19)
|
||||
#define IRIGB_R_OUT (1 << 14)
|
||||
|
||||
|
||||
/* status register */
|
||||
#define STATUS_VERSION_SHIFT 24
|
||||
#define STATUS_VERSION_MASK 0xff000000
|
||||
#define STATUS_HWREV_SHIFT 20
|
||||
#define STATUS_HWREV_MASK 0x00f00000
|
||||
|
||||
#define STATUS_CAN_ISF (1 << 11)
|
||||
#define STATUS_CSTM_ISF (1 << 10)
|
||||
#define STATUS_FIFO_ISF (1 << 9)
|
||||
#define STATUS_HOST_ISF (1 << 8)
|
||||
|
||||
|
||||
/* inputs */
|
||||
#define RESET_IN (1 << 0)
|
||||
#define CLOCK_IN (1 << 1)
|
||||
#define IRIGB_R_IN (1 << 5)
|
||||
|
||||
|
||||
/* hostctrl register */
|
||||
#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
|
||||
#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
|
||||
#define HOSTCTRL_CSTM1IE_GATE (1 << 7)
|
||||
#define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
|
||||
#define HOSTCTRL_CSTM0IE_GATE (1 << 5)
|
||||
#define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
|
||||
#define HOSTCTRL_FIFOIE_GATE (1 << 3)
|
||||
#define HOSTCTRL_FIFOIE_FLAG (1 << 2)
|
||||
#define HOSTCTRL_HCINT_GATE (1 << 1)
|
||||
#define HOSTCTRL_HCINT_FLAG (1 << 0)
|
||||
|
||||
#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000)
|
||||
#define NGCC_CTRL_FPGARST_N (1 << 2)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA to PPC interrupt
|
||||
*/
|
||||
#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
|
||||
#define IRQ1_FPGA (32+30) /* UIC1 - custom module */
|
||||
#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
|
||||
#define IRQ_ETH0 (64+ 4) /* UIC2 */
|
||||
#define IRQ_ETH1 ( 27) /* UIC0 */
|
||||
#define IRQ_RTC (64+ 0) /* UIC2 */
|
||||
#define IRQ_PCIA (64+ 1) /* UIC2 */
|
||||
#define IRQ_PCIB (32+18) /* UIC1 */
|
||||
#define IRQ_PCIC (32+19) /* UIC1 */
|
||||
#define IRQ_PCID (32+20) /* UIC1 */
|
||||
|
||||
#endif /* __PMC440_H__ */
|
||||
108
board/esd/pmc440/sdram.c
Normal file
108
board/esd/pmc440/sdram.c
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* (C) Copyright 2006-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* define DEBUG for debug output */
|
||||
#undef DEBUG
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
extern int denali_wait_for_dlllock(void);
|
||||
extern void denali_core_search_data_eye(void);
|
||||
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
|
||||
* for the 4k NAND boot image so define bus_frequency to 133MHz here
|
||||
* which is save for the refresh counter setup.
|
||||
*/
|
||||
#define get_bus_freq(val) 133000000
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
*
|
||||
************************************************************************/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
#if !defined(CONFIG_NAND_SPL)
|
||||
ulong speed = get_bus_freq(0);
|
||||
#else
|
||||
ulong speed = 133333333; /* 133MHz is on the safe side */
|
||||
#endif
|
||||
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
mtsdram(DDR0_00, 0x0000190A);
|
||||
mtsdram(DDR0_01, 0x01000000);
|
||||
mtsdram(DDR0_03, 0x02030602);
|
||||
mtsdram(DDR0_04, 0x0A020200);
|
||||
mtsdram(DDR0_05, 0x02020308);
|
||||
mtsdram(DDR0_06, 0x0102C812);
|
||||
mtsdram(DDR0_07, 0x000D0100);
|
||||
mtsdram(DDR0_08, 0x02430001);
|
||||
mtsdram(DDR0_09, 0x00011D5F);
|
||||
mtsdram(DDR0_10, 0x00000300);
|
||||
mtsdram(DDR0_11, 0x0027C800);
|
||||
mtsdram(DDR0_12, 0x00000003);
|
||||
mtsdram(DDR0_14, 0x00000000);
|
||||
mtsdram(DDR0_17, 0x19000000);
|
||||
mtsdram(DDR0_18, 0x19191919);
|
||||
mtsdram(DDR0_19, 0x19191919);
|
||||
mtsdram(DDR0_20, 0x0B0B0B0B);
|
||||
mtsdram(DDR0_21, 0x0B0B0B0B);
|
||||
mtsdram(DDR0_22, 0x00267F0B);
|
||||
mtsdram(DDR0_23, 0x00000000);
|
||||
mtsdram(DDR0_24, 0x01010002);
|
||||
if (speed > 133333334)
|
||||
mtsdram(DDR0_26, 0x5B26050C);
|
||||
else
|
||||
mtsdram(DDR0_26, 0x5B260408);
|
||||
mtsdram(DDR0_27, 0x0000682B);
|
||||
mtsdram(DDR0_28, 0x00000000);
|
||||
mtsdram(DDR0_31, 0x00000000);
|
||||
mtsdram(DDR0_42, 0x01000006);
|
||||
mtsdram(DDR0_43, 0x030A0200);
|
||||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
|
||||
denali_wait_for_dlllock();
|
||||
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/* -----------------------------------------------------------+
|
||||
* Perform data eye search if requested.
|
||||
* ----------------------------------------------------------*/
|
||||
denali_core_search_data_eye();
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
137
board/esd/pmc440/u-boot-nand.lds
Normal file
137
board/esd/pmc440/u-boot-nand.lds
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
/* Align to next NAND block */
|
||||
. = ALIGN(0x4000);
|
||||
common/environment.o (.ppcenv)
|
||||
/* Keep some space here for redundant env and potential bad env blocks */
|
||||
. = ALIGN(0x10000);
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -28,13 +28,11 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
|
|||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
/* .resetvec 0x01FFFFFC :*/
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
/* .bootpg 0x01FFF000 :*/
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
|
@ -69,20 +67,6 @@ SECTIONS
|
|||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/esd/cpci440/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
|
|
@ -95,7 +79,6 @@ SECTIONS
|
|||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
|
|
@ -154,6 +137,9 @@ SECTIONS
|
|||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/4xx_enet.o (.text)
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
|
@ -112,11 +113,11 @@ int misc_init_f (void)
|
|||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||
volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||
volatile unsigned short *lcd_contrast =
|
||||
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||
unsigned short *lcd_contrast =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
|
||||
volatile unsigned short *lcd_backlight =
|
||||
unsigned short *lcd_backlight =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
|
||||
unsigned char *dst;
|
||||
ulong len = sizeof(fpgadata);
|
||||
|
|
@ -180,25 +181,37 @@ int misc_init_r (void)
|
|||
/*
|
||||
* Reset FPGA via FPGA_INIT pin
|
||||
*/
|
||||
out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Reset external DUARTs
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Setup EEPROM write protection
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
*duart0_mcr = 0x08;
|
||||
*duart1_mcr = 0x08;
|
||||
out_8(duart0_mcr, 0x08);
|
||||
out_8(duart1_mcr, 0x08);
|
||||
|
||||
/*
|
||||
* Init lcd interface and display logo
|
||||
|
|
@ -240,17 +253,23 @@ int misc_init_r (void)
|
|||
/*
|
||||
* Set invert bit in small lcd controller
|
||||
*/
|
||||
*(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
|
||||
out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
|
||||
in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
|
||||
|
||||
/*
|
||||
* Set default contrast voltage on epson vga controller
|
||||
*/
|
||||
*lcd_contrast = 0x4646;
|
||||
out_be16(lcd_contrast, 0x4646);
|
||||
|
||||
/*
|
||||
* Enable backlight
|
||||
*/
|
||||
*lcd_backlight = 0xffff;
|
||||
out_be16(lcd_backlight, 0xffff);
|
||||
|
||||
/*
|
||||
* Enable external I2C bus
|
||||
*/
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -281,11 +300,6 @@ int checkboard (void)
|
|||
|
||||
putc ('\n');
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -334,3 +348,86 @@ void ide_set_reset(int on)
|
|||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable (unsigned dev_addr, int state)
|
||||
{
|
||||
if (CFG_I2C_EEPROM_ADDR != dev_addr) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts ("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts ("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||
NULL);
|
||||
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ SECTIONS
|
|||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/4xx_uart.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue