Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-28 23:51:33 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx

Browse source
This commit is contained in:
Wolfgang Denk 2008-02-22 13:03:28 +01:00
commit 6a2dcaf1ee
12 changed files with 110 additions and 116 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View file

@ -280,13 +280,14 @@ void pci_init_board(void)
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
>> MPC8610_PORDEVSR_IO_SEL_SHIFT;
uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
>> MPC8610_PORBMSR_HA_SHIFT;
printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;

24
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View file

@ -206,7 +206,8 @@ void pci_init_board(void)
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
#ifdef CONFIG_PCI1
{
@ -214,7 +215,8 @@ void pci_init_board(void)
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
#endif
if ((io_sel == 2 || io_sel == 3 || io_sel == 5
@ -321,28 +323,16 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
fdt_fixup_ethernet(blob, bd);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", bd->bi_busfreq, 1);
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
ft_cpu_setup(blob, bd);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;

41
board/sbc8641d/sbc8641d.c
View file

@ -35,11 +35,8 @@
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
#include <spd.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup (void *blob, bd_t * bd);
#endif
#include <libfdt.h>
#include <fdt_support.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc (unsigned int dram_size);
@ -341,18 +338,34 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup (void *blob, bd_t * bd)
#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
int node, tmp[2];
const char *path;
ft_cpu_setup (blob, bd);
ft_cpu_setup(blob, bd);
p = ft_get_prop (blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32 (bd->bi_memstart);
*p = cpu_to_be32 (bd->bi_memsize);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
#endif
#ifdef CONFIG_PCI2
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
#endif
}
}
#endif

17
cpu/mpc86xx/Makefile
View file

@ -28,13 +28,20 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o #resetvec.o
START = start.o
SOBJS = cache.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
spd_sdram.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
COBJS-y += traps.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
COBJS-y += speed.o
COBJS-y += interrupts.o
COBJS-y += spd_sdram.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)

61
cpu/mpc86xx/cpu.c
View file

@ -29,9 +29,6 @@
#include <mpc86xx.h>
#include <asm/fsl_law.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
int
checkcpu(void)
@ -269,64 +266,6 @@ dma_xfer(void *dest, uint count, void *src)
#endif /* CONFIG_DDR_ECC */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup(void *blob, bd_t *bd)
{
u32 *p;
ulong clock;
int len;
clock = bd->bi_busfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
if (p)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#if defined(CONFIG_TSEC3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet2addr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet2addr, 6);
#endif
#if defined(CONFIG_TSEC4)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6);
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6);
#endif
#endif /* CONFIG_OF_FLAT_TREE */
/*
* Print out the state of various machine registers.
* Currently prints out LAWs and BR0/OR0

1
cpu/mpc86xx/cpu_init.c
View file

@ -28,6 +28,7 @@
#include <common.h>
#include <mpc86xx.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;

35
cpu/mpc86xx/fdt.c Normal file
View file

@ -0,0 +1,35 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
void ft_cpu_setup(void *blob, bd_t *bd)
{
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \
|| defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
fdt_fixup_ethernet(blob, bd);
#endif
#ifdef CFG_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", bd->bi_busfreq, 1);
#endif
}

10
cpu/mpc86xx/spd_sdram.c
View file

@ -943,7 +943,7 @@ unsigned int enable_ddr(unsigned int ddr_num)
spd_eeprom_t spd1,spd2;
volatile ccsr_ddr_t *ddr;
unsigned sdram_cfg_1;
unsigned char sdram_type, mem_type, config, mod_attr;
unsigned char sdram_type, mem_type, mod_attr;
unsigned char d_init;
unsigned int no_dimm1=0, no_dimm2=0;
@ -1017,6 +1017,10 @@ unsigned int enable_ddr(unsigned int ddr_num)
printf("No memory modules found for DDR controller %d!!\n", ddr_num);
return 0;
} else {
#if defined(CONFIG_DDR_ECC)
unsigned char config;
#endif
mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
/*
@ -1122,8 +1126,8 @@ spd_sdram(void)
int memsize_ddr1_dimm2 = 0;
int memsize_ddr1 = 0;
unsigned int law_size_ddr1;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#ifdef CONFIG_DDR_INTERLEAVE
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
#endif
@ -1183,7 +1187,6 @@ spd_sdram(void)
#endif
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
#ifdef CONFIG_DDR_INTERLEAVE
#if (CFG_PAGE_INTERLEAVING == 1)
printf("Page ");
#elif (CFG_BANK_INTERLEAVING == 1)
@ -1192,7 +1195,6 @@ spd_sdram(void)
printf("Super-bank ");
#else
printf("Cache-line ");
#endif
#endif
printf("Interleaved");
return memsize_total * 1024 * 1024;

6
doc/README.mpc8610hpcd
View file

@ -65,3 +65,9 @@ Examples;
* 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
*/
pixis-reset altbank cf 40 2.5 10
DIP Switch Settings
-------------------
To manually switch the flash banks using the DIP switch
settings, toggle both SW6:1 and SW6:2.

12
include/asm-ppc/immap_86xx.h
View file

@ -1256,12 +1256,16 @@ typedef struct ccsr_rio {
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA 0x00060000
#define MPC85xx_PORBMSR_HA 0x00070000
#define MPC8610_PORBMSR_HA 0x00070000
#define MPC8610_PORBMSR_HA_SHIFT 16
#define MPC8641_PORBMSR_HA 0x00060000
#define MPC8641_PORBMSR_HA_SHIFT 17
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
#define MPC8610_PORDEVSR_IO_SEL 0x00380000
#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
#define MPC8641_PORDEVSR_IO_SEL 0x000F0000
#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];

2
include/configs/MPC8610HPCD.h
View file

@ -24,7 +24,7 @@
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
/* video */
#define CONFIG_VIDEO
#undef CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_CFB_CONSOLE

10
include/configs/sbc8641d.h
View file

@ -268,13 +268,9 @@
/*
* Pass open firmware flat tree to kernel
*/
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc@f8000000/serial@4500"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1