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SoC: exynos: add support for exynos 78x0
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Dzmitry Sankouski
Tom Rini
parent
d8428f73c3
commit
69bde0410a
9 changed files with 889 additions and 0 deletions
204
arch/arm/dts/exynos78x0-gpio.dtsi
Normal file
204
arch/arm/dts/exynos78x0-gpio.dtsi
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@ -0,0 +1,204 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Samsung's Exynos7880 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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/* ALIVE */
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gpio@139F0000 {
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etc0: etc0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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etc1: etc1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpa0: gpa0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpa1: gpa1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpa2: gpa2 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpa3: gpa3 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpq0: gpq0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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/* CCORE */
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gpio@10630000 {
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gpm0: gpm0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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/* DISP/AUD */
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gpio@148C0000 {
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gpz0: gpz0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpz1: gpz1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpz2: gpz2 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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/* FSYS0 */
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gpio@13750000 {
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gpr0: gpr0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpr1: gpr1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpr2: gpr2 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpr3: gpr3 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpr4: gpr4 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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/* TOP */
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gpio@139B0000 {
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gpb0: gpb0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc0: gpc0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc1: gpc1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc4: gpc4 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc5: gpc5 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc6: gpc6 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc8: gpc8 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpc9: gpc9 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpd1: gpd1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpd2: gpd2 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpd3: gpd3 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpd4: gpd4 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpd5: gpd5 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpe0: gpe0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpf0: gpf0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpf1: gpf1 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpf2: gpf2 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpf3: gpf3 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpf4: gpf4 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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280
arch/arm/dts/exynos78x0-pinctrl.dtsi
Normal file
280
arch/arm/dts/exynos78x0-pinctrl.dtsi
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@ -0,0 +1,280 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Samsung's Exynos7880 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
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*
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* Samsung's Exynos7880 SoC pin-mux and pin-config options are listed as device
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* tree nodes are listed in this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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/* ALIVE */
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pinctrl@139F0000 {
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uart2_bus: uart2-bus {
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samsung,pins = "gpa1-1", "gpa1-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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};
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dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
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samsung,pins = "gpa3-3";
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <4>;
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};
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key_power: key-power {
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samsung,pins = "gpa0-0";
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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key_voldown: key-voldown {
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samsung,pins = "gpa2-1";
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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key_volup: key-volup {
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samsung,pins = "gpa2-0";
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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key_home: key-home {
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samsung,pins = "gpa1-7";
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samsung,pin-function = <0xf>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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};
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/* TOP */
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pinctrl@139B0000 {
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i2c0_bus: i2c0-bus {
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samsung,pins = "gpc1-1", "gpc1-0";
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samsung,pin-function = <2>;
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};
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sd0_rst: sd0_rst {
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samsung,pins = "gpc0-2";
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samsung,pin-function = <0>;
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};
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};
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/* DISP/AUD */
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pinctrl@148C0000 {
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i2s_pmic_bus: i2s-pmic-bus {
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samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4";
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samsung,pin-function = <2>;
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samsung,pin-pud = <1>;
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samsung,pin-drv = <0>;
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};
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i2s_pmic_bus_idle: i2s-pmic-bus_idle {
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samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4";
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samsung,pin-function = <0>;
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samsung,pin-pud = <1>;
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samsung,pin-drv = <0>;
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};
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};
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/* FSYS0 */
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pinctrl@13750000 {
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sd0_clk: sd0-clk {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd0_cmd: sd0-cmd {
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samsung,pins = "gpr0-1";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd0_rdqs: sd0-rdqs {
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samsung,pins = "gpr0-2";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd0_clk_fast_slew_rate_1x: sd0-clk_fast_slew_rate_1x {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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sd0_clk_fast_slew_rate_2x: sd0-clk_fast_slew_rate_2x {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <1>;
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};
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sd0_clk_fast_slew_rate_3x: sd0-clk_fast_slew_rate_3x {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd0_clk_fast_slew_rate_4x: sd0-clk_fast_slew_rate_4x {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <3>;
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};
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sd0_clk_fast_slew_rate_5x: sd0-clk_fast_slew_rate_5x {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <4>;
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};
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sd0_clk_fast_slew_rate_6x: sd0-clk_fast_slew_rate_6x {
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samsung,pins = "gpr0-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <5>;
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};
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sd0_bus1: sd0-bus-width1 {
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samsung,pins = "gpr1-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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};
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sd0_bus4: sd0-bus-width4 {
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samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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};
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sd0_bus8: sd0-bus-width8 {
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samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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};
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sd1_clk: sd1-clk {
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samsung,pins = "gpr2-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd1_cmd: sd1-cmd {
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samsung,pins = "gpr2-1";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd1_bus1: sd1-bus-width1 {
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samsung,pins = "gpr3-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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samsung,pin-con-pdn = <2>;
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samsung,pin-pud-pdn = <3>;
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};
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sd1_bus4: sd1-bus-width4 {
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samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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samsung,pin-con-pdn = <2>;
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samsung,pin-pud-pdn = <3>;
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};
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sd2_clk: sd2-clk {
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samsung,pins = "gpr4-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd2_cmd: sd2-cmd {
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samsung,pins = "gpr4-1";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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};
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sd2_bus1: sd2-bus-width1 {
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samsung,pins = "gpr4-2";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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};
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sd2_bus4: sd2-bus-width4 {
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samsung,pins = "gpr4-3", "gpr4-4", "gpr4-5";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <2>;
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};
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sd2_clk_output: sd2-clk-output {
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samsung,pins = "gpr4-0";
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samsung,pin-function = <1>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd2_cmd_output: sd2-cmd-output {
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samsung,pins = "gpr4-1";
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samsung,pin-function = <1>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x {
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samsung,pins = "gpr4-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x {
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samsung,pins = "gpr4-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <1>;
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};
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sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x {
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samsung,pins = "gpr4-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <2>;
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};
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sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x {
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samsung,pins = "gpr4-0";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
98
arch/arm/dts/exynos78x0.dtsi
Normal file
98
arch/arm/dts/exynos78x0.dtsi
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Samsung Exynos7880 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos78x0-pinctrl.dtsi"
|
||||
#include "exynos78x0-gpio.dtsi"
|
||||
/ {
|
||||
compatible = "samsung,exynos7880";
|
||||
|
||||
fin_pll: xxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "fin_pll";
|
||||
u-boot,dm-pre-reloc;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
/* Dummy clock for uart */
|
||||
fin_uart: uart_dummy_fin {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "fin_uart";
|
||||
clock-frequency = <132710400>;
|
||||
u-boot,dm-pre-reloc;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
uart2: serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
u-boot,dm-pre-reloc;
|
||||
clocks = <&fin_uart>, <&fin_uart>; // driver uses 1st clock
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_bus>;
|
||||
};
|
||||
|
||||
gpioi2c0: i2c-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "i2c-gpio";
|
||||
status = "disabled";
|
||||
gpios = <
|
||||
&gpc1 0 0 /* sda */
|
||||
&gpc1 1 0 /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
|
||||
s2mu004@3d {
|
||||
compatible = "samsung,s2mu004mfd";
|
||||
};
|
||||
};
|
||||
|
||||
/* ALIVE */
|
||||
pinctrl_0: pinctrl@139F0000 {
|
||||
compatible = "samsung,exynos78x0-pinctrl";
|
||||
reg = <0x139F0000 0x1000>;
|
||||
};
|
||||
|
||||
/* DISP/AUD */
|
||||
pinctrl_2: pinctrl@148C0000 {
|
||||
compatible = "samsung,exynos78x0-pinctrl";
|
||||
reg = <0x148C0000 0x1000>;
|
||||
};
|
||||
|
||||
/* FSYS0 */
|
||||
pinctrl_4: pinctrl@13750000 {
|
||||
compatible = "samsung,exynos78x0-pinctrl";
|
||||
reg = <0x13750000 0x1000>;
|
||||
};
|
||||
|
||||
/* ALIVE */
|
||||
gpio_0: gpio@139F0000 {
|
||||
compatible = "samsung,exynos78x0-gpio";
|
||||
reg = <0x139F0000 0x1000>;
|
||||
};
|
||||
|
||||
/* DISP/AUD */
|
||||
gpio_2: gpio@148C0000 {
|
||||
compatible = "samsung,exynos78x0-gpio";
|
||||
reg = <0x148C0000 0x1000>;
|
||||
};
|
||||
|
||||
/* FSYS0 */
|
||||
gpio_4: gpio@13750000 {
|
||||
compatible = "samsung,exynos78x0-gpio";
|
||||
reg = <0x13750000 0x1000>;
|
||||
};
|
||||
|
||||
/* TOP */
|
||||
gpio_6: gpio@139B0000 {
|
||||
compatible = "samsung,exynos78x0-gpio";
|
||||
reg = <0x139B0000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -29,3 +29,69 @@ static struct mm_region exynos7420_mem_map[] = {
|
|||
|
||||
struct mm_region *mem_map = exynos7420_mem_map;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EXYNOS7870
|
||||
static struct mm_region exynos7870_mem_map[] = {
|
||||
{
|
||||
.virt = 0x10000000UL,
|
||||
.phys = 0x10000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN,
|
||||
},
|
||||
{
|
||||
.virt = 0x40000000UL,
|
||||
.phys = 0x40000000UL,
|
||||
.size = 0x3E400000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE,
|
||||
},
|
||||
{
|
||||
.virt = 0x80000000UL,
|
||||
.phys = 0x80000000UL,
|
||||
.size = 0x40000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE,
|
||||
},
|
||||
|
||||
{
|
||||
/* List terminator */
|
||||
},
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = exynos7870_mem_map;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EXYNOS7880
|
||||
static struct mm_region exynos7880_mem_map[] = {
|
||||
{
|
||||
.virt = 0x10000000UL,
|
||||
.phys = 0x10000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN,
|
||||
},
|
||||
{
|
||||
.virt = 0x40000000UL,
|
||||
.phys = 0x40000000UL,
|
||||
.size = 0x3E400000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE,
|
||||
},
|
||||
{
|
||||
.virt = 0x80000000UL,
|
||||
.phys = 0x80000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE,
|
||||
},
|
||||
|
||||
{
|
||||
/* List terminator */
|
||||
},
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = exynos7880_mem_map;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -357,6 +357,7 @@ static const struct udevice_id exynos_gpio_ids[] = {
|
|||
{ .compatible = "samsung,exynos4x12-pinctrl" },
|
||||
{ .compatible = "samsung,exynos5250-pinctrl" },
|
||||
{ .compatible = "samsung,exynos5420-pinctrl" },
|
||||
{ .compatible = "samsung,exynos78x0-gpio" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,3 +8,11 @@ config PINCTRL_EXYNOS7420
|
|||
help
|
||||
Support pin multiplexing and pin configuration control on
|
||||
Samsung's Exynos7420 SoC.
|
||||
|
||||
config PINCTRL_EXYNOS78x0
|
||||
bool "Samsung Exynos78x0 pinctrl driver"
|
||||
depends on ARCH_EXYNOS && PINCTRL_FULL
|
||||
select PINCTRL_EXYNOS
|
||||
help
|
||||
Support pin multiplexing and pin configuration control on
|
||||
Samsung's Exynos78x0 SoC.
|
||||
|
|
|
|||
|
|
@ -5,3 +5,4 @@
|
|||
|
||||
obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
|
||||
obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
|
||||
obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o
|
||||
|
|
|
|||
119
drivers/pinctrl/exynos/pinctrl-exynos78x0.c
Normal file
119
drivers/pinctrl/exynos/pinctrl-exynos78x0.c
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Exynos78x0 pinctrl driver.
|
||||
*
|
||||
* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
|
||||
*
|
||||
* based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
|
||||
* Copyright (C) 2016 Samsung Electronics
|
||||
* Thomas Abraham <thomas.ab@samsung.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <dm/root.h>
|
||||
#include <fdtdec.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "pinctrl-exynos.h"
|
||||
|
||||
static struct pinctrl_ops exynos78x0_pinctrl_ops = {
|
||||
.set_state = exynos_pinctrl_set_state
|
||||
};
|
||||
|
||||
/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
|
||||
static struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
|
||||
EXYNOS_PIN_BANK(6, 0x000, "etc0"),
|
||||
EXYNOS_PIN_BANK(3, 0x020, "etc1"),
|
||||
EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
|
||||
EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
|
||||
EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
|
||||
EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
|
||||
EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
|
||||
};
|
||||
|
||||
/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
|
||||
static struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
|
||||
EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
|
||||
};
|
||||
|
||||
/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
|
||||
static struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
|
||||
EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
|
||||
EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
|
||||
EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
|
||||
};
|
||||
|
||||
/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
|
||||
static struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
|
||||
EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
|
||||
EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
|
||||
EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
|
||||
EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
|
||||
EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
|
||||
};
|
||||
|
||||
/* pin banks of exynos78x0 pin-controller 6 (TOP) */
|
||||
static struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
|
||||
EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
|
||||
EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
|
||||
EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
|
||||
EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
|
||||
EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
|
||||
EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
|
||||
EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
|
||||
EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
|
||||
EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
|
||||
EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
|
||||
EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
|
||||
EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
|
||||
EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
|
||||
EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
|
||||
EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
|
||||
EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
|
||||
EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
|
||||
EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
|
||||
EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
|
||||
};
|
||||
|
||||
struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
|
||||
{
|
||||
/* pin-controller instance 0 Alive data */
|
||||
.pin_banks = exynos78x0_pin_banks0,
|
||||
.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0),
|
||||
}, {
|
||||
/* pin-controller instance 1 CCORE data */
|
||||
.pin_banks = exynos78x0_pin_banks1,
|
||||
.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1),
|
||||
}, {
|
||||
/* pin-controller instance 2 DISPAUD data */
|
||||
.pin_banks = exynos78x0_pin_banks2,
|
||||
.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2),
|
||||
}, {
|
||||
/* pin-controller instance 4 FSYS data */
|
||||
.pin_banks = exynos78x0_pin_banks4,
|
||||
.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4),
|
||||
}, {
|
||||
/* pin-controller instance 6 TOP data */
|
||||
.pin_banks = exynos78x0_pin_banks6,
|
||||
.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6),
|
||||
},
|
||||
{/* list terminator */}
|
||||
};
|
||||
|
||||
static const struct udevice_id exynos78x0_pinctrl_ids[] = {
|
||||
{ .compatible = "samsung,exynos78x0-pinctrl",
|
||||
.data = (ulong)exynos78x0_pin_ctrl },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_exynos78x0) = {
|
||||
.name = "pinctrl_exynos78x0",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = exynos78x0_pinctrl_ids,
|
||||
.priv_auto = sizeof(struct exynos_pinctrl_priv),
|
||||
.ops = &exynos78x0_pinctrl_ops,
|
||||
.probe = exynos_pinctrl_probe,
|
||||
};
|
||||
112
include/configs/exynos78x0-common.h
Normal file
112
include/configs/exynos78x0-common.h
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration settings for the EXYNOS 78x0 based boards.
|
||||
*
|
||||
* Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
|
||||
* based on include/exynos7420-common.h
|
||||
* Copyright (C) 2016 Samsung Electronics
|
||||
* Thomas Abraham <thomas.ab@samsung.com>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_EXYNOS78x0_COMMON_H
|
||||
#define __CONFIG_EXYNOS78x0_COMMON_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <linux/sizes.h>
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/* Timer input clock frequency */
|
||||
#define COUNTER_FREQUENCY 26000000
|
||||
|
||||
/* Device Tree */
|
||||
#define CONFIG_DEVICE_TREE_LIST "EXYNOS78x0-a5y17lte"
|
||||
|
||||
#define CPU_RELEASE_ADDR secondary_boot_addr
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
|
||||
|
||||
#define CONFIG_BOARD_COMMON
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
|
||||
/* DRAM Memory Banks */
|
||||
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
|
||||
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
|
||||
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
|
||||
|
||||
#define CONFIG_DEBUG_UART_CLOCK 132710400
|
||||
|
||||
#define CONFIG_PREBOOT \
|
||||
"echo Read pressed buttons status;" \
|
||||
"KEY_VOLUMEUP=gpa20;" \
|
||||
"KEY_HOME=gpa17;" \
|
||||
"KEY_VOLUMEDOWN=gpa21;" \
|
||||
"KEY_POWER=gpa00;" \
|
||||
"PRESSED=0;" \
|
||||
"RELEASED=1;" \
|
||||
"if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; " \
|
||||
"else setenv VOLUME_UP $RELEASED; fi;" \
|
||||
"if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; " \
|
||||
"else setenv VOLUME_DOWN $RELEASED; fi;" \
|
||||
"if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;" \
|
||||
"if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
|
||||
|
||||
#ifndef MEM_LAYOUT_ENV_SETTINGS
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"bootm_low=0x40000000\0"
|
||||
#endif
|
||||
|
||||
#ifndef EXYNOS_DEVICE_SETTINGS
|
||||
#define EXYNOS_DEVICE_SETTINGS \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0"
|
||||
#endif
|
||||
|
||||
#ifndef EXYNOS_FDTFILE_SETTING
|
||||
#define EXYNOS_FDTFILE_SETTING
|
||||
#endif
|
||||
|
||||
#define EXTRA_ENV_SETTINGS \
|
||||
EXYNOS_DEVICE_SETTINGS \
|
||||
EXYNOS_FDTFILE_SETTING \
|
||||
MEM_LAYOUT_ENV_SETTINGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
EXTRA_ENV_SETTINGS
|
||||
|
||||
#endif /* __CONFIG_EXYNOS78x0_COMMON_H */
|
||||
Loading…
Reference in a new issue