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85xx: Add defines for BUCSR bits to make code more readable

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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2010-03-29 13:50:31 -05:00
parent 22c9de064a
commit 69bcf5bc80
3 changed files with 10 additions and 5 deletions
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5
cpu/mpc85xx/release.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright 2008-2009 Freescale Semiconductor, Inc. * Copyright 2008-2010 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com> * Kumar Gala <kumar.gala@freescale.com>
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
@ -61,7 +61,8 @@ __secondary_start_page:
#endif #endif
/* Enable branch prediction */ /* Enable branch prediction */
li r3,0x201 lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r3 mtspr SPRN_BUCSR,r3
/* Ensure TB is 0 */ /* Ensure TB is 0 */

7
cpu/mpc85xx/start.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc. * Copyright (C) 2003 Motorola,Inc.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
@ -213,8 +213,9 @@ _start_e500:
/* Enable Branch Prediction */ /* Enable Branch Prediction */
#if defined(CONFIG_BTB) #if defined(CONFIG_BTB)
li r0,0x201 /* BBFI = 1, BPEN = 1 */ lis r0,BUCSR_ENABLE@h
mtspr BUCSR,r0 ori r0,r0,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r0
#endif #endif
#if defined(CONFIG_SYS_INIT_DBCR) #if defined(CONFIG_SYS_INIT_DBCR)

3
include/asm-ppc/processor.h
View file

@ -533,6 +533,9 @@
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
#define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID1 0x279 /* Process ID Register 1 */