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arm: mvebu: Make ECC support configurable on Armada XP

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Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
This commit is contained in:
Stefan Roese 2015-12-10 15:02:38 +01:00
parent bf0db8b82a
commit 698ffab239
4 changed files with 10 additions and 0 deletions
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3
drivers/ddr/marvell/axp/ddr3_axp.h
View file

@ -33,7 +33,10 @@
#define SAR1_CPU_CORE_MASK 0x00000018 #define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3 #define SAR1_CPU_CORE_OFFSET 3
/* Only enable ECC if the board selects it */
#ifdef CONFIG_BOARD_ECC_SUPPORT
#define ECC_SUPPORT #define ECC_SUPPORT
#endif
#define NEW_FABRIC_TWSI_ADDR 0x4E #define NEW_FABRIC_TWSI_ADDR 0x4E
#ifdef CONFIG_DB_784MP_GP #ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E

5
drivers/ddr/marvell/axp/ddr3_axp_config.h
View file

@ -44,7 +44,12 @@
* DDR3_TRAINING_DEBUG - Debug prints of internal code * DDR3_TRAINING_DEBUG - Debug prints of internal code
*/ */
#define DDR_TARGET_FABRIC 5 #define DDR_TARGET_FABRIC 5
/* Only enable ECC if the board selects it */
#ifdef CONFIG_BOARD_ECC_SUPPORT
#define DRAM_ECC 1 #define DRAM_ECC 1
#else
#define DRAM_ECC 0
#endif
#ifdef MV_DDR_32BIT #ifdef MV_DDR_32BIT
#define BUS_WIDTH 32 #define BUS_WIDTH 32

1
include/configs/db-mv784mp-gp.h
View file

@ -146,5 +146,6 @@
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e #define CONFIG_SPD_EEPROM 0x4e
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */ #endif /* _CONFIG_DB_MV7846MP_GP_H */

1
include/configs/maxbcm.h
View file

@ -108,5 +108,6 @@
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */ #endif /* _CONFIG_DB_MV7846MP_GP_H */