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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

Browse source 
- SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.
This commit is contained in:
Tom Rini 2019-05-26 20:15:46 -04:00
commit 696f02d99b
6 changed files with 58 additions and 64 deletions
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4
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
View file

@ -16,10 +16,6 @@
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
};
/* Clock sources */
clocks {
#address-cells = <1>;

1
arch/arm/mach-socfpga/include/mach/misc.h
View file

@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */

54
arch/arm/mach-socfpga/misc.c
View file

@ -70,6 +70,60 @@ void v7_outer_cache_disable(void)
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
void socfpga_pl310_clear(void)
{
u32 mask = 0xff, ena = 0;
icache_enable();
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x0, &pl310->pl310_tag_latency_ctrl);
writel(0x10, &pl310->pl310_data_latency_ctrl);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
L310_AUX_CTRL_INST_PREFETCH_MASK |
L310_SHARED_ATT_OVERRIDE_ENABLE);
/* Enable the L2 cache */
ena = readl(&pl310->pl310_ctrl);
ena |= L2X0_CTRL_EN;
/*
* Invalidate the PL310 L2 cache. Keep the invalidation code
* entirely in L1 I-cache to avoid any bus traffic through
* the L2.
*/
asm volatile(
".align 5 \n"
" b 3f \n"
"1: str %1, [%4] \n"
" dsb \n"
" isb \n"
" str %0, [%2] \n"
" dsb \n"
" isb \n"
"2: ldr %0, [%2] \n"
" cmp %0, #0 \n"
" bne 2b \n"
" str %0, [%3] \n"
" dsb \n"
" isb \n"
" b 4f \n"
"3: b 1b \n"
"4: nop \n"
: "+r"(mask), "+r"(ena)
: "r"(&pl310->pl310_inv_way),
"r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
: "memory", "cc");
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \

1
arch/arm/mach-socfpga/spl_a10.c
View file

@ -110,6 +110,7 @@ void board_init_f(ulong dummy)
socfpga_init_security_policies();
socfpga_sdram_remap_zero();
socfpga_pl310_clear();
/* Assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();

57
arch/arm/mach-socfpga/spl_gen5.c
View file

@ -5,7 +5,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/pl310.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <image.h>
@ -25,8 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
@ -63,60 +60,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
#endif
static void socfpga_pl310_clear(void)
{
u32 mask = 0xff, ena = 0;
icache_enable();
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x111, &pl310->pl310_tag_latency_ctrl);
writel(0x121, &pl310->pl310_data_latency_ctrl);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
L310_AUX_CTRL_INST_PREFETCH_MASK |
L310_SHARED_ATT_OVERRIDE_ENABLE);
/* Enable the L2 cache */
ena = readl(&pl310->pl310_ctrl);
ena |= L2X0_CTRL_EN;
/*
* Invalidate the PL310 L2 cache. Keep the invalidation code
* entirely in L1 I-cache to avoid any bus traffic through
* the L2.
*/
asm volatile(
".align 5 \n"
" b 3f \n"
"1: str %1, [%4] \n"
" dsb \n"
" isb \n"
" str %0, [%2] \n"
" dsb \n"
" isb \n"
"2: ldr %0, [%2] \n"
" cmp %0, #0 \n"
" bne 2b \n"
" str %0, [%3] \n"
" dsb \n"
" isb \n"
" b 4f \n"
"3: b 1b \n"
"4: nop \n"
: "+r"(mask), "+r"(ena)
: "r"(&pl310->pl310_inv_way),
"r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
: "memory", "cc");
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();

5
drivers/gpio/dwapb_gpio.c
View file

@ -185,12 +185,11 @@ static int gpio_dwapb_bind(struct udevice *dev)
plat->name = ofnode_get_name(node);
}
ret = device_bind(dev, dev->driver, plat->name,
plat, -1, &subdev);
ret = device_bind_ofnode(dev, dev->driver, plat->name,
plat, node, &subdev);
if (ret)
return ret;
dev->node = node;
bank++;
}