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doc: board: ti: am62x/j7200: Update with common boot flow diagram

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Update the bootflow svg diagram and reuse across the platforms as they
are common.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Nishanth Menon 2023-07-27 13:58:45 -05:00 committed by Heinrich Schuchardt
parent cce3e7a23d
commit 68b3baaf3b
3 changed files with 1927 additions and 151 deletions
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68
doc/board/ti/am62x_sk.rst
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@ -42,73 +42,7 @@ Boot Flow:
----------
Below is the pictorial representation of boot flow:
.. code-block:: text
+------------------------------------------------------------------------+
| TIFS | Main R5 | A53 |
+------------------------------------------------------------------------+
| +--------+ | | |
| | Reset | | | |
| +--------+ | | |
| : | | |
| +--------+ | +-----------+ | |
| | *ROM* |----------|-->| Reset rls | | |
| +--------+ | +-----------+ | |
| | | | : | |
| | ROM | | : | |
| |services| | : | |
| | | | +-------------+ | |
| | | | | *R5 ROM* | | |
| | | | +-------------+ | |
| | |<---------|---|Load and auth| | |
| | | | | tiboot3.bin | | |
| +--------+ | +-------------+ | |
| | |<---------|---| Load sysfw | | |
| | | | | part to TIFS| | |
| | | | | core | | |
| | | | +-------------+ | |
| | | | : | |
| | | | : | |
| | | | : | |
| | | | +-------------+ | |
| | | | | *R5 SPL* | | |
| | | | +-------------+ | |
| | | | | DDR | | |
| | | | | config | | |
| | | | +-------------+ | |
| | | | | Load | | |
| | | | | tispl.bin | | |
| | | | +-------------+ | |
| | | | | Load R5 | | |
| | | | | firmware | | |
| | | | +-------------+ | |
| | |<---------|---| Start A53 | | |
| | | | | and jump to | | |
| | | | | DM fw image | | |
| | | | +-------------+ | |
| | | | | +-----------+ |
| | |----------|-----------------------|---->| Reset rls | |
| | | | | +-----------+ |
| | TIFS | | | : |
| |Services| | | +-------------+ |
| | |<---------|-----------------------|---->|*TF-A/OP-TEE*| |
| | | | | +-------------+ |
| | | | | : |
| | | | | +-----------+ |
| | |<---------|-----------------------|---->| *A53 SPL* | |
| | | | | +-----------+ |
| | | | | | Load | |
| | | | | | u-boot.img| |
| | | | | +-----------+ |
| | | | | : |
| | | | | +-----------+ |
| | |<---------|-----------------------|---->| *U-Boot* | |
| | | | | +-----------+ |
| | | | | | prompt | |
| | |----------|-----------------------|-----+-----------+-----|
| +--------+ | | |
| | | |
+------------------------------------------------------------------------+
.. image:: img/boot_diagram_k3_current.svg
- Here TIFS acts as master and provides all the critical services. R5/A53
requests TIFS to get these services done as shown in the above diagram.

1925
doc/board/ti/img/boot_diagram_k3_current.svg Normal file
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85
doc/board/ti/j7200_evm.rst
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@ -30,90 +30,7 @@ Boot Flow:
----------
Below is the pictorial representation of boot flow:
.. code-block:: text
+------------------------------------------------------------------------+-----------------------+
| DMSC | MCU R5 | A72 | MAIN R5/C7x |
+------------------------------------------------------------------------+-----------------------+
| +--------+ | | | |
| | Reset | | | | |
| +--------+ | | | |
| : | | | |
| +--------+ | +-----------+ | | |
| | *ROM* |----------|-->| Reset rls | | | |
| +--------+ | +-----------+ | | |
| | | | : | | |
| | ROM | | : | | |
| |services| | : | | |
| | | | +-------------+ | | |
| | | | | *R5 ROM* | | | |
| | | | +-------------+ | | |
| | |<---------|---|Load and auth| | | |
| | | | | tiboot3.bin | | | |
| | Start | | +-------------+ | | |
| | TIFS |<---------|---| Start | | | |
| | | | | TIFS | | | |
| +--------+ | +-------------+ | | |
| : | | | | | |
| +---------+ | | Load | | | |
| | *TIFS* | | | system | | | |
| +---------+ | | Config data | | | |
| | |<--------|---| | | | |
| | | | +-------------+ | | |
| | | | : | | |
| | | | : | | |
| | | | : | | |
| | | | +-------------+ | | |
| | | | | *R5 SPL* | | | |
| | | | +-------------+ | | |
| | | | | DDR | | | |
| | | | | config | | | |
| | | | +-------------+ | | |
| | | | | Load | | | |
| | | | | tispl.bin | | | |
| | | | +-------------+ | | |
| | | | | Load R5 | | | |
| | | | | firmware | | | |
| | | | +-------------+ | | |
| | |<--------|---| Start A72 | | | |
| | | | | and jump to | | | |
| | | | | DM fw image | | | |
| | | | +-------------+ | | |
| | | | | +-----------+ | |
| | |---------|-----------------------|---->| Reset rls | | |
| | | | | +-----------+ | |
| | TIFS | | | : | |
| |Services | | | +-------------+ | |
| | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | |
| | | | | +-------------+ | |
| | | | | : | |
| | | | | +-----------+ | |
| | |<--------|-----------------------|---->| *A72 SPL* | | |
| | | | | +-----------+ | |
| | | | | | Load | | |
| | | | | | u-boot.img| | |
| | | | | +-----------+ | |
| | | | | : | |
| | | | | +-----------+ | |
| | |<--------|-----------------------|---->| *U-Boot* | | |
| | | | | +-----------+ | |
| | | | | | prompt | | |
| | | | | +-----------+ | |
| | | | | | Load R5 | | |
| | | | | | Firmware | | |
| | | | | +-----------+ | |
| | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
| | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
| | | | | | Load C7 | | +-----------+ |
| | | | | | Firmware | | |
| | | | | +-----------+ | |
| | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
| | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
| | | | | | +-----------+ |
| | | | | | |
| +---------+ | | | |
| | | | |
+------------------------------------------------------------------------+-----------------------+
.. image:: img/boot_diagram_k3_current.svg
- Here DMSC acts as master and provides all the critical services. R5/A72
requests DMSC to get these services done as shown in the above diagram.