Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- ApolloLake: add u64 parameters support for FSP2 bindings
- ApolloLake: add missing parameters to support full configuration of
  the latest FSP MR6 release
- Append appropriate suffixes in various assembly codes

arch/x86/cpu/apollolake/fsp_bindings.c

@@ -89,6 +89,28 @@ static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst)
 		ofnode_read_u32_array(node, name, dst, count);
 }
 
+/**
+ * read_u64_prop() - Read an u64 property from devicetree (scalar or array)
+ * @node:  Valid node reference to read property from
+ * @name:  Name of the property to read from
+ * @count: If the property is expected to be an array, this is the
+ *         number of expected elements
+ *         set to 0 if the property is expected to be a scalar
+ * @dst:   Pointer to destination of where to save the value(s) read
+ *         from devicetree
+ */
+static int read_u64_prop(ofnode node, char *name, size_t count, u64 *dst)
+{
+	if (count == 0) {
+		ofnode_read_u64(node, name, dst);
+	} else {
+		debug("ERROR: %s u64 arrays not supported!\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 /**
  * read_string_prop() - Read a string property from devicetree
  * @node:  Valid node reference to read property from
@@ -206,6 +228,12 @@ static int fsp_update_config_from_dtb(ofnode node, u8 *cfg,
 			read_u32_prop(node, fspb->propname, fspb->count,
 				      (u32 *)&cfg[fspb->offset]);
 		break;
+		case FSP_UINT64:
+			ret = read_u64_prop(node, fspb->propname, fspb->count,
+				      (u64 *)&cfg[fspb->offset]);
+			if (ret)
+				return ret;
+		break;
 		case FSP_STRING:
 			read_string_prop(node, fspb->propname, fspb->count,
 					 (char *)&cfg[fspb->offset]);
@@ -605,6 +633,17 @@ const struct fsp_binding fsp_m_bindings[] = {
 	.offset = offsetof(struct fsp_m_config, variable_nvs_buffer_ptr),
 	.propname = "fspm,variable-nvs-buffer-ptr",
 	}, {
+	.type = FSP_UINT64,
+	.offset = offsetof(struct fsp_m_config, start_timer_ticker_of_pfet_assert),
+	.propname = "fspm,start-timer-ticker-of-pfet-assert",
+	}, {
+	.type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, rt_en),
+	.propname = "fspm,rt-en",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_m_config, skip_pcie_power_sequence),
+	.propname = "fspm,skip-pcie-power-sequence",
+	}, {
 	.propname = NULL
 	}
 };
@@ -1794,6 +1833,18 @@ const struct fsp_binding fsp_s_bindings[] = {
 	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
 				      port_usb20_hs_npre_drv_sel),
 	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, os_selection),
+	.propname = "fsps,os-selection",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dptf_enabled),
+	.propname = "fsps,dptf-enabled",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pwm_enabled),
+	.propname = "fsps,pwm-enabled",
+	}, {
 	.propname = NULL
 	}
 };

arch/x86/cpu/call32.S

@@ -32,8 +32,7 @@ cpu_call32:
 	push	%rdi	/* 32-bit code segment */
 	lea	compat(%rip), %rax
 	push	%rax
-	.byte	0x48	/* REX prefix to force 64-bit far return */
-	retf
+	retfq
 .code32
 compat:
 	/*
@@ -60,4 +59,4 @@ compat:
 	/* Jump to the required target */
 	pushl	%edi	/* 32-bit code segment */
 	pushl	%esi	/* 32-bit target address */
-	retf
+	retfl

arch/x86/cpu/sipi_vector.S

@@ -131,12 +131,12 @@ ap_start:
 	jnz	microcode_done
 
 	/* Determine if parallel microcode loading is allowed */
-	cmp	$0xffffffff, microcode_lock
+	cmpl	$0xffffffff, microcode_lock
 	je	load_microcode
 
 	/* Protect microcode loading */
 lock_microcode:
-	lock bts $0, microcode_lock
+	lock btsl $0, microcode_lock
 	jc	lock_microcode
 
 load_microcode:
@@ -154,7 +154,7 @@ load_microcode:
 	popa
 
 	/* Unconditionally unlock microcode loading */
-	cmp	$0xffffffff, microcode_lock
+	cmpl	$0xffffffff, microcode_lock
 	je	microcode_done
 
 	xor	%eax, %eax

arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h

@@ -122,7 +122,10 @@ struct __packed fsp_m_config {
 
 	/* 0x150 */
 	void	*variable_nvs_buffer_ptr;
-	u8	reserved_fspm_upd[12];
+	u64	start_timer_ticker_of_pfet_assert;
+	u8	rt_en;
+	u8	skip_pcie_power_sequence;
+	u8	reserved_fspm_upd[2];
 };
 
 /** FSP-M UPD Configuration */

arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h

@@ -351,7 +351,10 @@ struct __packed fsp_s_config {
 	u8	port_usb20_hs_npre_drv_sel[8];
 
 	/* 0x370 */
-	u8	reserved_fsps_upd[16];
+	u8	os_selection;
+	u8	dptf_enabled;
+	u8	pwm_enabled;
+	u8	reserved_fsps_upd[13];
 };
 
 /** struct fsps_upd - FSP-S Configuration */
@@ -563,4 +566,8 @@ struct __packed fsps_upd {
 #define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0
 #define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1
 
+#define OS_SELECTION_WINDOWS 0
+#define OS_SELECTION_ANDROID 1
+#define OS_SELECTION_LINUX 3
+
 #endif

arch/x86/include/asm/arch-apollolake/fsp_bindings.h

@@ -17,6 +17,7 @@ enum conf_type {
 	FSP_UINT8,
 	FSP_UINT16,
 	FSP_UINT32,
+	FSP_UINT64,
 	FSP_STRING,
 	FSP_LPDDR4_SWIZZLE,
 };

arch/x86/include/asm/irq.h

@@ -12,8 +12,8 @@
  * Intel interrupt router configuration mechanism
  *
  * There are two known ways of Intel interrupt router configuration mechanism
- * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
- * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
+ * so far. On most cases, the IRQ routing configuration is controlled by PCI
+ * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0).
  * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
  * in the IBASE register block where IBASE is memory-mapped.
  */
@@ -36,7 +36,7 @@ struct pirq_regmap {
  * @link_base:	link value base number
  * @link_num:	number of PIRQ links supported
  * @has_regmap:	has mapping table between PIRQ link and routing register offset
- * @irq_mask:	IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
+ * @irq_mask:	IRQ mask representing the 16 IRQs in 8259, bit N is 1 means
  *		IRQ N is available to be routed
  * @lb_bdf:	irq router's PCI bus/device/function number encoding
  * @ibase:	IBASE register block base address

doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt

@@ -240,6 +240,9 @@ Optional properties:
 - fspm,enable-reset-system: Enable Reset System
 - fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
 - fspm,variable-nvs-buffer-ptr:
+- fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time - PFET
+- fspm,rt-en: Real Time Enabling
+- fspm,skip-pcie-power-sequence: Skip Pcie Power Sequence
 
 Example:
 

doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt

@@ -463,6 +463,12 @@ Optional properties:
 - fsps,port-usb20-i-usb-tx-emphasis-en: PerPort HS Transmitter Emphasis
 - fsps,port-usb20-per-port-rxi-set: PerPort HS Receiver Bias
 - fsps,port-usb20-hs-npre-drv-sel: Delay/skew's strength control for HS driver
+- fsps,os-selection: OS Selection
+  0: Windows
+  1: Android
+  3: Linux
+- fsps,dptf-enabled: DPTF
+- fsps,pwm-enabled: PWM Enabled
 
 Example: