mirror of
https://github.com/AsahiLinux/u-boot
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Tom Rini
commit
6856254fc0
4 changed files with 34 additions and 2 deletions
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@ -252,6 +252,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
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puts("Work-around for Erratum A-005812 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
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puts("Work-around for Erratum A005125 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
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(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
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@ -108,6 +108,14 @@ _start_e500:
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isync
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2:
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
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msync
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isync
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mfspr r3, SPRN_HDBCR0
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oris r3, r3, 0x0080
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mtspr SPRN_HDBCR0, r3
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#endif
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#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
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/* ISBC uses L2 as stack.
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@ -34,6 +34,7 @@
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_MPC8540)
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#define CONFIG_MAX_CPUS 1
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@ -52,6 +53,7 @@
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_MPC8548)
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#define CONFIG_MAX_CPUS 1
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@ -67,6 +69,7 @@
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
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@ -108,6 +111,7 @@
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_MPC8572)
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#define CONFIG_MAX_CPUS 2
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@ -117,6 +121,7 @@
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_DDR_115
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#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1010)
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#define CONFIG_MAX_CPUS 1
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@ -135,6 +140,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
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@ -149,6 +155,7 @@
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P1012 is single core version of P1021 */
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#elif defined(CONFIG_P1012)
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@ -164,6 +171,7 @@
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P1013 is single core version of P1022 */
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#elif defined(CONFIG_P1013)
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@ -176,6 +184,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1014)
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#define CONFIG_MAX_CPUS 1
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@ -205,6 +214,7 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1020)
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#define CONFIG_MAX_CPUS 2
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@ -216,6 +226,7 @@
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1021)
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#define CONFIG_MAX_CPUS 2
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@ -230,6 +241,7 @@
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1022)
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#define CONFIG_MAX_CPUS 2
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@ -241,6 +253,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1023)
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#define CONFIG_MAX_CPUS 2
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@ -254,6 +267,7 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
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@ -268,6 +282,7 @@
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_P1025)
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@ -283,6 +298,7 @@
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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/* P2010 is single core version of P2020 */
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#elif defined(CONFIG_P2010)
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@ -293,6 +309,7 @@
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_P2020)
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#define CONFIG_MAX_CPUS 2
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@ -307,6 +324,7 @@
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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@ -506,6 +524,7 @@
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#elif defined(CONFIG_BSC9132)
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#define CONFIG_MAX_CPUS 2
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@ -525,6 +544,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
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@ -658,6 +678,7 @@
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_A005125
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#else
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#error Processor type not defined for this platform
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@ -354,10 +354,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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/*
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* RapidIO
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