mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 23:51:33 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Tom Rini
commit
6856254fc0
4 changed files with 34 additions and 2 deletions
|
|
@ -252,6 +252,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
|
||||
puts("Work-around for Erratum A-005812 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
puts("Work-around for Erratum A005125 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
|
||||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
|
||||
|
|
|
|||
|
|
@ -108,6 +108,14 @@ _start_e500:
|
|||
isync
|
||||
2:
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
msync
|
||||
isync
|
||||
mfspr r3, SPRN_HDBCR0
|
||||
oris r3, r3, 0x0080
|
||||
mtspr SPRN_HDBCR0, r3
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
|
||||
/* ISBC uses L2 as stack.
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_MPC8540)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
|
|
@ -52,6 +53,7 @@
|
|||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_MPC8548)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
|
|
@ -67,6 +69,7 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
|
||||
|
||||
|
|
@ -108,6 +111,7 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_MPC8572)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -117,6 +121,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
|
||||
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1010)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
|
|
@ -135,6 +140,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
|
||||
#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
|
||||
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
|
||||
|
||||
|
|
@ -149,6 +155,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P1012 is single core version of P1021 */
|
||||
#elif defined(CONFIG_P1012)
|
||||
|
|
@ -164,6 +171,7 @@
|
|||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P1013 is single core version of P1022 */
|
||||
#elif defined(CONFIG_P1013)
|
||||
|
|
@ -176,6 +184,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_FSL_SATA_ERRATUM_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1014)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
|
|
@ -205,6 +214,7 @@
|
|||
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1020)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -216,6 +226,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1021)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -230,6 +241,7 @@
|
|||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1022)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -241,6 +253,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_FSL_SATA_ERRATUM_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P1023)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -254,6 +267,7 @@
|
|||
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
||||
|
||||
|
|
@ -268,6 +282,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P1025 is lower end variant of P1021 */
|
||||
#elif defined(CONFIG_P1025)
|
||||
|
|
@ -283,6 +298,7 @@
|
|||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
/* P2010 is single core version of P2020 */
|
||||
#elif defined(CONFIG_P2010)
|
||||
|
|
@ -293,6 +309,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_P2020)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -307,6 +324,7 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_RMU
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
|
||||
|
|
@ -506,6 +524,7 @@
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_BSC9132)
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
|
|
@ -525,6 +544,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
|
||||
|
||||
|
|
@ -658,6 +678,7 @@
|
|||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#else
|
||||
#error Processor type not defined for this platform
|
||||
|
|
|
|||
|
|
@ -354,10 +354,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
|
|
|
|||
Loading…
Reference in a new issue