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rockchip: sdhci: support 8bit bus-width

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The Rockchip-specific SDHCI wrapper does not process the 'bus-width'
property in the SDHCI node. Consequently, the bus is always kept in
4bit mode, even if 8bit wide operation is available, supported and
requested in the DTS.

This change adds processing of the 'bus-width' property and sets the
host capability flag for an 8bit wide bus, if set to 8. As the logic
in sdhci.c does not support clearing the 4bit capability, we assume
that 4bit operation is always supported.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Philipp Tomsich 2018-03-26 19:59:10 +02:00
parent 47b8583f58
commit 6837c58666
1 changed files with 8 additions and 0 deletions
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8
drivers/mmc/rockchip_sdhci.c
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@ -62,6 +62,13 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
host->max_clk = max_frequency; host->max_clk = max_frequency;
/*
* The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
* doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
* check for other bus-width values.
*/
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
@ -82,6 +89,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
host->name = dev->name; host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev); host->ioaddr = dev_read_addr_ptr(dev);
host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
#endif #endif
return 0; return 0;