Add i.MX7D based Meerkat96 board support

The Meerkat96 board, based on the NXP i.MX7D SoC, is a member of
96Boards community and complies with all Consumer Edition board
specifications.

https://www.novtech.com/products/meerkat96.html
https://www.96boards.org/product/imx7-96/

The initial supported/tested devices include:
 - Debug serial
 - SD
 - USB Host (with Ethernet)

With these support, it's good enough for loading Linux Kernel from SD or
Ethernet over USB.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Shawn Guo 2019-07-07 20:59:55 +08:00 committed by Stefano Babic
parent ad61658dd6
commit 6802d7951c
9 changed files with 345 additions and 0 deletions

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@ -28,6 +28,15 @@ config TARGET_CL_SOM_IMX7
select SUPPORT_SPL
imply CMD_DM
config TARGET_MEERKAT96
bool "NovTech Meerkat96 board"
select BOARD_LATE_INIT
select DM
select DM_SERIAL
select DM_THERMAL
select MX7D
imply CMD_DM
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
select BOARD_LATE_INIT
@ -67,6 +76,7 @@ config SYS_SOC
source "board/compulab/cl-som-imx7/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/novtech/meerkat96/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"

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@ -0,0 +1,12 @@
if TARGET_MEERKAT96
config SYS_BOARD
default "meerkat96"
config SYS_VENDOR
default "novtech"
config SYS_CONFIG_NAME
default "meerkat96"
endif

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@ -0,0 +1,6 @@
MEERKAT96 BOARD
M: Shawn Guo <shawn.guo@kernel.org>
S: Maintained
F: board/novtech/meerkat96
F: include/configs/meerkat96.h
F: configs/meerkat96_defconfig

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@ -0,0 +1 @@
obj-y := meerkat96.o

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@ -0,0 +1,18 @@
* Build U-Boot for Meerkat96 board
$ make mrproper
$ make meerkat96_defconfig
$ make
It will generate the U-Boot binary called u-boot-dtb.imx
* Install U-Boot to MicroSD card
Plug MicroSD card to a Linux machine (with card reader), find the
device name and replace sd[x] with the name in the following command.
$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=512 seek=2
It will install U-Boot to MicroSD card at 1KiB offset. Insert the
card to Meerkat96 MicroSD slot, power up the board, and U-Boot should
boot from the card.

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@ -0,0 +1,127 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : sd
*/
BOOT_FROM sd
/*
* Secure boot support
*/
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable OCRAM EPDC */
DATA 4 0x30340004 0x4F400005
/* =============================================================================
* DDR Controller Registers
* =============================================================================
* Memory type: DDR3
* Manufacturer: ISSI
* Device Part Number: IS43TR16256AL-125KBL
* Clock Freq.: 533MHz
* Density per CS in Gb: 4
* Chip Selects used: 1
* Number of Banks: 8
* Row address: 15
* Column address: 10
* Data bus width: 16
* ROW-BANK interleave: ENABLED
* =============================================================================
*/
DATA 4 0x30391000 0x00000002 // deassert presetn
DATA 4 0x307A0000 0x01041001 // DDRC_MSTR
DATA 4 0x307A0064 0x00400046 // DDRC_RFSHTMG
DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
DATA 4 0x307A00D4 0x00690000 // DDRC_INIT1
DATA 4 0x307A00D0 0x00020083 // DDRC_INIT0
DATA 4 0x307A00DC 0x09300004 // DDRC_INIT3
DATA 4 0x307A00E0 0x04080000 // DDRC_INIT4
DATA 4 0x307A00E4 0x00100004 // DDRC_INIT5
DATA 4 0x307A00F4 0x0000033F // DDRC_RANKCTL
DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
DATA 4 0x307A0104 0x0007020D // DDRC_DRAMTMG1
DATA 4 0x307A0108 0x03040407 // DDRC_DRAMTMG2
DATA 4 0x307A010C 0x00002006 // DDRC_DRAMTMG3
DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
DATA 4 0x307A0120 0x00000803 // DDRC_DRAMTMG8
DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
DATA 4 0x307A0190 0x02098204 // DDRC_DFITMG0
DATA 4 0x307A0194 0x00030303 // DDRC_DFITMG1
DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
DATA 4 0x307A01A4 0x00100020 // DDRC_DFIUPD1
DATA 4 0x307A01A8 0x80100004 // DDRC_DFIUPD2
DATA 4 0x307A0200 0x00000015 // DDRC_ADDRMAP0
DATA 4 0x307A0204 0x00070707 // DDRC_ADDRMAP1
DATA 4 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
DATA 4 0x307A0214 0x06060606 // DDRC_ADDRMAP5
DATA 4 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
DATA 4 0x307A0244 0x00000001 // DDRC_ODTMAP
/* =============================================================================
* PHY Control Register
* =============================================================================
*/
DATA 4 0x30391000 0x00000000 // deassert presetn
DATA 4 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
DATA 4 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
DATA 4 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
DATA 4 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
DATA 4 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
DATA 4 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
DATA 4 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
DATA 4 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790018 0x0000000F // DDR_PHY_LP_CON0
DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
DATA 4 0x307900C0 0x0E447304
DATA 4 0x307900C0 0x0E447306
DATA 4 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
/* =============================================================================
* Final Initialization start sequence
* =============================================================================
*/
DATA 4 0x30384130 0x00000000 // Disable Clock
DATA 4 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
DATA 4 0x30384130 0x00000002 // Enable Clock
/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */

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@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2016 NXP Semiconductors
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
static iomux_v3_cfg_t const meerkat96_pads[] = {
/* UART6 as debug serial */
MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_SD1_WP__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/* WDOG1 for reset */
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(meerkat96_pads,
ARRAY_SIZE(meerkat96_pads));
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int checkboard(void)
{
char *mode;
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
mode = "secure";
else
mode = "non-secure";
printf("Board: i.MX7D Meerkat96 in %s mode\n", mode);
return 0;
}
int board_late_init(void)
{
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
return 0;
}

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@ -0,0 +1,52 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_MEERKAT96=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/novtech/meerkat96/imximage.cfg"
CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_MMC_BROKEN_CD=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y

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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2016 NXP Semiconductors
*
* Configuration settings for Meerkat96 board.
*/
#ifndef __MEERKAT96_CONFIG_H
#define __MEERKAT96_CONFIG_H
#include "mx7_common.h"
#include <imximage.h>
#define PHYS_SDRAM_SIZE SZ_512M
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment configs */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
/* USB configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif