mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 23:51:33 +00:00
Initial revision
This commit is contained in:
wdenk
parent
16f217049a
commit
67c4f48a49
2 changed files with 840 additions and 0 deletions
272
board/mpc8260ads/mpc8260ads.c
Normal file
272
board/mpc8260ads/mpc8260ads.c
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@ -0,0 +1,272 @@
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Modified during 2001 by
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* Advanced Communications Technologies (Australia) Pty. Ltd.
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* Howard Walker, Tuong Vu-Dinh
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*
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
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* Added support for the 16M dram simm on the 8260ads boards
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */
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/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* LED */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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typedef struct bscr_ {
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unsigned long bcsr0;
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unsigned long bcsr1;
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unsigned long bcsr2;
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unsigned long bcsr3;
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unsigned long bcsr4;
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unsigned long bcsr5;
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unsigned long bcsr6;
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unsigned long bcsr7;
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} bcsr_t;
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void reset_phy(void)
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{
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volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
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/* reset the FEC port */
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bcsr->bcsr1 &= ~FETH_RST;
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bcsr->bcsr1 |= FETH_RST;
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}
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int board_pre_init (void)
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{
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volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
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bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;
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return 0;
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}
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long int initdram(int board_type)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar *ramaddr,
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c = 0xff;
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int i;
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#ifndef CFG_RAMBOOT
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immap->im_siu_conf.sc_ppc_acr = 0x00000002;
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immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
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immap->im_siu_conf.sc_tescr1 = 0x00004000;
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/* init local sdram, bank 4 */
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memctl->memc_lsrt = 0x00000010;
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memctl->memc_or4 = 0xFFC01480;
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memctl->memc_br4 = 0x04001861;
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memctl->memc_lsdmr = 0x2886A522;
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ramaddr = (uchar *)CFG_LSDRAM_BASE;
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*ramaddr = c;
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memctl->memc_lsdmr = 0x0886A522;
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for( i = 0; i < 8; i++ ) {
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*ramaddr = c;
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}
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memctl->memc_lsdmr = 0x1886A522;
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*ramaddr = c;
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memctl->memc_lsdmr = 0x4086A522;
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/* init sdram dimm */
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ramaddr = (uchar *)CFG_SDRAM_BASE;
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memctl->memc_psrt = 0x00000010;
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immap->im_memctl.memc_or2 = 0xFF000CA0;
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immap->im_memctl.memc_br2 = 0x00000041;
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memctl->memc_psdmr = 0x296EB452;
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*ramaddr = c;
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memctl->memc_psdmr = 0x096EB452;
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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memctl->memc_psdmr = 0x196EB452;
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*ramaddr = c;
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memctl->memc_psdmr = 0x416EB452;
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*ramaddr = c;
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#endif
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/* return total ram size of simm */
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return (16 * 1024 * 1024);
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}
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int checkboard(void)
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{
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puts ("Board: Motorola MPC8260ADS\n");
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return 0;
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}
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568
board/mpl/common/memtst.c
Normal file
568
board/mpl/common/memtst.c
Normal file
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@ -0,0 +1,568 @@
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/*
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* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
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||||
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||||
/* NOT Used yet...
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add following code to PIP405.c :
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int testdram (void)
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{
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unsigned char s[32];
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int i;
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i = getenv_r ("testmem", s, 32);
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if (i != 0) {
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i = (int) simple_strtoul (s, NULL, 10);
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if ((i > 0) && (i < 0xf)) {
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printf ("testing ");
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i = mem_test (0, ramsize, i);
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if (i > 0)
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printf ("ERROR ");
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else
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printf ("Ok ");
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}
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}
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return (1);
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}
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <405gp_i2c.h>
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#define FALSE 0
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#define TRUE 1
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||||
#define TEST_QUIET 8
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#define TEST_SHOW_PROG 4
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#define TEST_SHOW_ERR 2
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#define TEST_SHOW_ALL 1
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|
||||
#define TESTPAT1 0xAA55AA55
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#define TESTPAT2 0x55AA55AA
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#define TEST_PASSED 0
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#define TEST_FAILED 1
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#define MEGABYTE (1024*1024)
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||||
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||||
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||||
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typedef struct {
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volatile unsigned long pat1;
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||||
volatile unsigned long pat2;
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||||
} RAM_MEMTEST_PATTERN2;
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||||
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||||
typedef struct {
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volatile unsigned long addr;
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} RAM_MEMTEST_ADDRLINE;
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||||
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||||
static __inline unsigned long Swap_32 (unsigned long val)
|
||||
{
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||||
return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF));
|
||||
}
|
||||
|
||||
void testm_puts (int quiet, char *buf)
|
||||
{
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||||
if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL)
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||||
puts (buf);
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||||
}
|
||||
|
||||
|
||||
void Write_Error (int mode, unsigned long addr, unsigned long expected,
|
||||
unsigned long actual)
|
||||
{
|
||||
|
||||
char dispbuf[64];
|
||||
|
||||
sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ",
|
||||
addr, expected, actual);
|
||||
testm_puts (((mode & TEST_SHOW_ERR) ==
|
||||
TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* fills the memblock of <size> bytes from <startaddr> with pat1 and pat2
|
||||
*/
|
||||
|
||||
|
||||
void RAM_MemTest_WritePattern2 (unsigned long startaddr,
|
||||
unsigned long size, unsigned long pat1,
|
||||
unsigned long pat2)
|
||||
{
|
||||
RAM_MEMTEST_PATTERN2 *p, *pe;
|
||||
|
||||
p = (RAM_MEMTEST_PATTERN2 *) startaddr;
|
||||
pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
|
||||
|
||||
while (p < pe) {
|
||||
p->pat1 = pat1;
|
||||
p->pat2 = pat2;
|
||||
p++;
|
||||
} /* endwhile */
|
||||
}
|
||||
|
||||
/*
|
||||
* checks the memblock of <size> bytes from <startaddr> with pat1 and pat2
|
||||
* returns the address of the first error or NULL if all is well
|
||||
*/
|
||||
|
||||
void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long pat1,
|
||||
unsigned long pat2)
|
||||
{
|
||||
RAM_MEMTEST_PATTERN2 *p, *pe;
|
||||
unsigned long actual1, actual2;
|
||||
|
||||
p = (RAM_MEMTEST_PATTERN2 *) startaddr;
|
||||
pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
|
||||
|
||||
while (p < pe) {
|
||||
actual1 = p->pat1;
|
||||
actual2 = p->pat2;
|
||||
|
||||
if (actual1 != pat1) {
|
||||
Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1);
|
||||
return ((void *) &(p->pat1));
|
||||
}
|
||||
/* endif */
|
||||
if (actual2 != pat2) {
|
||||
Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2);
|
||||
return ((void *) &(p->pat2));
|
||||
}
|
||||
/* endif */
|
||||
p++;
|
||||
} /* endwhile */
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* fills the memblock of <size> bytes from <startaddr> with the address
|
||||
*/
|
||||
|
||||
void RAM_MemTest_WriteAddrLine (unsigned long startaddr,
|
||||
unsigned long size, int swapped)
|
||||
{
|
||||
RAM_MEMTEST_ADDRLINE *p, *pe;
|
||||
|
||||
p = (RAM_MEMTEST_ADDRLINE *) startaddr;
|
||||
pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
|
||||
|
||||
if (!swapped) {
|
||||
while (p < pe) {
|
||||
p->addr = (unsigned long) p;
|
||||
p++;
|
||||
} /* endwhile */
|
||||
} else {
|
||||
while (p < pe) {
|
||||
p->addr = Swap_32 ((unsigned long) p);
|
||||
p++;
|
||||
} /* endwhile */
|
||||
} /* endif */
|
||||
}
|
||||
|
||||
/*
|
||||
* checks the memblock of <size> bytes from <startaddr>
|
||||
* returns the address of the error or NULL if all is well
|
||||
*/
|
||||
|
||||
void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr,
|
||||
unsigned long size, int swapped)
|
||||
{
|
||||
RAM_MEMTEST_ADDRLINE *p, *pe;
|
||||
unsigned long actual, expected;
|
||||
|
||||
p = (RAM_MEMTEST_ADDRLINE *) startaddr;
|
||||
pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
|
||||
|
||||
if (!swapped) {
|
||||
while (p < pe) {
|
||||
actual = p->addr;
|
||||
expected = (unsigned long) p;
|
||||
if (actual != expected) {
|
||||
Write_Error (mode, (unsigned long) &(p->addr), expected,
|
||||
actual);
|
||||
return ((void *) &(p->addr));
|
||||
} /* endif */
|
||||
p++;
|
||||
} /* endwhile */
|
||||
} else {
|
||||
while (p < pe) {
|
||||
actual = p->addr;
|
||||
expected = Swap_32 ((unsigned long) p);
|
||||
if (actual != expected) {
|
||||
Write_Error (mode, (unsigned long) &(p->addr), expected,
|
||||
actual);
|
||||
return ((void *) &(p->addr));
|
||||
} /* endif */
|
||||
p++;
|
||||
} /* endwhile */
|
||||
} /* endif */
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* checks the memblock of <size> bytes from <startaddr+size>
|
||||
* returns the address of the error or NULL if all is well
|
||||
*/
|
||||
|
||||
void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr,
|
||||
unsigned long size, int swapped)
|
||||
{
|
||||
RAM_MEMTEST_ADDRLINE *p, *pe;
|
||||
unsigned long actual, expected;
|
||||
|
||||
p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr));
|
||||
pe = (RAM_MEMTEST_ADDRLINE *) startaddr;
|
||||
|
||||
if (!swapped) {
|
||||
while (p > pe) {
|
||||
actual = p->addr;
|
||||
expected = (unsigned long) p;
|
||||
if (actual != expected) {
|
||||
Write_Error (mode, (unsigned long) &(p->addr), expected,
|
||||
actual);
|
||||
return ((void *) &(p->addr));
|
||||
} /* endif */
|
||||
p--;
|
||||
} /* endwhile */
|
||||
} else {
|
||||
while (p > pe) {
|
||||
actual = p->addr;
|
||||
expected = Swap_32 ((unsigned long) p);
|
||||
if (actual != expected) {
|
||||
Write_Error (mode, (unsigned long) &(p->addr), expected,
|
||||
actual);
|
||||
return ((void *) &(p->addr));
|
||||
} /* endif */
|
||||
p--;
|
||||
} /* endwhile */
|
||||
} /* endif */
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* fills the memblock of <size> bytes from <startaddr> with walking bit pattern
|
||||
*/
|
||||
|
||||
void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size)
|
||||
{
|
||||
volatile unsigned long *p, *pe;
|
||||
unsigned long i;
|
||||
|
||||
p = (unsigned long *) startaddr;
|
||||
pe = (unsigned long *) (startaddr + size);
|
||||
i = 0;
|
||||
|
||||
while (p < pe) {
|
||||
*p = 1UL << i;
|
||||
i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
|
||||
p++;
|
||||
} /* endwhile */
|
||||
}
|
||||
|
||||
/*
|
||||
* checks the memblock of <size> bytes from <startaddr>
|
||||
* returns the address of the error or NULL if all is well
|
||||
*/
|
||||
|
||||
void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr,
|
||||
unsigned long size)
|
||||
{
|
||||
volatile unsigned long *p, *pe;
|
||||
unsigned long actual, expected;
|
||||
unsigned long i;
|
||||
|
||||
p = (unsigned long *) startaddr;
|
||||
pe = (unsigned long *) (startaddr + size);
|
||||
i = 0;
|
||||
|
||||
while (p < pe) {
|
||||
actual = *p;
|
||||
expected = (1UL << i);
|
||||
if (actual != expected) {
|
||||
Write_Error (mode, (unsigned long) p, expected, actual);
|
||||
return ((void *) p);
|
||||
} /* endif */
|
||||
i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
|
||||
p++;
|
||||
} /* endwhile */
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* fills the memblock of <size> bytes from <startaddr> with "random" pattern
|
||||
*/
|
||||
|
||||
void RAM_MemTest_WriteRandomPattern (unsigned long startaddr,
|
||||
unsigned long size,
|
||||
unsigned long *pat)
|
||||
{
|
||||
unsigned long i, p;
|
||||
|
||||
p = *pat;
|
||||
|
||||
for (i = 0; i < (size / 4); i++) {
|
||||
*(unsigned long *) (startaddr + i * 4) = p;
|
||||
if ((p % 2) > 0) {
|
||||
p ^= i;
|
||||
p >>= 1;
|
||||
p |= 0x80000000;
|
||||
} else {
|
||||
p ^= ~i;
|
||||
p >>= 1;
|
||||
} /* endif */
|
||||
} /* endfor */
|
||||
*pat = p;
|
||||
}
|
||||
|
||||
/*
|
||||
* checks the memblock of <size> bytes from <startaddr>
|
||||
* returns the address of the error or NULL if all is well
|
||||
*/
|
||||
|
||||
void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr,
|
||||
unsigned long size,
|
||||
unsigned long *pat)
|
||||
{
|
||||
void *perr = NULL;
|
||||
unsigned long i, p, p1;
|
||||
|
||||
p = *pat;
|
||||
|
||||
for (i = 0; i < (size / 4); i++) {
|
||||
p1 = *(unsigned long *) (startaddr + i * 4);
|
||||
if (p1 != p) {
|
||||
if (perr == NULL) {
|
||||
Write_Error (mode, startaddr + i * 4, p, p1);
|
||||
perr = (void *) (startaddr + i * 4);
|
||||
} /* endif */
|
||||
}
|
||||
/* endif */
|
||||
if ((p % 2) > 0) {
|
||||
p ^= i;
|
||||
p >>= 1;
|
||||
p |= 0x80000000;
|
||||
} else {
|
||||
p ^= ~i;
|
||||
p >>= 1;
|
||||
} /* endif */
|
||||
} /* endfor */
|
||||
|
||||
*pat = p;
|
||||
return (perr);
|
||||
}
|
||||
|
||||
|
||||
void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size,
|
||||
unsigned long *pat)
|
||||
{
|
||||
RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2);
|
||||
}
|
||||
|
||||
void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat)
|
||||
{
|
||||
return (RAM_MemTest_CheckPattern2
|
||||
(mode, startaddr, size, TESTPAT1, TESTPAT2));
|
||||
}
|
||||
|
||||
void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size,
|
||||
unsigned long *pat)
|
||||
{
|
||||
RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1);
|
||||
}
|
||||
|
||||
void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat)
|
||||
{
|
||||
return (RAM_MemTest_CheckPattern2
|
||||
(mode, startaddr, size, TESTPAT2, TESTPAT1));
|
||||
}
|
||||
|
||||
void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size,
|
||||
unsigned long *pat)
|
||||
{
|
||||
RAM_MemTest_WriteAddrLine (startaddr, size, FALSE);
|
||||
}
|
||||
|
||||
void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat)
|
||||
{
|
||||
return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE));
|
||||
}
|
||||
|
||||
void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat)
|
||||
{
|
||||
return (RAM_MemTest_CheckAddrLineReverse
|
||||
(mode, startaddr, size, FALSE));
|
||||
}
|
||||
|
||||
void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size,
|
||||
unsigned long *pat)
|
||||
{
|
||||
RAM_MemTest_WriteAddrLine (startaddr, size, TRUE);
|
||||
}
|
||||
|
||||
void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat)
|
||||
{
|
||||
return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE));
|
||||
}
|
||||
|
||||
void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat)
|
||||
{
|
||||
return (RAM_MemTest_CheckAddrLineReverse
|
||||
(mode, startaddr, size, TRUE));
|
||||
}
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
void (*test_write) (unsigned long startaddr, unsigned long size,
|
||||
unsigned long *pat);
|
||||
char *test_write_desc;
|
||||
void *(*test_check1) (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat);
|
||||
void *(*test_check2) (int mode, unsigned long startaddr,
|
||||
unsigned long size, unsigned long *pat);
|
||||
} RAM_MEMTEST_FUNC;
|
||||
|
||||
|
||||
#define TEST_STAGES 5
|
||||
const RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
|
||||
{RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1,
|
||||
NULL},
|
||||
{RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2,
|
||||
NULL},
|
||||
{RAM_MemTest_WriteAddr1, "address line test...\n",
|
||||
RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1},
|
||||
{RAM_MemTest_WriteAddr2, "address line test (swapped)...\n",
|
||||
RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2},
|
||||
{RAM_MemTest_WriteRandomPattern, "random data test...\n",
|
||||
RAM_MemTest_CheckRandomPattern, NULL}
|
||||
};
|
||||
|
||||
|
||||
|
||||
int mem_test (unsigned long start, unsigned long ramsize, int quiet)
|
||||
{
|
||||
unsigned long errors, stage;
|
||||
unsigned long startaddr, size, i;
|
||||
const unsigned long blocksize = 0x80000; /* check in 512KB blocks */
|
||||
unsigned long *perr;
|
||||
unsigned long rdatapat;
|
||||
char dispbuf[80];
|
||||
int status = TEST_PASSED;
|
||||
int prog = 0;
|
||||
|
||||
errors = 0;
|
||||
startaddr = start;
|
||||
size = ramsize;
|
||||
if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
|
||||
prog++;
|
||||
printf (".");
|
||||
}
|
||||
sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n",
|
||||
startaddr, size);
|
||||
testm_puts (quiet, dispbuf);
|
||||
for (stage = 0; stage < TEST_STAGES; stage++) {
|
||||
sprintf (dispbuf, test_stage[stage].test_write_desc);
|
||||
testm_puts (quiet, dispbuf);
|
||||
/* fill SDRAM */
|
||||
rdatapat = 0x12345678;
|
||||
sprintf (dispbuf, "writing block: ");
|
||||
testm_puts (quiet, dispbuf);
|
||||
for (i = 0; i < size; i += blocksize) {
|
||||
sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
|
||||
testm_puts (quiet, dispbuf);
|
||||
test_stage[stage].test_write (startaddr + i, blocksize,
|
||||
&rdatapat);
|
||||
} /* endfor */
|
||||
sprintf (dispbuf, "\n");
|
||||
testm_puts (quiet, dispbuf);
|
||||
if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
|
||||
prog++;
|
||||
printf (".");
|
||||
}
|
||||
/* check SDRAM */
|
||||
rdatapat = 0x12345678;
|
||||
sprintf (dispbuf, "checking block: ");
|
||||
testm_puts (quiet, dispbuf);
|
||||
for (i = 0; i < size; i += blocksize) {
|
||||
sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
|
||||
testm_puts (quiet, dispbuf);
|
||||
if ((perr =
|
||||
test_stage[stage].test_check1 (quiet, startaddr + i,
|
||||
blocksize,
|
||||
&rdatapat)) != NULL) {
|
||||
status = TEST_FAILED;
|
||||
} /* endif */
|
||||
} /* endfor */
|
||||
sprintf (dispbuf, "\n");
|
||||
testm_puts (quiet, dispbuf);
|
||||
if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
|
||||
prog++;
|
||||
printf (".");
|
||||
}
|
||||
if (test_stage[stage].test_check2 != NULL) {
|
||||
/* check2 SDRAM */
|
||||
sprintf (dispbuf, "2nd checking block: ");
|
||||
rdatapat = 0x12345678;
|
||||
testm_puts (quiet, dispbuf);
|
||||
for (i = 0; i < size; i += blocksize) {
|
||||
sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
|
||||
testm_puts (quiet, dispbuf);
|
||||
if ((perr =
|
||||
test_stage[stage].test_check2 (quiet, startaddr + i,
|
||||
blocksize,
|
||||
&rdatapat)) != NULL) {
|
||||
status = TEST_FAILED;
|
||||
} /* endif */
|
||||
} /* endfor */
|
||||
sprintf (dispbuf, "\n");
|
||||
testm_puts (quiet, dispbuf);
|
||||
if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
|
||||
prog++;
|
||||
printf (".");
|
||||
}
|
||||
}
|
||||
|
||||
} /* next stage */
|
||||
if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
|
||||
while (prog-- > 0)
|
||||
printf ("\b \b");
|
||||
}
|
||||
|
||||
if (status == TEST_FAILED)
|
||||
errors++;
|
||||
|
||||
return (errors);
|
||||
}
|
||||
Loading…
Reference in a new issue