mirror of
https://github.com/AsahiLinux/u-boot
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i2c: designware: Convert driver to multibus/multiadapter framework
In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
This commit is contained in:
Stefan Roese
Heiko Schocher
parent
318a9cea49
commit
678398b19e
6 changed files with 141 additions and 177 deletions
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@ -38,7 +38,7 @@ int arch_cpu_init(void)
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#if defined(CONFIG_DW_UDC)
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periph1_clken |= MISC_USBDENB;
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#endif
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#if defined(CONFIG_DW_I2C)
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#if defined(CONFIG_SYS_I2C_DW)
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periph1_clken |= MISC_I2CENB;
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#endif
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#if defined(CONFIG_ST_SMI)
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@ -6,7 +6,6 @@
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#
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obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
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obj-$(CONFIG_DW_I2C) += designware_i2c.o
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obj-$(CONFIG_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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@ -14,6 +13,7 @@ obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
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obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
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@ -6,17 +6,33 @@
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include "designware_i2c.h"
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#include <i2c.h>
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#ifdef CONFIG_I2C_MULTI_BUS
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static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
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static unsigned int current_bus = 0;
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static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 4
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case 3:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
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#endif
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case 0:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
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default:
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printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
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}
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static struct i2c_regs *i2c_regs_p =
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(struct i2c_regs *)CONFIG_SYS_I2C_BASE;
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return NULL;
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}
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/*
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* set_speed - Set the i2c speed mode (standard, high, fast)
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@ -24,51 +40,52 @@ static struct i2c_regs *i2c_regs_p =
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*
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* Set the i2c speed mode (standard, high, fast)
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*/
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static void set_speed(int i2c_spd)
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static void set_speed(struct i2c_adapter *adap, int i2c_spd)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int cntl;
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unsigned int hcnt, lcnt;
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unsigned int enbl;
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/* to set speed cltr must be disabled */
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enbl = readl(&i2c_regs_p->ic_enable);
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enbl = readl(&i2c_base->ic_enable);
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enbl &= ~IC_ENABLE_0B;
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writel(enbl, &i2c_regs_p->ic_enable);
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writel(enbl, &i2c_base->ic_enable);
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cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
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cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
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switch (i2c_spd) {
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case IC_SPEED_MODE_MAX:
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cntl |= IC_CON_SPD_HS;
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hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
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writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt);
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writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
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lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt);
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writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
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break;
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case IC_SPEED_MODE_STANDARD:
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cntl |= IC_CON_SPD_SS;
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hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
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writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt);
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writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
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lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt);
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writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
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break;
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case IC_SPEED_MODE_FAST:
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default:
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cntl |= IC_CON_SPD_FS;
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hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
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writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
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writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
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lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
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writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
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break;
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}
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writel(cntl, &i2c_regs_p->ic_con);
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writel(cntl, &i2c_base->ic_con);
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/* Enable back i2c now speed set */
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enbl |= IC_ENABLE_0B;
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writel(enbl, &i2c_regs_p->ic_enable);
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writel(enbl, &i2c_base->ic_enable);
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}
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/*
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@ -77,7 +94,8 @@ static void set_speed(int i2c_spd)
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*
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* Set the i2c speed.
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*/
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int i2c_set_bus_speed(unsigned int speed)
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static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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int i2c_spd;
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@ -88,28 +106,8 @@ int i2c_set_bus_speed(unsigned int speed)
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else
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i2c_spd = IC_SPEED_MODE_STANDARD;
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set_speed(i2c_spd);
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return i2c_spd;
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}
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/*
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* i2c_get_bus_speed - Gets the i2c speed
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*
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* Gets the i2c speed.
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*/
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unsigned int i2c_get_bus_speed(void)
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{
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u32 cntl;
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cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
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if (cntl == IC_CON_SPD_HS)
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return I2C_MAX_SPEED;
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else if (cntl == IC_CON_SPD_FS)
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return I2C_FAST_SPEED;
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else if (cntl == IC_CON_SPD_SS)
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return I2C_STANDARD_SPEED;
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set_speed(adap, i2c_spd);
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adap->speed = speed;
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return 0;
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}
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@ -117,34 +115,32 @@ unsigned int i2c_get_bus_speed(void)
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/*
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* i2c_init - Init function
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* @speed: required i2c speed
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* @slaveadd: slave address for the device
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* @slaveaddr: slave address for the device
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*
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* Initialization function.
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*/
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void i2c_init(int speed, int slaveadd)
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static void dw_i2c_init(struct i2c_adapter *adap, int speed,
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int slaveaddr)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int enbl;
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/* Disable i2c */
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enbl = readl(&i2c_regs_p->ic_enable);
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enbl = readl(&i2c_base->ic_enable);
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enbl &= ~IC_ENABLE_0B;
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writel(enbl, &i2c_regs_p->ic_enable);
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writel(enbl, &i2c_base->ic_enable);
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writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
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writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
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writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
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i2c_set_bus_speed(speed);
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writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
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writel(slaveadd, &i2c_regs_p->ic_sar);
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writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
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writel(IC_RX_TL, &i2c_base->ic_rx_tl);
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writel(IC_TX_TL, &i2c_base->ic_tx_tl);
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dw_i2c_set_bus_speed(adap, speed);
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writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
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writel(slaveaddr, &i2c_base->ic_sar);
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/* Enable i2c */
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enbl = readl(&i2c_regs_p->ic_enable);
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enbl = readl(&i2c_base->ic_enable);
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enbl |= IC_ENABLE_0B;
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writel(enbl, &i2c_regs_p->ic_enable);
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#ifdef CONFIG_I2C_MULTI_BUS
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bus_initialized[current_bus] = 1;
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#endif
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writel(enbl, &i2c_base->ic_enable);
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}
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/*
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@ -153,21 +149,22 @@ void i2c_init(int speed, int slaveadd)
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(unsigned int i2c_addr)
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static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int enbl;
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/* Disable i2c */
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enbl = readl(&i2c_regs_p->ic_enable);
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enbl = readl(&i2c_base->ic_enable);
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enbl &= ~IC_ENABLE_0B;
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writel(enbl, &i2c_regs_p->ic_enable);
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writel(enbl, &i2c_base->ic_enable);
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writel(i2c_addr, &i2c_regs_p->ic_tar);
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writel(i2c_addr, &i2c_base->ic_tar);
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/* Enable i2c */
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enbl = readl(&i2c_regs_p->ic_enable);
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enbl = readl(&i2c_base->ic_enable);
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enbl |= IC_ENABLE_0B;
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writel(enbl, &i2c_regs_p->ic_enable);
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writel(enbl, &i2c_base->ic_enable);
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}
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/*
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@ -175,10 +172,12 @@ static void i2c_setaddress(unsigned int i2c_addr)
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(void)
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static void i2c_flush_rxfifo(struct i2c_adapter *adap)
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{
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while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_regs_p->ic_cmd_data);
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_base->ic_cmd_data);
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}
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/*
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@ -186,12 +185,13 @@ static void i2c_flush_rxfifo(void)
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(void)
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static int i2c_wait_for_bb(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned long start_time_bb = get_timer(0);
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while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
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while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
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@ -201,40 +201,44 @@ static int i2c_wait_for_bb(void)
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return 0;
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}
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static int i2c_xfer_init(uchar chip, uint addr, int alen)
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static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen)
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{
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if (i2c_wait_for_bb())
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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if (i2c_wait_for_bb(adap))
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return 1;
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i2c_setaddress(chip);
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i2c_setaddress(adap, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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writel((addr >> (alen * 8)) & 0xff,
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&i2c_regs_p->ic_cmd_data);
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&i2c_base->ic_cmd_data);
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}
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return 0;
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}
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static int i2c_xfer_finish(void)
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static int i2c_xfer_finish(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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ulong start_stop_det = get_timer(0);
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while (1) {
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if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_regs_p->ic_clr_stop_det);
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if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_base->ic_clr_stop_det);
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break;
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} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
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break;
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}
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}
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if (i2c_wait_for_bb()) {
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if (i2c_wait_for_bb(adap)) {
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printf("Timed out waiting for bus\n");
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return 1;
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}
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i2c_flush_rxfifo();
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i2c_flush_rxfifo(adap);
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return 0;
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}
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@ -249,8 +253,10 @@ static int i2c_xfer_finish(void)
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*
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* Read from i2c memory.
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*/
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned long start_time_rx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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@ -265,25 +271,25 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(chip, addr, alen))
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if (i2c_xfer_init(adap, dev, addr, alen))
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return 1;
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start_time_rx = get_timer(0);
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while (len) {
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if (len == 1)
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writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data);
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writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
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else
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writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
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writel(IC_CMD, &i2c_base->ic_cmd_data);
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if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
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*buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
|
||||
if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
|
||||
*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
|
||||
len--;
|
||||
start_time_rx = get_timer(0);
|
||||
|
||||
|
|
@ -292,7 +298,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
}
|
||||
}
|
||||
|
||||
return i2c_xfer_finish();
|
||||
return i2c_xfer_finish(adap);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -305,8 +311,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
*
|
||||
* Write to i2c memory.
|
||||
*/
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
|
||||
int alen, u8 *buffer, int len)
|
||||
{
|
||||
struct i2c_regs *i2c_base = i2c_get_base(adap);
|
||||
int nb = len;
|
||||
unsigned long start_time_tx;
|
||||
|
||||
|
|
@ -322,23 +330,25 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
|
||||
|
||||
debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
|
||||
debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
|
||||
addr);
|
||||
#endif
|
||||
|
||||
if (i2c_xfer_init(chip, addr, alen))
|
||||
if (i2c_xfer_init(adap, dev, addr, alen))
|
||||
return 1;
|
||||
|
||||
start_time_tx = get_timer(0);
|
||||
while (len) {
|
||||
if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
|
||||
if (--len == 0)
|
||||
writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data);
|
||||
else
|
||||
writel(*buffer, &i2c_regs_p->ic_cmd_data);
|
||||
if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
|
||||
if (--len == 0) {
|
||||
writel(*buffer | IC_STOP,
|
||||
&i2c_base->ic_cmd_data);
|
||||
} else {
|
||||
writel(*buffer, &i2c_base->ic_cmd_data);
|
||||
}
|
||||
buffer++;
|
||||
start_time_tx = get_timer(0);
|
||||
|
||||
|
|
@ -348,13 +358,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
}
|
||||
}
|
||||
|
||||
return i2c_xfer_finish();
|
||||
return i2c_xfer_finish(adap);
|
||||
}
|
||||
|
||||
/*
|
||||
* i2c_probe - Probe the i2c chip
|
||||
*/
|
||||
int i2c_probe(uchar chip)
|
||||
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
|
||||
{
|
||||
u32 tmp;
|
||||
int ret;
|
||||
|
|
@ -362,80 +372,31 @@ int i2c_probe(uchar chip)
|
|||
/*
|
||||
* Try to read the first location of the chip.
|
||||
*/
|
||||
ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
|
||||
ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
|
||||
if (ret)
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
dw_i2c_init(adap, adap->speed, adap->slaveaddr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_I2C_MULTI_BUS
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
{
|
||||
switch (bus) {
|
||||
case 0:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
|
||||
break;
|
||||
#ifdef CONFIG_SYS_I2C_BASE1
|
||||
case 1:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE2
|
||||
case 2:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE3
|
||||
case 3:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE4
|
||||
case 4:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE5
|
||||
case 5:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE6
|
||||
case 6:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE7
|
||||
case 7:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE8
|
||||
case 8:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_BASE9
|
||||
case 9:
|
||||
i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("Bad bus: %d\n", bus);
|
||||
return -1;
|
||||
}
|
||||
U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
||||
dw_i2c_write, dw_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
|
||||
|
||||
current_bus = bus;
|
||||
|
||||
if (!bus_initialized[current_bus])
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_num(void)
|
||||
{
|
||||
return current_bus;
|
||||
}
|
||||
#if CONFIG_SYS_I2C_BUS_MAX >= 2
|
||||
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
||||
dw_i2c_write, dw_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
|
||||
#endif
|
||||
|
||||
#if CONFIG_SYS_I2C_BUS_MAX >= 3
|
||||
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
||||
dw_i2c_write, dw_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
|
||||
#endif
|
||||
|
||||
#if CONFIG_SYS_I2C_BUS_MAX >= 4
|
||||
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
||||
dw_i2c_write, dw_i2c_set_bus_speed,
|
||||
CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -83,12 +83,15 @@
|
|||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DW_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_DW
|
||||
#define CONFIG_I2C_ENV_EEPROM_BUS 2
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SPEED1 100000
|
||||
#define CONFIG_SYS_I2C_SPEED2 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
#define CONFIG_SYS_I2C_SLAVE1 0
|
||||
#define CONFIG_SYS_I2C_SLAVE2 0
|
||||
#define CONFIG_SYS_I2C_BASE 0xE001D000
|
||||
#define CONFIG_SYS_I2C_BASE1 0xE001E000
|
||||
#define CONFIG_SYS_I2C_BASE2 0xE001F000
|
||||
|
|
|
|||
|
|
@ -37,8 +37,8 @@
|
|||
#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
|
||||
|
||||
/* I2C driver configuration */
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DW_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_DW
|
||||
#if defined(CONFIG_SPEAR600)
|
||||
#define CONFIG_SYS_I2C_BASE 0xD0200000
|
||||
#elif defined(CONFIG_SPEAR300)
|
||||
|
|
|
|||
|
|
@ -83,8 +83,8 @@
|
|||
#define CONFIG_SPEAR_GPIO
|
||||
|
||||
/* I2C config options */
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DW_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_DW
|
||||
#define CONFIG_SYS_I2C_BASE 0xD0200000
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x02
|
||||
|
|
|
|||
Loading…
Reference in a new issue