mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
commit
66c433ed43
760 changed files with 1764 additions and 1302 deletions
3
Kconfig
3
Kconfig
|
|
@ -226,7 +226,8 @@ config BUILD_ROM
|
|||
|
||||
config BUILD_TARGET
|
||||
string "Build target special images"
|
||||
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
|
||||
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
|
||||
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
|
||||
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
|
||||
default "u-boot-elf.srec" if RCAR_GEN3
|
||||
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
|
||||
|
|
|
|||
18
MAINTAINERS
18
MAINTAINERS
|
|
@ -12,13 +12,8 @@ Descriptions of section entries:
|
|||
S: Status, one of the following:
|
||||
Supported: Someone is actually paid to look after this.
|
||||
Maintained: Someone actually looks after it.
|
||||
Odd Fixes: It has a maintainer but they don't have time to do
|
||||
much other than throw the odd patch in. See below..
|
||||
Orphan: No current maintainer [but maybe you could take the
|
||||
role as you write your new code].
|
||||
Obsolete: Old code. Something tagged obsolete generally means
|
||||
it has been replaced by a better system and you
|
||||
should be using that.
|
||||
F: Files and directories with wildcard patterns.
|
||||
A trailing slash includes all files and subdirectory files.
|
||||
F: drivers/net/ all files in and below drivers/net
|
||||
|
|
@ -166,16 +161,19 @@ S: Maintained
|
|||
F: arch/arm/cpu/armv8/hisilicon
|
||||
F: arch/arm/include/asm/arch-hi6220/
|
||||
|
||||
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX
|
||||
M: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
M: Luka Perkov <luka.perkov@sartura.hr>
|
||||
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
T: git git://git.denx.de/u-boot-marvell.git
|
||||
F: arch/arm/mach-kirkwood/
|
||||
F: arch/arm/mach-mvebu/
|
||||
F: drivers/ata/ahci_mvebu.c
|
||||
F: drivers/phy/marvell/
|
||||
F: drivers/ddr/marvell/
|
||||
F: drivers/gpio/mvebu_gpio.c
|
||||
F: drivers/spi/kirkwood_spi.c
|
||||
F: drivers/pci/pci_mvebu.c
|
||||
F: drivers/pci/pcie_dw_mvebu.c
|
||||
F: drivers/watchdog/orion_wdt.c
|
||||
|
||||
ARM MARVELL PXA
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
|
|
@ -456,7 +454,7 @@ EFI PAYLOAD
|
|||
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
|
||||
R: Alexander Graf <agraf@csgraf.de>
|
||||
S: Maintained
|
||||
T: git git://github.com/agraf/u-boot.git
|
||||
T: git git://git.denx.de/u-boot-efi.git
|
||||
F: doc/README.uefi
|
||||
F: doc/README.iscsi
|
||||
F: Documentation/efi.rst
|
||||
|
|
|
|||
10
Makefile
10
Makefile
|
|
@ -3,7 +3,7 @@
|
|||
VERSION = 2019
|
||||
PATCHLEVEL = 04
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc4
|
||||
NAME =
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
|
|||
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
|
||||
|
||||
quiet_cmd_mkfitimage = MKIMAGE $@
|
||||
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@\
|
||||
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@\
|
||||
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
|
||||
|
||||
quiet_cmd_cat = CAT $@
|
||||
|
|
@ -1200,6 +1200,12 @@ u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
|
|||
$(call if_changed,mkimage)
|
||||
$(BOARD_SIZE_CHECK)
|
||||
|
||||
ifeq ($(CONFIG_SPL_LOAD_FIT_FULL),y)
|
||||
MKIMAGEFLAGS_u-boot.itb =
|
||||
else
|
||||
MKIMAGEFLAGS_u-boot.itb = -E
|
||||
endif
|
||||
|
||||
u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
|
||||
$(call if_changed,mkfitimage)
|
||||
$(BOARD_SIZE_CHECK)
|
||||
|
|
|
|||
15
README
15
README
|
|
@ -2130,21 +2130,6 @@ The following options need to be configured:
|
|||
this is instead controlled by the value of
|
||||
/config/load-environment.
|
||||
|
||||
- Serial Flash support
|
||||
Usage requires an initial 'sf probe' to define the serial
|
||||
flash parameters, followed by read/write/erase/update
|
||||
commands.
|
||||
|
||||
The following defaults may be provided by the platform
|
||||
to handle the common case when only a single serial
|
||||
flash is present on the system.
|
||||
|
||||
CONFIG_SF_DEFAULT_BUS Bus identifier
|
||||
CONFIG_SF_DEFAULT_CS Chip-select
|
||||
CONFIG_SF_DEFAULT_MODE (see include/spi.h)
|
||||
CONFIG_SF_DEFAULT_SPEED in Hz
|
||||
|
||||
|
||||
- TFTP Fixed UDP Port:
|
||||
CONFIG_TFTP_PORT
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ config ARCH_LS1021A
|
|||
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
|
||||
select SYS_FSL_ERRATUM_A008378
|
||||
select SYS_FSL_ERRATUM_A008407
|
||||
select SYS_FSL_ERRATUM_A008850
|
||||
select SYS_FSL_ERRATUM_A008997
|
||||
select SYS_FSL_ERRATUM_A009007
|
||||
select SYS_FSL_ERRATUM_A009008
|
||||
|
|
@ -63,6 +64,11 @@ config SYS_CCI400_OFFSET
|
|||
Offset for CCI400 base.
|
||||
CCI400 base addr = CCSRBAR + CCI400_OFFSET
|
||||
|
||||
config SYS_FSL_ERRATUM_A008850
|
||||
bool
|
||||
help
|
||||
Workaround for DDR erratum A008850
|
||||
|
||||
config SYS_FSL_ERRATUM_A008997
|
||||
bool
|
||||
help
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <asm/arch/ls102xa_soc.h>
|
||||
#include <asm/arch/ls102xa_stream_id.h>
|
||||
#include <fsl_csu.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
|
||||
struct liodn_id_table sec_liodn_tbl[] = {
|
||||
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
|
||||
|
|
@ -103,6 +104,41 @@ static void erratum_a009007(void)
|
|||
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
|
||||
}
|
||||
|
||||
static void erratum_a008850_early(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
|
||||
/* part 1 of 2 */
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
|
||||
/* disables propagation of barrier transactions to DDRC from CCI400 */
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
|
||||
|
||||
/* disable the re-ordering in DDRC */
|
||||
out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
|
||||
#endif
|
||||
}
|
||||
|
||||
void erratum_a008850_post(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
|
||||
/* part 2 of 2 */
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
u32 tmp;
|
||||
|
||||
/* enable propagation of barrier transactions to DDRC from CCI400 */
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
||||
|
||||
/* enable the re-ordering in DDRC */
|
||||
tmp = in_be32(&ddr->eor);
|
||||
tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
|
||||
out_be32(&ddr->eor, tmp);
|
||||
#endif
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -163,13 +199,6 @@ int arch_soc_init(void)
|
|||
*/
|
||||
out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
|
||||
out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
|
||||
|
||||
/* Workaround for the issue that DDR could not respond to
|
||||
* barrier transaction which is generated by executing DSB/ISB
|
||||
* instruction. Set CCI-400 control override register to
|
||||
* terminate the barrier transaction. After DDR is initialized,
|
||||
* allow barrier transaction to DDR again */
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
|
||||
}
|
||||
|
||||
/* Enable all the snoop signal for various masters */
|
||||
|
|
@ -191,6 +220,7 @@ int arch_soc_init(void)
|
|||
out_be32(&scfg->eddrtqcfg, 0x63b20042);
|
||||
|
||||
/* Erratum */
|
||||
erratum_a008850_early();
|
||||
erratum_a009008();
|
||||
erratum_a009798();
|
||||
erratum_a008997();
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ if ARM64
|
|||
config ARMV8_SPL_EXCEPTION_VECTORS
|
||||
bool "Install crash dump exception vectors"
|
||||
depends on SPL
|
||||
default y
|
||||
default n
|
||||
help
|
||||
The default exception vector table is only used for the crash
|
||||
dump, but still takes quite a lot of space in the image size.
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ pie_fixup_done:
|
|||
bl reset_sctrl
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
|
||||
.macro set_vbar, regname, reg
|
||||
msr \regname, \reg
|
||||
.endm
|
||||
|
|
@ -354,7 +354,7 @@ ENDPROC(smp_kick_all_cpus)
|
|||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
ENTRY(c_runtime_cpu_setup)
|
||||
#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
|
||||
/* Relocate vBAR */
|
||||
adr x0, vectors
|
||||
switch_el x1, 3f, 2f, 1f
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
|
|||
|
||||
dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
|
||||
|
||||
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5250-spring.dtb \
|
||||
|
|
@ -25,10 +27,44 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
|
|||
exynos5800-peach-pi.dtb \
|
||||
exynos5422-odroidxu3.dtb
|
||||
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_DAVINCI) += \
|
||||
da850-evm.dtb \
|
||||
da850-lcdk.dtb
|
||||
|
||||
dtb-$(CONFIG_KIRKWOOD) += \
|
||||
kirkwood-atl-sbx81lifkw.dtb \
|
||||
kirkwood-atl-sbx81lifxcat.dtb \
|
||||
kirkwood-blackarmor-nas220.dtb \
|
||||
kirkwood-d2net.dtb \
|
||||
kirkwood-dns325.dtb \
|
||||
kirkwood-dockstar.dtb \
|
||||
kirkwood-dreamplug.dtb \
|
||||
kirkwood-ds109.dtb \
|
||||
kirkwood-goflexnet.dtb \
|
||||
kirkwood-guruplug-server-plus.dtb \
|
||||
kirkwood-ib62x0.dtb \
|
||||
kirkwood-iconnect.dtb \
|
||||
kirkwood-is2.dtb \
|
||||
kirkwood-km_kirkwood.dtb \
|
||||
kirkwood-lsxhl.dtb \
|
||||
kirkwood-lschlv2.dtb \
|
||||
kirkwood-net2big.dtb \
|
||||
kirkwood-ns2.dtb \
|
||||
kirkwood-ns2lite.dtb \
|
||||
kirkwood-ns2max.dtb \
|
||||
kirkwood-ns2mini.dtb \
|
||||
kirkwood-pogo_e02.dtb \
|
||||
kirkwood-sheevaplug.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_OWL) += \
|
||||
bubblegum_96.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk3036-sdk.dtb \
|
||||
rk3128-evb.dtb \
|
||||
rk3188-radxarock.dtb \
|
||||
rk3229-evb.dtb \
|
||||
rk3288-evb.dtb \
|
||||
rk3288-fennec.dtb \
|
||||
rk3288-firefly.dtb \
|
||||
|
|
@ -50,6 +86,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
|||
rk3368-px5-evb.dtb \
|
||||
rk3399-evb.dtb \
|
||||
rk3399-firefly.dtb \
|
||||
rk3399-gru-bob.dtb \
|
||||
rk3399-puma-ddr1333.dtb \
|
||||
rk3399-puma-ddr1600.dtb \
|
||||
rk3399-puma-ddr1866.dtb \
|
||||
|
|
@ -96,12 +133,13 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
|
|||
armada-3720-db.dtb \
|
||||
armada-3720-espressobin.dtb \
|
||||
armada-3720-turris-mox.dtb \
|
||||
armada-3720-uDPU.dts \
|
||||
armada-3720-uDPU.dtb \
|
||||
armada-375-db.dtb \
|
||||
armada-388-clearfog.dtb \
|
||||
armada-388-gp.dtb \
|
||||
armada-388-helios4.dtb \
|
||||
armada-385-amc.dtb \
|
||||
armada-385-turris-omnia.dtb \
|
||||
armada-7040-db.dtb \
|
||||
armada-7040-db-nand.dtb \
|
||||
armada-8040-db.dtb \
|
||||
|
|
@ -140,6 +178,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
|
|||
uniphier-sld8-ref.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_ZYNQ) += \
|
||||
bitmain-antminer-s9.dtb \
|
||||
zynq-cc108.dtb \
|
||||
zynq-cse-nand.dtb \
|
||||
zynq-cse-nor.dtb \
|
||||
|
|
@ -156,6 +195,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
|
|||
zynq-zc706.dtb \
|
||||
zynq-zc770-xm010.dtb \
|
||||
zynq-zc770-xm011.dtb \
|
||||
zynq-zc770-xm011-x16.dtb \
|
||||
zynq-zc770-xm012.dtb \
|
||||
zynq-zc770-xm013.dtb \
|
||||
zynq-zed.dtb \
|
||||
|
|
@ -192,7 +232,14 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
|
|||
versal-mini-emmc1.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
|
||||
zynqmp-r5.dtb
|
||||
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
|
||||
dtb-$(CONFIG_AM33XX) += \
|
||||
am335x-baltos.dtb \
|
||||
am335x-bone.dtb \
|
||||
am335x-boneblack.dtb \
|
||||
am335x-brppt1-mmc.dtb \
|
||||
am335x-brppt1-nand.dtb \
|
||||
am335x-brppt1-spi.dtb \
|
||||
am335x-brxre1.dtb \
|
||||
am335x-draco.dtb \
|
||||
am335x-evm.dtb \
|
||||
am335x-evmsk.dtb \
|
||||
|
|
@ -209,6 +256,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
|
|||
am43x-epos-evm.dtb \
|
||||
am437x-idk-evm.dtb \
|
||||
am4372-generic.dtb
|
||||
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
|
||||
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
|
||||
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
|
||||
|
||||
|
|
@ -355,6 +403,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
|
|||
sun7i-a20-olinuxino-lime2.dtb \
|
||||
sun7i-a20-olinuxino-lime2-emmc.dtb \
|
||||
sun7i-a20-olinuxino-micro.dtb \
|
||||
sun7i-a20-olinuxino-micro-emmc.dtb \
|
||||
sun7i-a20-orangepi.dtb \
|
||||
sun7i-a20-orangepi-mini.dtb \
|
||||
sun7i-a20-pcduino3.dtb \
|
||||
|
|
@ -383,7 +432,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
|
|||
sun8i-a83t-allwinner-h8homlet-v2.dtb \
|
||||
sun8i-a83t-bananapi-m3.dtb \
|
||||
sun8i-a83t-cubietruck-plus.dtb \
|
||||
sun8i-a83t-tbs-a711.dts
|
||||
sun8i-a83t-tbs-a711.dtb
|
||||
dtb-$(CONFIG_MACH_SUN8I_H3) += \
|
||||
sun8i-h2-plus-bananapi-m2-zero.dtb \
|
||||
sun8i-h2-plus-libretech-all-h3-cc.dtb \
|
||||
|
|
@ -408,6 +457,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
|
|||
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
|
||||
sun8i-v3s-licheepi-zero.dtb
|
||||
dtb-$(CONFIG_MACH_SUN50I_H5) += \
|
||||
sun50i-h5-bananapi-m2-plus.dtb \
|
||||
sun50i-h5-emlid-neutis-n5-devboard.dtb \
|
||||
sun50i-h5-libretech-all-h3-cc.dtb \
|
||||
sun50i-h5-nanopi-neo2.dtb \
|
||||
|
|
@ -426,6 +476,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
|
|||
sun50i-a64-nanopi-a64.dtb \
|
||||
sun50i-a64-olinuxino.dtb \
|
||||
sun50i-a64-orangepi-win.dtb \
|
||||
sun50i-a64-pine64-lts.dtb \
|
||||
sun50i-a64-pine64-plus.dtb \
|
||||
sun50i-a64-pine64.dtb \
|
||||
sun50i-a64-pinebook.dtb \
|
||||
|
|
@ -441,7 +492,12 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
|
|||
pcm052.dtb \
|
||||
bk4r1.dtb
|
||||
|
||||
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
|
||||
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
|
||||
imx53-kp.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6Q) += \
|
||||
imx6q-display5.dtb \
|
||||
imx6q-logicpd.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6QDL) += \
|
||||
imx6dl-icore.dtb \
|
||||
|
|
@ -452,7 +508,6 @@ dtb-$(CONFIG_MX6QDL) += \
|
|||
imx6q-icore.dtb \
|
||||
imx6q-icore-mipi.dtb \
|
||||
imx6q-icore-rqs.dtb \
|
||||
imx6q-logicpd.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
imx6q-sabresd.dtb \
|
||||
imx6dl-sabreauto.dtb \
|
||||
|
|
@ -462,7 +517,7 @@ dtb-$(CONFIG_MX6QDL) += \
|
|||
|
||||
dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6SL) += imx6sll-evk.dtb
|
||||
dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6SX) += \
|
||||
imx6sx-sabreauto.dtb \
|
||||
|
|
@ -477,12 +532,19 @@ dtb-$(CONFIG_MX6UL) += \
|
|||
imx6ul-9x9-evk.dtb \
|
||||
imx6ul-9x9-evk.dtb \
|
||||
imx6ul-liteboard.dtb \
|
||||
imx6ul-phycore-segin.dtb
|
||||
imx6ul-phycore-segin.dtb \
|
||||
imx6ul-pico-hobbit.dtb \
|
||||
imx6ul-pico-pi.dtb
|
||||
|
||||
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
|
||||
dtb-$(CONFIG_MX6ULL) += \
|
||||
imx6ull-14x14-evk.dtb \
|
||||
imx6ull-colibri.dtb \
|
||||
|
||||
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
|
||||
imx7d-sdb-qspi.dtb
|
||||
imx7d-sdb-qspi.dtb \
|
||||
imx7-colibri-emmc.dtb \
|
||||
imx7-colibri-rawnand.dtb \
|
||||
imx7s-warp.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
|
||||
|
||||
|
|
@ -490,6 +552,16 @@ dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
|
|||
|
||||
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
|
||||
|
||||
dtb-$(CONFIG_RCAR_GEN2) += \
|
||||
r8a7790-lager-u-boot.dtb \
|
||||
r8a7790-stout-u-boot.dtb \
|
||||
r8a7791-koelsch-u-boot.dtb \
|
||||
r8a7791-porter-u-boot.dtb \
|
||||
r8a7792-blanche-u-boot.dtb \
|
||||
r8a7793-gose-u-boot.dtb \
|
||||
r8a7794-alt-u-boot.dtb \
|
||||
r8a7794-silk-u-boot.dtb
|
||||
|
||||
dtb-$(CONFIG_RCAR_GEN3) += \
|
||||
r8a7795-h3ulcb-u-boot.dtb \
|
||||
r8a7795-salvator-x-u-boot.dtb \
|
||||
|
|
@ -509,8 +581,12 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
|
|||
|
||||
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_MEESC) += at91sam9263ek.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb
|
||||
|
|
@ -531,9 +607,15 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
|
|||
|
||||
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
|
||||
logicpd-torpedo-37xx-devkit.dtb \
|
||||
logicpd-som-lv-37xx-devkit.dtb
|
||||
logicpd-som-lv-35xx-devkit.dtb \
|
||||
logicpd-som-lv-37xx-devkit.dtb \
|
||||
logicpd-torpedo-35xx-devkit.dtb \
|
||||
logicpd-torpedo-37xx-devkit.dtb
|
||||
|
||||
dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
|
||||
omap3-evm-37xx.dtb \
|
||||
|
|
@ -582,9 +664,16 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
|
|||
bcm2835-rpi-b-plus.dtb \
|
||||
bcm2835-rpi-b-rev2.dtb \
|
||||
bcm2835-rpi-b.dtb \
|
||||
bcm2835-rpi-zero-w.dtb \
|
||||
bcm2836-rpi-2-b.dtb \
|
||||
bcm2837-rpi-3-b.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM63158) += \
|
||||
bcm963158.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM6858) += \
|
||||
bcm968580xref.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie {
|
||||
status = "okay";
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
|
|
|
|||
|
|
@ -234,7 +234,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie {
|
||||
status = "okay";
|
||||
/*
|
||||
* One PCIe units is accessible through
|
||||
|
|
|
|||
|
|
@ -243,7 +243,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
|
||||
adc@12D10000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
vdd-supply = <&ldo4_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -44,6 +45,7 @@
|
|||
regulator-name = "vdd_ldo1";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -51,18 +53,21 @@
|
|||
regulator-name = "vddq_mmc0";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "vdd_adc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "vdd_ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -70,6 +75,7 @@
|
|||
regulator-name = "vdd_ldo6";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -77,6 +83,7 @@
|
|||
regulator-name = "vdd_ldo7";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -84,6 +91,7 @@
|
|||
regulator-name = "vdd_ldo8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -91,6 +99,7 @@
|
|||
regulator-name = "vdd_ldo9";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -98,6 +107,7 @@
|
|||
regulator-name = "vdd_ldo10";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -105,6 +115,7 @@
|
|||
regulator-name = "vdd_ldo11";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -112,6 +123,7 @@
|
|||
regulator-name = "vdd_ldo12";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -119,12 +131,14 @@
|
|||
regulator-name = "vddq_mmc2";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
};
|
||||
|
||||
ldo15_reg: LDO15 {
|
||||
regulator-name = "vdd_ldo15";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -132,6 +146,7 @@
|
|||
regulator-name = "vdd_ldo16";
|
||||
regulator-min-microvolt = <2200000>;
|
||||
regulator-max-microvolt = <2200000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -139,6 +154,7 @@
|
|||
regulator-name = "vdd_ldo17";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -146,18 +162,21 @@
|
|||
regulator-name = "vdd_emmc_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "vdd_sd";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
};
|
||||
|
||||
ldo24_reg: LDO24 {
|
||||
regulator-name = "tsp_io";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -165,6 +184,7 @@
|
|||
regulator-name = "vdd_ldo26";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-ramp-delay = <12000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -256,7 +276,7 @@
|
|||
};
|
||||
|
||||
serial@12C20000 {
|
||||
status="okay";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc@12200000 {
|
||||
|
|
|
|||
|
|
@ -18,6 +18,10 @@
|
|||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
pinctrl: pin-controller@10000 {
|
||||
pmx_led_bluetooth: pmx-led-bluetooth {
|
||||
|
|
|
|||
|
|
@ -19,6 +19,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,14 @@
|
|||
#include "r8a7795-salvator-x.dts"
|
||||
#include "r8a7795-u-boot.dtsi"
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&vcc_sdhi3 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,14 @@
|
|||
#include "r8a7796-salvator-x.dts"
|
||||
#include "r8a7796-u-boot.dtsi"
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&vcc_sdhi3 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,14 @@
|
|||
#include "r8a77965-salvator-x.dts"
|
||||
#include "r8a77965-u-boot.dtsi"
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&vcc_sdhi3 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
|
||||
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
|
|
@ -60,6 +61,7 @@
|
|||
|
||||
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
|
|
|
|||
|
|
@ -95,6 +95,7 @@
|
|||
mac-address = [00 00 00 00 00 00];
|
||||
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
|
||||
reset-names = "stmmaceth";
|
||||
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -106,6 +107,7 @@
|
|||
mac-address = [00 00 00 00 00 00];
|
||||
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
|
||||
reset-names = "stmmaceth";
|
||||
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -117,6 +119,7 @@
|
|||
mac-address = [00 00 00 00 00 00];
|
||||
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
|
||||
reset-names = "stmmaceth";
|
||||
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@ unsigned int get_soc_major_rev(void);
|
|||
int arch_soc_init(void);
|
||||
int ls102xa_smmu_stream_id_init(void);
|
||||
|
||||
void erratum_a008850_post(void);
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
|
||||
void erratum_a010315(void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -88,8 +88,6 @@ __weak void board_quiesce_devices(void)
|
|||
*/
|
||||
static void announce_and_cleanup(int fake)
|
||||
{
|
||||
printf("\nStarting kernel ...%s\n\n", fake ?
|
||||
"(fake run for tracing)" : "");
|
||||
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
|
||||
#ifdef CONFIG_BOOTSTAGE_FDT
|
||||
bootstage_fdt_add_report();
|
||||
|
|
@ -104,6 +102,8 @@ static void announce_and_cleanup(int fake)
|
|||
|
||||
board_quiesce_devices();
|
||||
|
||||
printf("\nStarting kernel ...%s\n\n", fake ?
|
||||
"(fake run for tracing)" : "");
|
||||
/*
|
||||
* Call remove function of all devices with a removal flag set.
|
||||
* This may be useful for last-stage operations, like cancelling
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
|
|||
{
|
||||
int upto, todo;
|
||||
int i, timeout = 100;
|
||||
struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
|
||||
struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
|
||||
|
||||
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
|
||||
/* set the spi1 GPIO */
|
||||
|
|
|
|||
|
|
@ -26,6 +26,12 @@
|
|||
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
|
||||
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
|
||||
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
|
||||
/*
|
||||
* Disable the dcache. Currently the network driver (mvgbe.c) and USB
|
||||
* EHCI driver (ehci-marvell.c) and possibly others rely on the data
|
||||
* cache being disabled.
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
/*
|
||||
* By default kwbimage.cfg from board specific folder is used
|
||||
|
|
@ -54,21 +60,6 @@
|
|||
#define NAND_ALLOW_ERASE_ALL 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SPI Flash configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#ifndef CONFIG_ENV_SPI_BUS
|
||||
# define CONFIG_ENV_SPI_BUS 0
|
||||
#endif
|
||||
#ifndef CONFIG_ENV_SPI_CS
|
||||
# define CONFIG_ENV_SPI_CS 0
|
||||
#endif
|
||||
#ifndef CONFIG_ENV_SPI_MAX_HZ
|
||||
# define CONFIG_ENV_SPI_MAX_HZ 50000000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -45,21 +45,6 @@
|
|||
|
||||
#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
|
||||
|
||||
/*
|
||||
* SPI Flash configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#ifndef CONFIG_ENV_SPI_BUS
|
||||
# define CONFIG_ENV_SPI_BUS 0
|
||||
#endif
|
||||
#ifndef CONFIG_ENV_SPI_CS
|
||||
# define CONFIG_ENV_SPI_CS 0
|
||||
#endif
|
||||
#ifndef CONFIG_ENV_SPI_MAX_HZ
|
||||
# define CONFIG_ENV_SPI_MAX_HZ 50000000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Needed for SPI NOR booting in SPL */
|
||||
#define CONFIG_DM_SEQ_ALIAS 1
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
dtb-$(CONFIG_ARCH_MT7620) += \
|
||||
gardena-smart-gateway-mt7688.dtb \
|
||||
linkit-smart-7688.dtb
|
||||
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
|
||||
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
|
||||
dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
|
||||
|
|
@ -17,6 +20,8 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
|
|||
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
|
||||
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
|
||||
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
|
||||
dtb-$(CONFIG_SOC_BMIPS_BCM6358) += sfr,nb4-ser.dtb
|
||||
dtb-$(CONFIG_SOC_BMIPS_BCM6838) += brcm,bcm968380gerg.dtb
|
||||
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
|
||||
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
|
||||
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
|
||||
dtb-$(CONFIG_MCR3000) += mcr3000.dtb
|
||||
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
|
||||
|
||||
targets += $(dtb-y)
|
||||
|
||||
|
|
|
|||
|
|
@ -15,19 +15,6 @@
|
|||
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifndef CONFIG_SF_DEFAULT_SPEED
|
||||
# define CONFIG_SF_DEFAULT_SPEED 1000000
|
||||
#endif
|
||||
#ifndef CONFIG_SF_DEFAULT_MODE
|
||||
# define CONFIG_SF_DEFAULT_MODE SPI_MODE0
|
||||
#endif
|
||||
#ifndef CONFIG_SF_DEFAULT_CS
|
||||
# define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
#ifndef CONFIG_SF_DEFAULT_BUS
|
||||
# define CONFIG_SF_DEFAULT_BUS 0
|
||||
#endif
|
||||
|
||||
#define MAX_SERIAL_SIZE 15
|
||||
#define MAX_HWADDR_SIZE 17
|
||||
|
||||
|
|
|
|||
|
|
@ -97,6 +97,8 @@ int dram_init(void)
|
|||
ddrmc_init();
|
||||
#endif
|
||||
|
||||
erratum_a008850_post();
|
||||
|
||||
gd->ram_size = DDR_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -179,6 +179,8 @@ int fsl_initdram(void)
|
|||
fsl_dp_resume();
|
||||
#endif
|
||||
|
||||
erratum_a008850_post();
|
||||
|
||||
gd->ram_size = dram_size;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -5,6 +5,9 @@
|
|||
|
||||
#ifndef __DDR_H__
|
||||
#define __DDR_H__
|
||||
|
||||
void erratum_a008850_post(void);
|
||||
|
||||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
|
|
|
|||
|
|
@ -200,10 +200,6 @@ int board_early_init_f(void)
|
|||
#ifdef CONFIG_SPL_BUILD
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
unsigned int major;
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
u32 porsr1, pinctl;
|
||||
|
|
@ -240,10 +236,6 @@ void board_init_f(ulong dummy)
|
|||
i2c_init_all();
|
||||
#endif
|
||||
|
||||
major = get_soc_major_rev();
|
||||
if (major == SOC_MAJOR_VER_1_0)
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
|
||||
|
||||
timer_init();
|
||||
dram_init();
|
||||
|
||||
|
|
@ -420,22 +412,12 @@ int misc_init_r(void)
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
unsigned int major;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
|
||||
erratum_a010315();
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
|
||||
erratum_a009942_check_cpo();
|
||||
#endif
|
||||
major = get_soc_major_rev();
|
||||
if (major == SOC_MAJOR_VER_1_0) {
|
||||
/* Set CCI-400 control override register to
|
||||
* enable barrier transaction */
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
||||
}
|
||||
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
|
||||
|
|
@ -456,18 +438,6 @@ int board_init(void)
|
|||
#if defined(CONFIG_DEEP_SLEEP)
|
||||
void board_sleep_prepare(void)
|
||||
{
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
unsigned int major;
|
||||
|
||||
major = get_soc_major_rev();
|
||||
if (major == SOC_MAJOR_VER_1_0) {
|
||||
/* Set CCI-400 control override register to
|
||||
* enable barrier transaction */
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
|
||||
enable_layerscape_ns_access();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -222,6 +222,8 @@ int dram_init(void)
|
|||
ddrmc_init();
|
||||
#endif
|
||||
|
||||
erratum_a008850_post();
|
||||
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
|
||||
|
|
|
|||
|
|
@ -628,8 +628,9 @@ int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
|
|||
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
||||
{
|
||||
char mdio_ioslot_str[] = "mdio@00";
|
||||
char mdio_mux_str[] = "mdio-mux-0";
|
||||
struct lx2160a_qds_mdio *priv;
|
||||
u64 reg;
|
||||
u32 phandle;
|
||||
int offset, mux_val;
|
||||
|
||||
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
|
||||
|
|
@ -643,15 +644,32 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
|||
debug("real_bus_num = %d, ioslot = %d\n",
|
||||
priv->realbusnum, priv->ioslot);
|
||||
|
||||
sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
|
||||
offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
|
||||
if (priv->realbusnum == EMI1)
|
||||
reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||
else
|
||||
reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||
|
||||
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found under node %s in device tree\n",
|
||||
mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
|
||||
printf("mdio@%llx node not found in device tree\n", reg);
|
||||
return offset;
|
||||
}
|
||||
|
||||
phandle = fdt_get_phandle(fdt, offset);
|
||||
phandle = cpu_to_fdt32(phandle);
|
||||
offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
|
||||
&phandle, 4);
|
||||
if (offset < 0) {
|
||||
printf("mdio-mux-%d node not found in device tree\n",
|
||||
priv->realbusnum == EMI1 ? 1 : 2);
|
||||
return offset;
|
||||
}
|
||||
|
||||
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||
if (priv->realbusnum == EMI1)
|
||||
mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
|
||||
else
|
||||
mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
|
||||
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
|
||||
|
||||
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
|
||||
|
|
@ -675,7 +693,9 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
|
|||
|
||||
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
|
||||
if (*subnodeoffset <= 0) {
|
||||
printf("Could not add subnode %s\n", phy_node_name);
|
||||
printf("Could not add subnode %s inside node %s err = %s\n",
|
||||
phy_node_name, fdt_get_name(fdt, offset, NULL),
|
||||
fdt_strerror(*subnodeoffset));
|
||||
return *subnodeoffset;
|
||||
}
|
||||
|
||||
|
|
@ -779,7 +799,6 @@ int fdt_fixup_board_phy(void *fdt)
|
|||
}
|
||||
if (dpmac_id == NUM_WRIOP_PORTS)
|
||||
continue;
|
||||
|
||||
ret = fdt_create_phy_node(fdt, offset, i,
|
||||
&subnodeoffset,
|
||||
phy_dev, phandle);
|
||||
|
|
@ -792,6 +811,11 @@ int fdt_fixup_board_phy(void *fdt)
|
|||
fdt_del_node(fdt, subnodeoffset);
|
||||
break;
|
||||
}
|
||||
/* calculate offset again as new node addition may have
|
||||
* changed offset;
|
||||
*/
|
||||
offset = fdt_get_ioslot_offset(fdt, mii_dev,
|
||||
fpga_offset);
|
||||
phandle++;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
RPI BOARD
|
||||
M: Alexander Graf <agraf@suse.de>
|
||||
M: Matthias Brugger <mbrugger@suse.com>
|
||||
S: Maintained
|
||||
F: board/raspberrypi/rpi/
|
||||
F: include/configs/rpi.h
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
ARNDALE BOARD
|
||||
M: Chander Kashyap <k.chander@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
S: Maintained
|
||||
F: board/samsung/arndale/
|
||||
F: include/configs/arndale.h
|
||||
|
|
|
|||
|
|
@ -249,11 +249,22 @@ int board_eth_init(bd_t *bis)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
#if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE)
|
||||
int checkboard(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_BOARD_TYPES)) {
|
||||
const char *board_info = get_board_type();
|
||||
const char *board_info;
|
||||
|
||||
if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
|
||||
/*
|
||||
* Printing type requires having revision, although
|
||||
* this will succeed only if done late.
|
||||
* Otherwise revision will be set in misc_init_r().
|
||||
*/
|
||||
set_board_revision();
|
||||
}
|
||||
|
||||
board_info = get_board_type();
|
||||
|
||||
if (board_info)
|
||||
printf("Type: %s\n", board_info);
|
||||
|
|
@ -287,6 +298,16 @@ int board_late_init(void)
|
|||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_BOARD_TYPES) &&
|
||||
!IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
|
||||
/*
|
||||
* If revision was not set by late display boardinfo,
|
||||
* set it here. At this point regulators should be already
|
||||
* available.
|
||||
*/
|
||||
set_board_revision();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
set_board_info();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
# ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr
|
||||
#
|
||||
# It requires a list of environment variables to be defined before load:
|
||||
# platform dependent: boardname, fdtfile, console
|
||||
# platform dependent: board_name, fdtfile, console
|
||||
# system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype
|
||||
#
|
||||
setenv fdtaddr "40800000"
|
||||
|
|
@ -35,17 +35,17 @@ else
|
|||
setenv initrd_addr -;
|
||||
fi;"
|
||||
|
||||
#### Routine: boot_fit - check that env $boardname is set and boot proper config of ITB image
|
||||
#### Routine: boot_fit - check that env $board_name is set and boot proper config of ITB image
|
||||
setenv setboot_fit "
|
||||
if test -e '${boardname}'; then
|
||||
if test -e '${board_name}'; then
|
||||
setenv fdt_addr ;
|
||||
setenv initrd_addr ;
|
||||
setenv kerneladdr 0x42000000;
|
||||
setenv kernelname Image.itb;
|
||||
setenv itbcfg "\"#${boardname}\"";
|
||||
setenv itbcfg "\"#${board_name}\"";
|
||||
setenv imgbootcmd bootm;
|
||||
else
|
||||
echo Warning! Variable: \$boardname is undefined!;
|
||||
echo Warning! Variable: \$board_name is undefined!;
|
||||
fi"
|
||||
|
||||
#### Routine: setboot_uimg - prepare env to boot uImage
|
||||
|
|
|
|||
|
|
@ -57,12 +57,48 @@ static unsigned int odroid_get_rev(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read ADC at least twice and check the resuls. If regulator providing voltage
|
||||
* on to measured point was just turned on, first reads might require time
|
||||
* to stabilize.
|
||||
*/
|
||||
static int odroid_get_adc_val(unsigned int *adcval)
|
||||
{
|
||||
unsigned int adcval_prev = 0;
|
||||
int ret, retries = 20;
|
||||
|
||||
ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN,
|
||||
&adcval_prev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
while (retries--) {
|
||||
mdelay(5);
|
||||
|
||||
ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN,
|
||||
adcval);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* If difference between ADC reads is less than 3%,
|
||||
* accept the result
|
||||
*/
|
||||
if ((100 * abs(*adcval - adcval_prev) / adcval_prev) < 3)
|
||||
return ret;
|
||||
|
||||
adcval_prev = *adcval;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int odroid_get_board_type(void)
|
||||
{
|
||||
unsigned int adcval;
|
||||
int ret, i;
|
||||
|
||||
ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN, &adcval);
|
||||
ret = odroid_get_adc_val(&adcval);
|
||||
if (ret)
|
||||
goto rev_default;
|
||||
|
||||
|
|
@ -192,8 +228,11 @@ const char *get_board_type(void)
|
|||
|
||||
/**
|
||||
* set_board_type() - set board type in gd->board_type.
|
||||
* As default type set EXYNOS5_BOARD_GENERIC, if detect Odroid,
|
||||
* then set its proper type.
|
||||
* As default type set EXYNOS5_BOARD_GENERIC. If Odroid is detected,
|
||||
* set its proper type based on device tree.
|
||||
*
|
||||
* This might be called early when some more specific ways to detect revision
|
||||
* are not yet available.
|
||||
*/
|
||||
void set_board_type(void)
|
||||
{
|
||||
|
|
@ -211,8 +250,15 @@ void set_board_type(void)
|
|||
gd->board_type = of_match->data;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* If Odroid, then check its revision */
|
||||
/**
|
||||
* set_board_revision() - set detailed board type in gd->board_type.
|
||||
* Should be called when resources (e.g. regulators) are available
|
||||
* so ADC can be used to detect the specific revision of a board.
|
||||
*/
|
||||
void set_board_revision(void)
|
||||
{
|
||||
if (board_is_odroidxu3())
|
||||
gd->board_type = odroid_get_board_type();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ void set_board_info(void)
|
|||
bdtype = "";
|
||||
|
||||
sprintf(info, "%s%s", bdname, bdtype);
|
||||
env_set("boardname", info);
|
||||
env_set("board_name", info);
|
||||
#endif
|
||||
snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb",
|
||||
CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype);
|
||||
|
|
|
|||
|
|
@ -54,6 +54,14 @@ void set_board_type(void)
|
|||
gd->board_type = ODROID_TYPE_U3;
|
||||
}
|
||||
|
||||
void set_board_revision(void)
|
||||
{
|
||||
/*
|
||||
* Revision already set by set_board_type() because it can be
|
||||
* executed early.
|
||||
*/
|
||||
}
|
||||
|
||||
const char *get_board_type(void)
|
||||
{
|
||||
const char *board_type[] = {"u3", "x2"};
|
||||
|
|
@ -462,18 +470,33 @@ struct dwc2_plat_otg_data s5pc210_otg_data = {
|
|||
|
||||
#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
|
||||
|
||||
static void set_usb3503_ref_clk(void)
|
||||
{
|
||||
#ifdef CONFIG_BOARD_TYPES
|
||||
/*
|
||||
* gpx3-0 chooses primary (low) or secondary (high) reference clock
|
||||
* frequencies table. The choice of clock is done through hard-wired
|
||||
* REF_SEL pins.
|
||||
* The Odroid Us have reference clock at 24 MHz (00 entry from secondary
|
||||
* table) and Odroid Xs have it at 26 MHz (01 entry from primary table).
|
||||
*/
|
||||
if (gd->board_type == ODROID_TYPE_U3)
|
||||
gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
|
||||
else
|
||||
gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
|
||||
#else
|
||||
/* Choose Odroid Xs frequency without board types */
|
||||
gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
|
||||
#endif /* CONFIG_BOARD_TYPES */
|
||||
}
|
||||
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
#ifdef CONFIG_CMD_USB
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
|
||||
/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
|
||||
if (gd->board_type == ODROID_TYPE_U3)
|
||||
gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
|
||||
else
|
||||
gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
|
||||
set_usb3503_ref_clk();
|
||||
|
||||
/* Disconnect, Reset, Connect */
|
||||
gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
|
||||
|
|
|
|||
|
|
@ -3,4 +3,3 @@
|
|||
# Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
|
||||
|
||||
obj-y += axs10x.o
|
||||
obj-$(CONFIG_CMD_NAND) += nand.o
|
||||
|
|
|
|||
|
|
@ -1,242 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <bouncebuf.h>
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <nand.h>
|
||||
#include <asm/io.h>
|
||||
#include "axs10x.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define BUS_WIDTH 8 /* AXI data bus width in bytes */
|
||||
|
||||
/* DMA buffer descriptor bits & masks */
|
||||
#define BD_STAT_OWN (1 << 31)
|
||||
#define BD_STAT_BD_FIRST (1 << 3)
|
||||
#define BD_STAT_BD_LAST (1 << 2)
|
||||
#define BD_SIZES_BUFFER1_MASK 0xfff
|
||||
|
||||
#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
|
||||
|
||||
/* Controller command flags */
|
||||
#define B_WFR (1 << 19) /* 1b - Wait for ready */
|
||||
#define B_LC (1 << 18) /* 1b - Last cycle */
|
||||
#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
|
||||
|
||||
/* NAND cycle types */
|
||||
#define B_CT_ADDRESS (0x0 << 16) /* Address operation */
|
||||
#define B_CT_COMMAND (0x1 << 16) /* Command operation */
|
||||
#define B_CT_WRITE (0x2 << 16) /* Write operation */
|
||||
#define B_CT_READ (0x3 << 16) /* Write operation */
|
||||
|
||||
enum nand_isr_t {
|
||||
NAND_ISR_DATAREQUIRED = 0,
|
||||
NAND_ISR_TXUNDERFLOW,
|
||||
NAND_ISR_TXOVERFLOW,
|
||||
NAND_ISR_DATAAVAILABLE,
|
||||
NAND_ISR_RXUNDERFLOW,
|
||||
NAND_ISR_RXOVERFLOW,
|
||||
NAND_ISR_TXDMACOMPLETE,
|
||||
NAND_ISR_RXDMACOMPLETE,
|
||||
NAND_ISR_DESCRIPTORUNAVAILABLE,
|
||||
NAND_ISR_CMDDONE,
|
||||
NAND_ISR_CMDAVAILABLE,
|
||||
NAND_ISR_CMDERROR,
|
||||
NAND_ISR_DATATRANSFEROVER,
|
||||
NAND_ISR_NONE
|
||||
};
|
||||
|
||||
enum nand_regs_t {
|
||||
AC_FIFO = 0, /* address and command fifo */
|
||||
IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
|
||||
INT_STATUS = 0x118, /* interrupt status register */
|
||||
INT_CLR_STATUS = 0x120, /* interrupt clear status register */
|
||||
};
|
||||
|
||||
struct nand_bd {
|
||||
uint32_t status; /* DES0 */
|
||||
uint32_t sizes; /* DES1 */
|
||||
uint32_t buffer_ptr0; /* DES2 */
|
||||
uint32_t buffer_ptr1; /* DES3 */
|
||||
};
|
||||
|
||||
#define NAND_REG_WRITE(r, v) \
|
||||
writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
|
||||
#define NAND_REG_READ(r) \
|
||||
readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
|
||||
|
||||
static struct nand_bd *bd; /* DMA buffer descriptors */
|
||||
|
||||
/**
|
||||
* axs101_nand_write_buf - write buffer to chip
|
||||
* @mtd: MTD device structure
|
||||
* @buf: data buffer
|
||||
* @len: number of bytes to write
|
||||
*/
|
||||
static uint32_t nand_flag_is_set(uint32_t flag)
|
||||
{
|
||||
uint32_t reg = NAND_REG_READ(INT_STATUS);
|
||||
|
||||
if (reg & (1 << NAND_ISR_CMDERROR))
|
||||
return 0;
|
||||
|
||||
if (reg & (1 << flag)) {
|
||||
NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* axs101_nand_write_buf - write buffer to chip
|
||||
* @mtd: MTD device structure
|
||||
* @buf: data buffer
|
||||
* @len: number of bytes to write
|
||||
*/
|
||||
static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
|
||||
int len)
|
||||
{
|
||||
struct bounce_buffer bbstate;
|
||||
|
||||
bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
|
||||
|
||||
/* Setup buffer descriptor */
|
||||
writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
|
||||
writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
|
||||
writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
|
||||
writel(0, &bd->buffer_ptr1);
|
||||
|
||||
/* Flush modified buffer descriptor */
|
||||
flush_dcache_range((unsigned long)bd,
|
||||
(unsigned long)bd + sizeof(struct nand_bd));
|
||||
|
||||
/* Issue "write" command */
|
||||
NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
|
||||
|
||||
/* Wait for NAND command and DMA to complete */
|
||||
while (!nand_flag_is_set(NAND_ISR_CMDDONE))
|
||||
;
|
||||
while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
|
||||
;
|
||||
|
||||
bounce_buffer_stop(&bbstate);
|
||||
}
|
||||
|
||||
/**
|
||||
* axs101_nand_read_buf - read chip data into buffer
|
||||
* @mtd: MTD device structure
|
||||
* @buf: buffer to store data
|
||||
* @len: number of bytes to read
|
||||
*/
|
||||
static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
struct bounce_buffer bbstate;
|
||||
|
||||
bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
|
||||
|
||||
/* Setup buffer descriptor */
|
||||
writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
|
||||
writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
|
||||
writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
|
||||
writel(0, &bd->buffer_ptr1);
|
||||
|
||||
/* Flush modified buffer descriptor */
|
||||
flush_dcache_range((unsigned long)bd,
|
||||
(unsigned long)bd + sizeof(struct nand_bd));
|
||||
|
||||
/* Issue "read" command */
|
||||
NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
|
||||
|
||||
/* Wait for NAND command and DMA to complete */
|
||||
while (!nand_flag_is_set(NAND_ISR_CMDDONE))
|
||||
;
|
||||
while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
|
||||
;
|
||||
|
||||
bounce_buffer_stop(&bbstate);
|
||||
}
|
||||
|
||||
/**
|
||||
* axs101_nand_read_byte - read one byte from the chip
|
||||
* @mtd: MTD device structure
|
||||
*/
|
||||
static u_char axs101_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
|
||||
return byte;
|
||||
}
|
||||
|
||||
/**
|
||||
* axs101_nand_read_word - read one word from the chip
|
||||
* @mtd: MTD device structure
|
||||
*/
|
||||
static u16 axs101_nand_read_word(struct mtd_info *mtd)
|
||||
{
|
||||
u16 word;
|
||||
|
||||
axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
|
||||
return word;
|
||||
}
|
||||
|
||||
/**
|
||||
* axs101_nand_hwcontrol - NAND control functions wrapper.
|
||||
* @mtd: MTD device structure
|
||||
* @cmd: Command
|
||||
*/
|
||||
static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
|
||||
unsigned int ctrl)
|
||||
{
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
cmd = cmd & 0xff;
|
||||
|
||||
switch (ctrl & (NAND_ALE | NAND_CLE)) {
|
||||
/* Address */
|
||||
case NAND_ALE:
|
||||
cmd |= B_CT_ADDRESS;
|
||||
break;
|
||||
|
||||
/* Command */
|
||||
case NAND_CLE:
|
||||
cmd |= B_CT_COMMAND | B_WFR;
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
debug("%s: unknown ctrl %#x\n", __func__, ctrl);
|
||||
}
|
||||
|
||||
NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
|
||||
while (!nand_flag_is_set(NAND_ISR_CMDDONE))
|
||||
;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
|
||||
sizeof(struct nand_bd));
|
||||
|
||||
/* Set buffer descriptor address in IDMAC */
|
||||
NAND_REG_WRITE(IDMAC_BDADDR, bd);
|
||||
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
nand->cmd_ctrl = axs101_nand_hwcontrol;
|
||||
nand->read_byte = axs101_nand_read_byte;
|
||||
nand->read_word = axs101_nand_read_word;
|
||||
nand->write_buf = axs101_nand_write_buf;
|
||||
nand->read_buf = axs101_nand_read_buf;
|
||||
|
||||
/* MBv3 has NAND IC with 16-bit data bus */
|
||||
if (gd->board_type == AXS_MB_V3)
|
||||
nand->options |= NAND_BUSWIDTH_16;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -83,10 +83,11 @@ Useful notes on bulding and using of U-Boot on ARC HS Development Kit (AKA HSDK)
|
|||
HSDK board.
|
||||
|
||||
Note that Python3 script is used for generation of a header, thus
|
||||
to get that done it's required to have Python3 with elftools installed.
|
||||
On CentOS/RHEL/Fedora this could be installed with:
|
||||
to get that done it's required to have Python3 with "pyelftools" installed.
|
||||
|
||||
"pyelftools" could be installed with help of "pip" even w/o root rights:
|
||||
------------------------->8----------------------
|
||||
sudo dnf install python3-pyelftools
|
||||
python3 -m pip install --user pyelftools
|
||||
------------------------->8----------------------
|
||||
|
||||
EXECUTING U-BOOT
|
||||
|
|
|
|||
|
|
@ -1096,6 +1096,16 @@ int board_fit_config_name_match(const char *name)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
|
||||
int fastboot_set_reboot_flag(void)
|
||||
{
|
||||
printf("Setting reboot to fastboot flag ...\n");
|
||||
env_set("dofastboot", "1");
|
||||
env_save();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TI_SECURE_DEVICE
|
||||
void board_fit_image_post_process(void **p_image, size_t *p_size)
|
||||
{
|
||||
|
|
@ -1107,15 +1117,5 @@ void board_tee_image_process(ulong tee_image, size_t tee_size)
|
|||
secure_tee_install((u32)tee_image);
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
|
||||
int fastboot_set_reboot_flag(void)
|
||||
{
|
||||
printf("Setting reboot to fastboot flag ...\n");
|
||||
env_set("dofastboot", "1");
|
||||
env_save();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1092,6 +1092,16 @@ int board_fit_config_name_match(const char *name)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
|
||||
int fastboot_set_reboot_flag(void)
|
||||
{
|
||||
printf("Setting reboot to fastboot flag ...\n");
|
||||
env_set("dofastboot", "1");
|
||||
env_save();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TI_SECURE_DEVICE
|
||||
void board_fit_image_post_process(void **p_image, size_t *p_size)
|
||||
{
|
||||
|
|
@ -1103,15 +1113,5 @@ void board_tee_image_process(ulong tee_image, size_t tee_size)
|
|||
secure_tee_install((u32)tee_image);
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
|
||||
int fastboot_set_reboot_flag(void)
|
||||
{
|
||||
printf("Setting reboot to fastboot flag ...\n");
|
||||
env_set("dofastboot", "1");
|
||||
env_save();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -155,11 +155,13 @@ __weak void tqma6_iomuxc_spi(void)
|
|||
ARRAY_SIZE(tqma6_ecspi1_pads));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return ((bus == CONFIG_SF_DEFAULT_BUS) &&
|
||||
(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct i2c_pads_info tqma6_i2c3_pads = {
|
||||
/* I2C3: on board LM75, M24C64, */
|
||||
|
|
|
|||
12
cmd/Kconfig
12
cmd/Kconfig
|
|
@ -1040,10 +1040,20 @@ config CMD_SF_TEST
|
|||
everything is working properly.
|
||||
|
||||
config CMD_SPI
|
||||
bool "sspi"
|
||||
bool "sspi - Command to access spi device"
|
||||
help
|
||||
SPI utility command.
|
||||
|
||||
config DEFAULT_SPI_BUS
|
||||
int "default spi bus used by sspi command"
|
||||
depends on CMD_SPI
|
||||
default 0
|
||||
|
||||
config DEFAULT_SPI_MODE
|
||||
hex "default spi mode used by sspi command (see include/spi.h)"
|
||||
depends on CMD_SPI
|
||||
default 0
|
||||
|
||||
config CMD_TSI148
|
||||
bool "tsi148 - Command to access tsi148 device"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <fastboot.h>
|
||||
#include <net.h>
|
||||
#include <usb.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
static int do_fastboot_udp(int argc, char *const argv[],
|
||||
uintptr_t buf_addr, size_t buf_size)
|
||||
|
|
@ -74,6 +75,7 @@ static int do_fastboot_usb(int argc, char *const argv[],
|
|||
break;
|
||||
if (ctrlc())
|
||||
break;
|
||||
WATCHDOG_RESET();
|
||||
usb_gadget_handle_interrupts(controller_index);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -80,7 +80,6 @@ static void efi_dump_single_var(u16 *name, efi_guid_t *guid)
|
|||
printf(", DataSize = 0x%zx\n", size);
|
||||
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, data, size, true);
|
||||
|
||||
return;
|
||||
out:
|
||||
free(data);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,13 +22,6 @@
|
|||
# define MAX_SPI_BYTES 32 /* Maximum number of bytes we can handle */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DEFAULT_SPI_BUS
|
||||
# define CONFIG_DEFAULT_SPI_BUS 0
|
||||
#endif
|
||||
#ifndef CONFIG_DEFAULT_SPI_MODE
|
||||
# define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Values from last command.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -53,8 +53,8 @@ bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr,
|
|||
entry_size = fdt32_to_cpu(hdr->dt_entry_size);
|
||||
unmap_sysmem(hdr);
|
||||
|
||||
if (index > entry_count) {
|
||||
printf("Error: index > dt_entry_count (%u > %u)\n", index,
|
||||
if (index >= entry_count) {
|
||||
printf("Error: index >= dt_entry_count (%u >= %u)\n", index,
|
||||
entry_count);
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -491,6 +491,10 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
|
|||
|
||||
if (!spl_fit_image_get_os(fit, node, &os_type))
|
||||
debug("Loadable is %s\n", genimg_get_os_name(os_type));
|
||||
#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
|
||||
else
|
||||
os_type = IH_OS_U_BOOT;
|
||||
#endif
|
||||
|
||||
if (os_type == IH_OS_U_BOOT) {
|
||||
spl_fit_append_fdt(&image_info, info, sector,
|
||||
|
|
|
|||
|
|
@ -41,6 +41,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -41,6 +41,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ CONFIG_ENV_IS_IN_REMOTE=y
|
|||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ CONFIG_FSL_CAAM=y
|
|||
# CONFIG_MMC is not set
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ CONFIG_FSL_CAAM=y
|
|||
# CONFIG_MMC is not set
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -39,6 +39,8 @@ CONFIG_FLASH_CFI_MTD=y
|
|||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -39,6 +39,8 @@ CONFIG_FLASH_CFI_MTD=y
|
|||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@ CONFIG_CMD_CACHE=y
|
|||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=2
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=1
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=1
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=1
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ CONFIG_CMD_PING=y
|
|||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=1
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_ISO_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=1
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ CONFIG_MTD_NOR_FLASH=y
|
|||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ CONFIG_MTD_NOR_FLASH=y
|
|||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ CONFIG_MTD_NOR_FLASH=y
|
|||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ CONFIG_MTD_NOR_FLASH=y
|
|||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue