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https://github.com/AsahiLinux/u-boot
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ARM: orion5x: fix use of callee-saved registers in lowloevel_init
The lowlevel_init function uses r4 and r6 without preserving their values as required by the AAPCS. Use r0 and r2 instead as these are call-clobbered. Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Chris Packham <judge.packham@gmail.com>
This commit is contained in:
Mans Rullgard
Tom Rini
parent
3eceff642c
commit
66a00be287
1 changed files with 84 additions and 84 deletions
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@ -71,67 +71,67 @@ lowlevel_init:
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#ifdef CONFIG_SPL_BUILD
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/* Use 'r4 as the base for internal register accesses */
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ldr r4, =ORION5X_REGS_PHY_BASE
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/* Use 'r2 as the base for internal register accesses */
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ldr r2, =ORION5X_REGS_PHY_BASE
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/* move internal registers from the default 0xD0000000
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* to their intended location, defined by SoC */
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ldr r3, =0xD0000000
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add r3, r3, #0x20000
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str r4, [r3, #0x80]
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str r2, [r3, #0x80]
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/* Use R3 as the base for DRAM registers */
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add r3, r4, #0x01000
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add r3, r2, #0x01000
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/*DDR SDRAM Initialization Control */
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ldr r6, =0x00000001
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str r6, [r3, #0x480]
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ldr r0, =0x00000001
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str r0, [r3, #0x480]
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/* Use R3 as the base for PCI registers */
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add r3, r4, #0x31000
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add r3, r2, #0x31000
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/* Disable arbiter */
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ldr r6, =0x00000030
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str r6, [r3, #0xd00]
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ldr r0, =0x00000030
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str r0, [r3, #0xd00]
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/* Use R3 as the base for DRAM registers */
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add r3, r4, #0x01000
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add r3, r2, #0x01000
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/* set all dram windows to 0 */
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mov r6, #0
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str r6, [r3, #0x504]
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str r6, [r3, #0x50C]
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str r6, [r3, #0x514]
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str r6, [r3, #0x51C]
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mov r0, #0
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str r0, [r3, #0x504]
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str r0, [r3, #0x50C]
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str r0, [r3, #0x514]
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str r0, [r3, #0x51C]
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/* 1) Configure SDRAM */
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ldr r6, =SDRAM_CONFIG
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str r6, [r3, #0x400]
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ldr r0, =SDRAM_CONFIG
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str r0, [r3, #0x400]
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/* 2) Set SDRAM Control reg */
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ldr r6, =SDRAM_CONTROL
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str r6, [r3, #0x404]
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ldr r0, =SDRAM_CONTROL
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str r0, [r3, #0x404]
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/* 3) Write SDRAM address control register */
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ldr r6, =SDRAM_ADDR_CTRL
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str r6, [r3, #0x410]
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ldr r0, =SDRAM_ADDR_CTRL
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str r0, [r3, #0x410]
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/* 4) Write SDRAM bank 0 size register */
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ldr r6, =SDRAM_BANK0_SIZE
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str r6, [r3, #0x504]
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ldr r0, =SDRAM_BANK0_SIZE
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str r0, [r3, #0x504]
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/* keep other banks disabled */
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/* 5) Write SDRAM open pages control register */
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ldr r6, =SDRAM_OPEN_PAGE_EN
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str r6, [r3, #0x414]
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ldr r0, =SDRAM_OPEN_PAGE_EN
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str r0, [r3, #0x414]
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/* 6) Write SDRAM timing Low register */
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ldr r6, =SDRAM_TIME_CTRL_LOW
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str r6, [r3, #0x408]
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ldr r0, =SDRAM_TIME_CTRL_LOW
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str r0, [r3, #0x408]
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/* 7) Write SDRAM timing High register */
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ldr r6, =SDRAM_TIME_CTRL_HI
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str r6, [r3, #0x40C]
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ldr r0, =SDRAM_TIME_CTRL_HI
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str r0, [r3, #0x40C]
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/* 8) Write SDRAM mode register */
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/* The CPU must not attempt to change the SDRAM Mode register setting */
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@ -142,73 +142,73 @@ lowlevel_init:
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/* and then sets SDRAM Mode register to its new value. */
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/* 8.1 write 'nop' to SDRAM operation */
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ldr r6, =SDRAM_OP_NOP
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str r6, [r3, #0x418]
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ldr r0, =SDRAM_OP_NOP
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str r0, [r3, #0x418]
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/* 8.2 poll SDRAM operation until back in 'normal' mode. */
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1:
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ldr r6, [r3, #0x418]
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cmp r6, #0
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ldr r0, [r3, #0x418]
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cmp r0, #0
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bne 1b
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/* 8.3 Now its safe to write new value to SDRAM Mode register */
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ldr r6, =SDRAM_MODE
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str r6, [r3, #0x41C]
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ldr r0, =SDRAM_MODE
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str r0, [r3, #0x41C]
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/* 8.4 Set new mode */
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ldr r6, =SDRAM_OP_SETMODE
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str r6, [r3, #0x418]
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ldr r0, =SDRAM_OP_SETMODE
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str r0, [r3, #0x418]
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/* 8.5 poll SDRAM operation until back in 'normal' mode. */
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2:
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ldr r6, [r3, #0x418]
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cmp r6, #0
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ldr r0, [r3, #0x418]
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cmp r0, #0
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bne 2b
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/* DDR SDRAM Address/Control Pads Calibration */
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ldr r6, [r3, #0x4C0]
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ldr r0, [r3, #0x4C0]
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/* Set Bit [31] to make the register writable */
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orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
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str r6, [r3, #0x4C0]
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orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
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str r0, [r3, #0x4C0]
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bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
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bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
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bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
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bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
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bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
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bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
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bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
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bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
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/* Get the final N locked value of driving strength [22:17] */
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mov r1, r6
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mov r1, r0
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mov r1, r1, LSL #9
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mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
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orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
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/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
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orr r6, r6, r1
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str r6, [r3, #0x4C0]
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orr r0, r0, r1
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str r0, [r3, #0x4C0]
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/* DDR SDRAM Data Pads Calibration */
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ldr r6, [r3, #0x4C4]
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ldr r0, [r3, #0x4C4]
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/* Set Bit [31] to make the register writable */
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orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
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str r6, [r3, #0x4C4]
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orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
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str r0, [r3, #0x4C4]
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bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
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bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
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bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
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bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
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bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
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bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
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bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
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bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
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/* Get the final N locked value of driving strength [22:17] */
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mov r1, r6
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mov r1, r0
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mov r1, r1, LSL #9
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mov r1, r1, LSR #26
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orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
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/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
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orr r6, r6, r1
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orr r0, r0, r1
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str r6, [r3, #0x4C4]
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str r0, [r3, #0x4C4]
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/* Implement Guideline (GL# MEM-3) Drive Strength Value */
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/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
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@ -216,37 +216,37 @@ lowlevel_init:
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ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
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/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
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ldr r6, [r3, #0x4C0]
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orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
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str r6, [r3, #0x4C0]
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ldr r0, [r3, #0x4C0]
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orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
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str r0, [r3, #0x4C0]
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/* Correct strength and disable writes again */
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bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
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bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
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orr r6, r6, r1
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str r6, [r3, #0x4C0]
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bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
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bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
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orr r0, r0, r1
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str r0, [r3, #0x4C0]
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/* Enable writes to DDR SDRAM Data Pads Calibration register */
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ldr r6, [r3, #0x4C4]
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orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
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str r6, [r3, #0x4C4]
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ldr r0, [r3, #0x4C4]
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orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
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str r0, [r3, #0x4C4]
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/* Correct strength and disable writes again */
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bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
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bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
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orr r6, r6, r1
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str r6, [r3, #0x4C4]
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bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
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bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
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orr r0, r0, r1
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str r0, [r3, #0x4C4]
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/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
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/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
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/* Get the "sample on reset" register for the DDR frequancy */
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ldr r3, =0x10000
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ldr r6, [r3, #0x010]
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ldr r0, [r3, #0x010]
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ldr r1, =MSAR_ARMDDRCLCK_MASK
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and r1, r6, r1
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and r1, r0, r1
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ldr r6, =FTDLL_DDR1_166MHZ
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ldr r0, =FTDLL_DDR1_166MHZ
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cmp r1, #MSAR_ARMDDRCLCK_333_167
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beq 3f
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cmp r1, #MSAR_ARMDDRCLCK_500_167
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@ -254,7 +254,7 @@ lowlevel_init:
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cmp r1, #MSAR_ARMDDRCLCK_667_167
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beq 3f
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ldr r6, =FTDLL_DDR1_200MHZ
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ldr r0, =FTDLL_DDR1_200MHZ
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cmp r1, #MSAR_ARMDDRCLCK_400_200_1
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beq 3f
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cmp r1, #MSAR_ARMDDRCLCK_400_200
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@ -264,21 +264,21 @@ lowlevel_init:
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cmp r1, #MSAR_ARMDDRCLCK_800_200
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beq 3f
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ldr r6, =0
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ldr r0, =0
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3:
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/* Use R3 as the base for DRAM registers */
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add r3, r4, #0x01000
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add r3, r2, #0x01000
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ldr r2, [r3, #0x484]
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orr r2, r2, r6
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orr r2, r2, r0
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str r2, [r3, #0x484]
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/* enable for 2 GB DDR; detection should find out real amount */
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sub r6, r6, r6
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str r6, [r3, #0x500]
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ldr r6, =0x7fff0001
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str r6, [r3, #0x504]
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sub r0, r0, r0
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str r0, [r3, #0x500]
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ldr r0, =0x7fff0001
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str r0, [r3, #0x504]
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#endif /* CONFIG_SPL_BUILD */
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