mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 15:12:04 +00:00
- kwboot: Misc improvements and fixes (Pali) - Kirkwood: Move to DM ethernet support for some boards (Tony) - Minor misc stuff
This commit is contained in:
Tom Rini
commit
6662e5e406
19 changed files with 120 additions and 332 deletions
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@ -278,11 +278,20 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
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F: arch/arm/mach-kirkwood/
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F: arch/arm/mach-mvebu/
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F: drivers/ata/ahci_mvebu.c
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F: drivers/clk/mvebu/
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F: drivers/ddr/marvell/
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F: drivers/gpio/mvebu_gpio.c
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F: drivers/i2c/mvtwsi.c
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F: drivers/mmc/xenon_sdhci.c
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F: drivers/phy/marvell/
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F: drivers/pinctrl/mvebu/
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F: drivers/rtc/armada38x.c
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F: drivers/spi/kirkwood_spi.c
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F: drivers/spi/mvebu_a3700_spi.c
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F: drivers/pci/pcie_dw_mvebu.c
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F: drivers/watchdog/armada-37xx-wdt.c
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F: drivers/watchdog/orion_wdt.c
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F: include/configs/mv-common.h
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ARM MARVELL PCIE CONTROLLER DRIVERS
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M: Pali Rohár <pali@kernel.org>
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@ -1,4 +1,5 @@
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DREAMPLUG BOARD
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M: Tony Dinh <mibodhi@gmail.com>
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M: Jason Cooper <u-boot@lakedaemon.net>
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S: Maintained
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F: board/Marvell/dreamplug/
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@ -1,8 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com>
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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* Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2011 Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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@ -11,16 +10,19 @@
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#include <common.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/global_data.h>
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#include "dreamplug.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DREAMPLUG_OE_LOW (~(0))
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#define DREAMPLUG_OE_HIGH (~(0))
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#define DREAMPLUG_OE_VAL_LOW 0
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#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
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int board_early_init_f(void)
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{
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/*
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@ -90,83 +92,15 @@ int board_early_init_f(void)
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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return cpu_eth_init(bis);
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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static int fdt_get_phy_addr(const char *path)
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{
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const void *fdt = gd->fdt_blob;
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const u32 *reg;
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const u32 *val;
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int node, phandle, addr;
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/* Find the node by its full path */
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node = fdt_path_offset(fdt, path);
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if (node >= 0) {
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/* Look up phy-handle */
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val = fdt_getprop(fdt, node, "phy-handle", NULL);
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if (val) {
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phandle = fdt32_to_cpu(*val);
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if (!phandle)
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return -1;
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/* Follow it to its node */
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node = fdt_node_offset_by_phandle(fdt, phandle);
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if (node) {
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/* Look up reg */
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reg = fdt_getprop(fdt, node, "reg", NULL);
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if (reg) {
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addr = fdt32_to_cpu(*reg);
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return addr;
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}
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}
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}
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}
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return -1;
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}
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#ifdef CONFIG_RESET_PHY_R
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void mv_phy_88e1116_init(const char *name, const char *path)
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{
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u16 reg;
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int phyaddr;
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if (miiphy_set_current_dev(name))
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return;
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phyaddr = fdt_get_phy_addr(path);
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if (phyaddr < 0)
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return;
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL2_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL2_REG, reg);
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, phyaddr);
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printf("88E1116 Initialized on %s\n", name);
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}
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void reset_phy(void)
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{
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char *eth0_name = "ethernet-controller@72000";
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char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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char *eth1_name = "ethernet-controller@76000";
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char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0";
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/* configure and initialize both PHY's */
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mv_phy_88e1116_init(eth0_name, eth0_path);
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mv_phy_88e1116_init(eth1_name, eth1_path);
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}
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#endif /* CONFIG_RESET_PHY_R */
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@ -1,25 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*/
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#ifndef __DREAMPLUG_H
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#define __DREAMPLUG_H
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#define DREAMPLUG_OE_LOW (~(0))
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#define DREAMPLUG_OE_HIGH (~(0))
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#define DREAMPLUG_OE_VAL_LOW 0
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#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
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/* PHY related */
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#define MV88E1116_MAC_CTRL2_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __DREAMPLUG_H */
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@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
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*
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* Based on sheevaplug.c originally written by
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@ -11,18 +12,22 @@
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#include <common.h>
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#include <bootstage.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/cpu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include "dockstar.h"
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define DOCKSTAR_OE_LOW (~(0))
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#define DOCKSTAR_OE_HIGH (~(0))
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#define DOCKSTAR_OE_VAL_LOW BIT(29) /* USB_PWEN low */
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#define DOCKSTAR_OE_VAL_HIGH BIT(17) /* LED pin high */
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int board_early_init_f(void)
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{
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/*
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@ -92,6 +97,11 @@ int board_early_init_f(void)
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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return cpu_eth_init(bis);
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}
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int board_init(void)
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{
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/*
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@ -105,53 +115,21 @@ int board_init(void)
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__FUNCTION__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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#if CONFIG_IS_ENABLED(BOOTSTAGE)
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#define GREEN_LED (1 << 14)
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#define ORANGE_LED (1 << 15)
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#define GREEN_LED BIT(14)
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#define ORANGE_LED BIT(15)
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#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
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#define NEITHER_LED 0
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static void set_leds(u32 leds, u32 blinking)
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{
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struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
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u32 oe = readl(&r->oe) | BOTH_LEDS;
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u32 oe;
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u32 bl;
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oe = readl(&r->oe) | BOTH_LEDS;
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writel(oe & ~leds, &r->oe); /* active low */
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u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
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bl = readl(&r->blink_en) & ~BOTH_LEDS;
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writel(bl | blinking, &r->blink_en);
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}
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
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*
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* Based on sheevaplug.h originally written by
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* Prafulla Wadaskar <prafulla@marvell.com>
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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*/
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#ifndef __DOCKSTAR_H
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#define __DOCKSTAR_H
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#define DOCKSTAR_OE_LOW (~(0))
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#define DOCKSTAR_OE_HIGH (~(0))
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#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
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#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
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/* PHY related */
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __DOCKSTAR_H */
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@ -1,5 +1,6 @@
|
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
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* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
|
||||
* Copyright (C) 2012
|
||||
* David Purdy <david.c.purdy@gmail.com>
|
||||
*
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@ -12,16 +13,21 @@
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#include <common.h>
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#include <init.h>
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#include <log.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
|
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/global_data.h>
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#include "pogo_e02.h"
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#include <linux/bitops.h>
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|
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DECLARE_GLOBAL_DATA_PTR;
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|
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/* GPIO configuration */
|
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#define POGO_E02_OE_LOW (~(0))
|
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#define POGO_E02_OE_HIGH (~(0))
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#define POGO_E02_OE_VAL_LOW BIT(29)
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#define POGO_E02_OE_VAL_HIGH 0
|
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|
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int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -64,6 +70,11 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
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int board_eth_init(struct bd_info *bis)
|
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{
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Boot parameters address */
|
||||
|
|
@ -71,37 +82,3 @@ int board_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
/* Configure and initialize PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
u16 reg;
|
||||
u16 devadr;
|
||||
char *name = "egiga0";
|
||||
|
||||
if (miiphy_set_current_dev(name))
|
||||
return;
|
||||
|
||||
/* command to read PHY dev address */
|
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
|
||||
printf("Err..(%s) could not read PHY dev address\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port
|
||||
* Ref: sec 4.7.2 of chip datasheet
|
||||
*/
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
|
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
|
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
||||
|
||||
/* reset the phy */
|
||||
miiphy_reset(name, devadr);
|
||||
|
||||
debug("88E1116 Initialized on %s\n", name);
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2012
|
||||
* David Purdy <david.c.purdy@gmail.com>
|
||||
*
|
||||
* Based on Kirkwood support:
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __POGO_E02_H
|
||||
#define __POGO_E02_H
|
||||
|
||||
/* GPIO configuration */
|
||||
#define POGO_E02_OE_LOW (~(0))
|
||||
#define POGO_E02_OE_HIGH (~(0))
|
||||
#define POGO_E02_OE_VAL_LOW (1 << 29)
|
||||
#define POGO_E02_OE_VAL_HIGH 0
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __POGO_E02_H */
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
|
||||
* Copyright (C) 2009-2012
|
||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
* Luka Perkov <luka@openwrt.org>
|
||||
|
|
@ -7,15 +8,20 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/mpp.h>
|
||||
#include <asm/global_data.h>
|
||||
#include "iconnect.h"
|
||||
#include <linux/bitops.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define ICONNECT_OE_LOW (~BIT(7))
|
||||
#define ICONNECT_OE_HIGH (~BIT(10))
|
||||
#define ICONNECT_OE_VAL_LOW (0)
|
||||
#define ICONNECT_OE_VAL_HIGH BIT(10)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -85,9 +91,14 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2009-2012
|
||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
* Luka Perkov <luka@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef __ICONNECT_H
|
||||
#define __ICONNECT_H
|
||||
|
||||
#define ICONNECT_OE_LOW (~(1 << 7))
|
||||
#define ICONNECT_OE_HIGH (~(1 << 10))
|
||||
#define ICONNECT_OE_VAL_LOW (0)
|
||||
#define ICONNECT_OE_VAL_HIGH (1 << 10)
|
||||
|
||||
/* PHY related */
|
||||
#define MV88E1116_LED_FCTRL_REG 10
|
||||
#define MV88E1116_CPRSP_CR3_REG 21
|
||||
#define MV88E1116_MAC_CTRL_REG 21
|
||||
#define MV88E1116_PGADR_REG 22
|
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
|
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
|
||||
|
||||
#endif /* __ICONNECT_H */
|
||||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_KIRKWOOD=y
|
||||
CONFIG_SYS_KWD_CONFIG="board/Seagate/dockstar/kwbimage.cfg"
|
||||
CONFIG_SYS_TEXT_BASE=0x600000
|
||||
|
|
@ -18,6 +19,7 @@ CONFIG_USE_BOOTCOMMAND=y
|
|||
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; ubifsload 0x1100000 ${initrd}; bootm 0x800000 0x1100000"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="DockStar> "
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
|
|
@ -36,11 +38,14 @@ CONFIG_ISO_PARTITION=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MVGBE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ CONFIG_SYS_ATA_ALT_OFFSET=0x100
|
|||
CONFIG_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MVGBE=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi
|
|||
CONFIG_USE_PREBOOT=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SYS_PROMPT="iconnect => "
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="iConnect> "
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_PCI=y
|
||||
|
|
@ -39,11 +40,14 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MVGBE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCI=y
|
||||
|
|
|
|||
|
|
@ -2,13 +2,14 @@ CONFIG_ARM=y
|
|||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_KIRKWOOD=y
|
||||
CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_e02/kwbimage.cfg"
|
||||
CONFIG_SYS_TEXT_BASE=0x600000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_TARGET_POGO_E02=y
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0x60000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
|
||||
CONFIG_IDENT_STRING="\nPogo E02"
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -36,11 +37,14 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MVGBE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
|
||||
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
|
||||
*
|
||||
* Based on sheevaplug.h originally written by
|
||||
|
|
@ -17,14 +18,6 @@
|
|||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
/*
|
||||
* max 4k env size is enough, but in case of nand
|
||||
* it has to be rounded to sector size
|
||||
*/
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
|
|
@ -32,7 +25,7 @@
|
|||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console=console=ttyS0,115200\0" \
|
||||
"mtdids=nand0=orion_nand\0" \
|
||||
"mtdparts="CONFIG_MTDPARTS_DEFAULT \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT \
|
||||
"kernel=/boot/uImage\0" \
|
||||
"initrd=/boot/uInitrd\0" \
|
||||
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
|
||||
|
|
@ -40,13 +33,10 @@
|
|||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
|
||||
#endif
|
||||
|
||||
#endif /* _CONFIG_DOCKSTAR_H */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Jason Cooper <u-boot@lakedaemon.net>
|
||||
* (C) Copyright 2022 Tony Dinh <mibodhi@gmail.com>
|
||||
* (C) Copyright 2011 Jason Cooper <u-boot@lakedaemon.net>
|
||||
*
|
||||
* Based on work by:
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
|
|
@ -13,15 +13,6 @@
|
|||
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
|
||||
/*
|
||||
* max 4k env size is enough, but in case of nand
|
||||
* it has to be rounded to sector size
|
||||
*/
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
|
|
@ -36,16 +27,15 @@
|
|||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SATA Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_SATA
|
||||
#define CONFIG_LBA48
|
||||
#endif /* CONFIG_SATA */
|
||||
|
||||
#endif /* _CONFIG_DREAMPLUG_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
|
||||
* (C) Copyright 2009-2012
|
||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
|
||||
* Luka Perkov <luka@openwrt.org>
|
||||
|
|
@ -10,32 +11,24 @@
|
|||
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Environment variables configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console=console=ttyS0,115200\0" \
|
||||
"mtdids=nand0=orion_nand\0" \
|
||||
"mtdparts="CONFIG_MTDPARTS_DEFAULT \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT \
|
||||
"kernel=/boot/uImage\0" \
|
||||
"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
|
||||
|
||||
/*
|
||||
* Ethernet driver configuration
|
||||
*
|
||||
* This board has PCIe Wifi card, so allow Ethernet to be disabled
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 11
|
||||
#undef CONFIG_RESET_PHY_R
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
|
||||
#endif
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
|
||||
#endif /* _CONFIG_ICONNECT_H */
|
||||
|
|
|
|||
|
|
@ -14,10 +14,6 @@
|
|||
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
|
|
@ -33,13 +29,10 @@
|
|||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#ifdef CONFIG_RESET_PHY_R
|
||||
#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
|
||||
#endif
|
||||
|
||||
#endif /* _CONFIG_POGO_E02_H */
|
||||
|
|
|
|||
|
|
@ -1183,10 +1183,10 @@ kwboot_xmodem(int tty, const void *_img, size_t size, int baudrate)
|
|||
static int
|
||||
kwboot_term_pipe(int in, int out, const char *quit, int *s)
|
||||
{
|
||||
char buf[128];
|
||||
ssize_t nin;
|
||||
char _buf[128], *buf = _buf;
|
||||
|
||||
nin = read(in, buf, sizeof(_buf));
|
||||
nin = read(in, buf, sizeof(buf));
|
||||
if (nin <= 0)
|
||||
return -1;
|
||||
|
||||
|
|
@ -1194,18 +1194,21 @@ kwboot_term_pipe(int in, int out, const char *quit, int *s)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < nin; i++) {
|
||||
if (*buf == quit[*s]) {
|
||||
if (buf[i] == quit[*s]) {
|
||||
(*s)++;
|
||||
if (!quit[*s])
|
||||
return 0;
|
||||
buf++;
|
||||
nin--;
|
||||
if (!quit[*s]) {
|
||||
nin = i - *s;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (kwboot_write(out, quit, *s) < 0)
|
||||
if (*s > i && kwboot_write(out, quit, *s - i) < 0)
|
||||
return -1;
|
||||
*s = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == nin)
|
||||
nin -= *s;
|
||||
}
|
||||
|
||||
if (kwboot_write(out, buf, nin) < 0)
|
||||
|
|
@ -1767,7 +1770,7 @@ main(int argc, char **argv)
|
|||
bootmsg = kwboot_msg_boot;
|
||||
if (prev_optind == optind)
|
||||
goto usage;
|
||||
if (argv[optind] && argv[optind][0] != '-')
|
||||
if (optind < argc - 1 && argv[optind] && argv[optind][0] != '-')
|
||||
imgpath = argv[optind++];
|
||||
break;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue