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https://github.com/AsahiLinux/u-boot
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imx: mx6dlarm2: Add support for i.MX6Q/DL arm2 LPDDR2 boards
Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2 arm2 board. Since the LPDDR2 arm2 board has different DDR size, use CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE. Signed-off-by: Ye.Li <B37916@freescale.com>
This commit is contained in:
Ye.Li
Stefano Babic
parent
b357503f1c
commit
661139faf7
9 changed files with 518 additions and 14 deletions
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@ -6,3 +6,5 @@ F: board/freescale/mx6qarm2/
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F: include/configs/mx6qarm2.h
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F: configs/mx6qarm2_defconfig
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F: configs/mx6dlarm2_defconfig
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F: configs/mx6qarm2_lpddr2_defconfig
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F: configs/mx6dlarm2_lpddr2_defconfig
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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@ -30,6 +30,185 @@ BOOT_FROM sd
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#ifdef CONFIG_MX6DQ_LPDDR2
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/* DCD */
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DATA 4 0x020C4018 0x60324
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DATA 4 0x020E05a8 0x00003038
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DATA 4 0x020E05b0 0x00003038
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DATA 4 0x020E0524 0x00003038
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DATA 4 0x020E051c 0x00003038
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DATA 4 0x020E0518 0x00003038
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DATA 4 0x020E050c 0x00003038
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DATA 4 0x020E05b8 0x00003038
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DATA 4 0x020E05c0 0x00003038
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DATA 4 0x020E05ac 0x00000038
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DATA 4 0x020E05b4 0x00000038
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DATA 4 0x020E0528 0x00000038
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DATA 4 0x020E0520 0x00000038
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DATA 4 0x020E0514 0x00000038
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DATA 4 0x020E0510 0x00000038
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DATA 4 0x020E05bc 0x00000038
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DATA 4 0x020E05c4 0x00000038
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DATA 4 0x020E056c 0x00000038
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DATA 4 0x020E0578 0x00000038
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DATA 4 0x020E0588 0x00000038
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DATA 4 0x020E0594 0x00000038
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DATA 4 0x020E057c 0x00000038
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DATA 4 0x020E0590 0x00000038
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DATA 4 0x020E0598 0x00000038
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DATA 4 0x020E058c 0x00000000
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DATA 4 0x020E059c 0x00000038
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DATA 4 0x020E05a0 0x00000038
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DATA 4 0x020E0784 0x00000038
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DATA 4 0x020E0788 0x00000038
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DATA 4 0x020E0794 0x00000038
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DATA 4 0x020E079c 0x00000038
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DATA 4 0x020E07a0 0x00000038
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DATA 4 0x020E07a4 0x00000038
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DATA 4 0x020E07a8 0x00000038
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DATA 4 0x020E0748 0x00000038
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DATA 4 0x020E074c 0x00000038
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DATA 4 0x020E0750 0x00020000
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DATA 4 0x020E0758 0x00000000
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DATA 4 0x020E0774 0x00020000
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DATA 4 0x020E078c 0x00000038
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DATA 4 0x020E0798 0x00080000
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b401c 0x00008000
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DATA 4 0x021b085c 0x1b5f01ff
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DATA 4 0x021b485c 0x1b5f01ff
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DATA 4 0x021b0800 0xa1390000
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DATA 4 0x021b4800 0xa1390000
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DATA 4 0x021b0890 0x00400000
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DATA 4 0x021b4890 0x00400000
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DATA 4 0x021b48bc 0x00055555
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b48b8 0x00000800
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b481c 0x33333333
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DATA 4 0x021b4820 0x33333333
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DATA 4 0x021b4824 0x33333333
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DATA 4 0x021b4828 0x33333333
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DATA 4 0x021b082c 0xf3333333
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DATA 4 0x021b0830 0xf3333333
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DATA 4 0x021b0834 0xf3333333
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DATA 4 0x021b0838 0xf3333333
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DATA 4 0x021b482c 0xf3333333
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DATA 4 0x021b4830 0xf3333333
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DATA 4 0x021b4834 0xf3333333
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DATA 4 0x021b4838 0xf3333333
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DATA 4 0x021b0848 0x49383b39
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DATA 4 0x021b0850 0x30364738
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DATA 4 0x021b4848 0x3e3c3846
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DATA 4 0x021b4850 0x4c294b35
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DATA 4 0x021b083c 0x20000000
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DATA 4 0x021b0840 0x0
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DATA 4 0x021b483c 0x20000000
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DATA 4 0x021b4840 0x0
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DATA 4 0x021b0858 0xf00
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DATA 4 0x021b4858 0xf00
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DATA 4 0x021b08b8 0x800
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DATA 4 0x021b48b8 0x800
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DATA 4 0x021b000c 0x555a61a5
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DATA 4 0x021b0004 0x20036
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DATA 4 0x021b0010 0x160e83
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DATA 4 0x021b0014 0xdd
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DATA 4 0x021b0018 0x8174c
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DATA 4 0x021b002c 0xf9f26d2
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DATA 4 0x021b0030 0x20e
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DATA 4 0x021b0038 0x200aac
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DATA 4 0x021b0008 0x0
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DATA 4 0x021b0040 0x5f
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DATA 4 0x021b0000 0xc3010000
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DATA 4 0x021b400c 0x555a61a5
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DATA 4 0x021b4004 0x20036
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DATA 4 0x021b4010 0x160e83
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DATA 4 0x021b4014 0xdd
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DATA 4 0x021b4018 0x8174c
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DATA 4 0x021b402c 0xf9f26d2
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DATA 4 0x021b4030 0x20e
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DATA 4 0x021b4038 0x200aac
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DATA 4 0x021b4008 0x0
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DATA 4 0x021b4040 0x3f
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DATA 4 0x021b4000 0xc3010000
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DATA 4 0x021b001c 0x3f8030
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DATA 4 0x021b001c 0xff0a8030
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DATA 4 0x021b001c 0xc2018030
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DATA 4 0x021b001c 0x6028030
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DATA 4 0x021b001c 0x2038030
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DATA 4 0x021b401c 0x3f8030
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DATA 4 0x021b401c 0xff0a8030
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DATA 4 0x021b401c 0xc2018030
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DATA 4 0x021b401c 0x6028030
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DATA 4 0x021b401c 0x2038030
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b4800 0xa1390003
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DATA 4 0x021b0020 0x7800
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DATA 4 0x021b4020 0x7800
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DATA 4 0x021b0818 0x0
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DATA 4 0x021b4818 0x0
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b4800 0xa1390003
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DATA 4 0x021b08b8 0x800
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DATA 4 0x021b48b8 0x800
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DATA 4 0x021b001c 0x0
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DATA 4 0x021b401c 0x0
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DATA 4 0x021b0404 0x00011006
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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DATA 4 0x020c407c 0x0F0000C3
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DATA 4 0x020c4080 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4 0x020e0010 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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#else
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DATA 4 0x020e05a8 0x00000030
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DATA 4 0x020e05b0 0x00000030
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DATA 4 0x020e0524 0x00000030
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@ -142,12 +321,8 @@ DATA 4 0x021b48b8 0x00000800
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DATA 4 0x021b001c 0x00000000
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DATA 4 0x021b0404 0x00011006
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DATA 4 0x020e0010 0xF00000FF
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DATA 4 0x020e0018 0x00070007
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DATA 4 0x020e001c 0x00070007
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC00
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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@ -159,3 +334,5 @@ DATA 4 0x020e0010 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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#endif /* CONFIG_MX6DQ_LPDDR2 */
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@ -30,6 +30,324 @@ BOOT_FROM sd
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#ifdef CONFIG_MX6DL_LPDDR2
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/* IOMUX SETTINGS */
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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DATA 4 0x020E04bc 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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DATA 4 0x020E04c0 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
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DATA 4 0x020E04c4 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
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DATA 4 0x020E04c8 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
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DATA 4 0x020E04cc 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
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DATA 4 0x020E04d0 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
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DATA 4 0x020E04d4 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
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DATA 4 0x020E04d8 0x00003028
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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DATA 4 0x020E0470 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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DATA 4 0x020E0474 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
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DATA 4 0x020E0478 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
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DATA 4 0x020E047c 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
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DATA 4 0x020E0480 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
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DATA 4 0x020E0484 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
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DATA 4 0x020E0488 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
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DATA 4 0x020E048c 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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DATA 4 0x020E0464 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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DATA 4 0x020E0490 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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DATA 4 0x020E04ac 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
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DATA 4 0x020E04b0 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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DATA 4 0x020E0494 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
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DATA 4 0x020E04a4 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
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DATA 4 0x020E04a8 0x00000038
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/*
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
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* DSE can be configured using Group Control Register:
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* IOMUXC_SW_PAD_CTL_GRP_CTLDS
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*/
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DATA 4 0x020E04a0 0x00000000
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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DATA 4 0x020E04b4 0x00000038
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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DATA 4 0x020E04b8 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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DATA 4 0x020E0764 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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DATA 4 0x020E0770 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
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DATA 4 0x020E0778 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
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DATA 4 0x020E077c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
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DATA 4 0x020E0780 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
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DATA 4 0x020E0784 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
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DATA 4 0x020E078c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
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DATA 4 0x020E0748 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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DATA 4 0x020E074c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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DATA 4 0x020E076c 0x00000038
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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DATA 4 0x020E0750 0x00020000
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/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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DATA 4 0x020E0754 0x00000000
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/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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DATA 4 0x020E0760 0x00020000
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/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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DATA 4 0x020E0774 0x00080000
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/*
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* DDR Controller Registers
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*
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* Manufacturer: Mocron
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* Device Part Number: MT42L64M64D2KH-18
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* Clock Freq.: 528MHz
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* MMDC channels: Both MMDC0, MMDC1
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*Density per CS in Gb: 256M
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* Chip Selects used: 2
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* Number of Banks: 8
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* Row address: 14
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* Column address: 9
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* Data bus width 32
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*/
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/* MMDC_P0_BASE_ADDR = 0x021b0000 */
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/* MMDC_P1_BASE_ADDR = 0x021b4000 */
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/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
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DATA 4 0x021b001c 0x00008000
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/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
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DATA 4 0x021b401c 0x00008000
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/*LPDDR2 ZQ params */
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DATA 4 0x021b085c 0x1b5f01ff
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DATA 4 0x021b485c 0x1b5f01ff
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/* Calibration setup. */
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/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
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DATA 4 0x021b0800 0xa1390003
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/*ca bus abs delay */
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DATA 4 0x021b0890 0x00400000
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/*ca bus abs delay */
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DATA 4 0x021b4890 0x00400000
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/* values of 20,40,50,60,7f tried. no difference seen */
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/* DDR_PHY_P1_MPWRCADL */
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DATA 4 0x021b48bc 0x00055555
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/*frc_msr.*/
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DATA 4 0x021b08b8 0x00000800
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/*frc_msr.*/
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DATA 4 0x021b48b8 0x00000800
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/* DDR_PHY_P0_MPREDQBY0DL3 */
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DATA 4 0x021b081c 0x33333333
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/* DDR_PHY_P0_MPREDQBY1DL3 */
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DATA 4 0x021b0820 0x33333333
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/* DDR_PHY_P0_MPREDQBY2DL3 */
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DATA 4 0x021b0824 0x33333333
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/* DDR_PHY_P0_MPREDQBY3DL3 */
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DATA 4 0x021b0828 0x33333333
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/* DDR_PHY_P1_MPREDQBY0DL3 */
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DATA 4 0x021b481c 0x33333333
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/* DDR_PHY_P1_MPREDQBY1DL3 */
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DATA 4 0x021b4820 0x33333333
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/* DDR_PHY_P1_MPREDQBY2DL3 */
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DATA 4 0x021b4824 0x33333333
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/* DDR_PHY_P1_MPREDQBY3DL3 */
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DATA 4 0x021b4828 0x33333333
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/*
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* Read and write data delay, per byte.
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* For optimized DDR operation it is recommended to run mmdc_calibration
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* on your board, and replace 4 delay register assigns with resulted values
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* Note:
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* a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
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* should be skipped, or the write/read calibration comming after that
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* will stall
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* b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
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*/
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DATA 4 0x021b0848 0x4b4b524f
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DATA 4 0x021b4848 0x494f4c44
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DATA 4 0x021b0850 0x3c3d303c
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DATA 4 0x021b4850 0x3c343d38
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/*dqs gating dis */
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DATA 4 0x021b083c 0x20000000
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DATA 4 0x021b0840 0x0
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||||
DATA 4 0x021b483c 0x20000000
|
||||
DATA 4 0x021b4840 0x0
|
||||
|
||||
/*clk delay */
|
||||
DATA 4 0x021b0858 0xa00
|
||||
/*clk delay */
|
||||
DATA 4 0x021b4858 0xa00
|
||||
|
||||
/*frc_msr */
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
/*frc_msr */
|
||||
DATA 4 0x021b48b8 0x00000800
|
||||
/* Calibration setup end */
|
||||
|
||||
/* Channel0 - startng address 0x80000000 */
|
||||
/* MMDC0_MDCFG0 */
|
||||
DATA 4 0x021b000c 0x34386145
|
||||
|
||||
/* MMDC0_MDPDC */
|
||||
DATA 4 0x021b0004 0x00020036
|
||||
/* MMDC0_MDCFG1 */
|
||||
DATA 4 0x021b0010 0x00100c83
|
||||
/* MMDC0_MDCFG2 */
|
||||
DATA 4 0x021b0014 0x000000Dc
|
||||
/* MMDC0_MDMISC */
|
||||
DATA 4 0x021b0018 0x0000174C
|
||||
/* MMDC0_MDRWD;*/
|
||||
DATA 4 0x021b002c 0x0f9f26d2
|
||||
/* MMDC0_MDOR */
|
||||
DATA 4 0x021b0030 0x0000020e
|
||||
/* MMDC0_MDCFG3LP */
|
||||
DATA 4 0x021b0038 0x00190778
|
||||
/* MMDC0_MDOTC */
|
||||
DATA 4 0x021b0008 0x00000000
|
||||
|
||||
/* CS0_END */
|
||||
DATA 4 0x021b0040 0x0000005f
|
||||
/* ROC */
|
||||
DATA 4 0x021b0404 0x0000000f
|
||||
|
||||
/* MMDC0_MDCTL */
|
||||
DATA 4 0x021b0000 0xc3010000
|
||||
|
||||
/* Channel1 - starting address 0x10000000 */
|
||||
/* MMDC1_MDCFG0 */
|
||||
DATA 4 0x021b400c 0x34386145
|
||||
|
||||
/* MMDC1_MDPDC */
|
||||
DATA 4 0x021b4004 0x00020036
|
||||
/* MMDC1_MDCFG1 */
|
||||
DATA 4 0x021b4010 0x00100c83
|
||||
/* MMDC1_MDCFG2 */
|
||||
DATA 4 0x021b4014 0x000000Dc
|
||||
/* MMDC1_MDMISC */
|
||||
DATA 4 0x021b4018 0x0000174C
|
||||
/* MMDC1_MDRWD;*/
|
||||
DATA 4 0x021b402c 0x0f9f26d2
|
||||
/* MMDC1_MDOR */
|
||||
DATA 4 0x021b4030 0x0000020e
|
||||
/* MMDC1_MDCFG3LP */
|
||||
DATA 4 0x021b4038 0x00190778
|
||||
/* MMDC1_MDOTC */
|
||||
DATA 4 0x021b4008 0x00000000
|
||||
|
||||
/* CS0_END */
|
||||
DATA 4 0x021b4040 0x0000003f
|
||||
|
||||
/* MMDC1_MDCTL */
|
||||
DATA 4 0x021b4000 0xc3010000
|
||||
|
||||
/* Channel0 : Configure DDR device:*/
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
|
||||
DATA 4 0x021b001c 0x003f8030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
|
||||
DATA 4 0x021b001c 0xff0a8030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
|
||||
DATA 4 0x021b001c 0xa2018030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
|
||||
DATA 4 0x021b001c 0x06028030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
|
||||
DATA 4 0x021b001c 0x01038030
|
||||
|
||||
/* Channel1 : Configure DDR device:*/
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
|
||||
DATA 4 0x021b401c 0x003f8030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
|
||||
DATA 4 0x021b401c 0xff0a8030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
|
||||
DATA 4 0x021b401c 0xa2018030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
|
||||
DATA 4 0x021b401c 0x06028030
|
||||
/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
|
||||
DATA 4 0x021b401c 0x01038030
|
||||
|
||||
/* MMDC0_MDREF */
|
||||
DATA 4 0x021b0020 0x00005800
|
||||
/* MMDC1_MDREF */
|
||||
DATA 4 0x021b4020 0x00005800
|
||||
|
||||
/* DDR_PHY_P0_MPODTCTRL */
|
||||
DATA 4 0x021b0818 0x0
|
||||
/* DDR_PHY_P1_MPODTCTRL */
|
||||
DATA 4 0x021b4818 0x0
|
||||
|
||||
/*
|
||||
* calibration values based on calibration compare of 0x00ffff00:
|
||||
* Note, these calibration values are based on Freescale's board
|
||||
* May need to run calibration on target board to fine tune these
|
||||
*/
|
||||
|
||||
/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
|
||||
DATA 4 0x021b0800 0xa1310003
|
||||
|
||||
/* DDR_PHY_P0_MPMUR0, frc_msr */
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
/* DDR_PHY_P1_MPMUR0, frc_msr */
|
||||
DATA 4 0x021b48b8 0x00000800
|
||||
|
||||
/*
|
||||
* MMDC0_MDSCR, clear this register
|
||||
* (especially the configuration bit as initialization is complete)
|
||||
*/
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
/*
|
||||
* MMDC0_MDSCR, clear this register
|
||||
* (especially the configuration bit as initialization is complete)
|
||||
*/
|
||||
DATA 4 0x021b401c 0x00000000
|
||||
|
||||
DATA 4 0x020c4068 0x00C03F3F
|
||||
DATA 4 0x020c406c 0x0030FC03
|
||||
DATA 4 0x020c4070 0x0FFFC000
|
||||
DATA 4 0x020c4074 0x3FF00000
|
||||
DATA 4 0x020c4078 0x00FFF300
|
||||
DATA 4 0x020c407c 0x0F0000C3
|
||||
DATA 4 0x020c4080 0x000003FF
|
||||
|
||||
DATA 4 0x020e0010 0xF00000CF
|
||||
DATA 4 0x020e0018 0x007F007F
|
||||
DATA 4 0x020e001c 0x007F007F
|
||||
|
||||
#else /* CONFIG_MX6DL_LPDDR2 */
|
||||
|
||||
DATA 4 0x020e0798 0x000c0000
|
||||
DATA 4 0x020e0758 0x00000000
|
||||
DATA 4 0x020e0588 0x00000030
|
||||
|
|
@ -141,3 +459,4 @@ DATA 4 0x020c4080 0x000003FF
|
|||
DATA 4 0x020e0010 0xF00000CF
|
||||
DATA 4 0x020e0018 0x007F007F
|
||||
DATA 4 0x020e001c 0x007F007F
|
||||
#endif /* CONFIG_MX6DL_LPDDR2 */
|
||||
|
|
|
|||
|
|
@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
|
||||
defined(CONFIG_DDR_32BIT)
|
||||
gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
|
||||
#else
|
||||
gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_MX6QARM2=y
|
||||
|
|
|
|||
3
configs/mx6dlarm2_lpddr2_defconfig
Normal file
3
configs/mx6dlarm2_lpddr2_defconfig
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_MX6QARM2=y
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_MX6QARM2=y
|
||||
|
|
|
|||
3
configs/mx6qarm2_lpddr2_defconfig
Normal file
3
configs/mx6qarm2_lpddr2_defconfig
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_MX6QARM2=y
|
||||
|
|
@ -168,11 +168,6 @@
|
|||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#ifdef CONFIG_DDR_32BIT
|
||||
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
|
||||
#else
|
||||
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
|
|
|
|||
Loading…
Reference in a new issue