mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Minkyu Kang
commit
6596753387
4 changed files with 289 additions and 144 deletions
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@ -113,4 +113,142 @@ typedef struct at91_matrix {
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#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
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#if defined CONFIG_AT91SAM9261
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/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
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#define AT91_MATRIX_MCFG_RCB0 (1 << 0)
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
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#define AT91_MATRIX_MCFG_RCB1 (1 << 1)
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#endif
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/* Undefined Length Burst Type */
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
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defined(CONFIG_AT91SAM9G45)
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#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
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#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
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#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
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#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
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#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
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#endif
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#if defined(CONFIG_AT91SAM9G45)
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#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
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#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
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#define AT91_MATRIX_MCFG_ULBT_128 0x00000007
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#endif
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/* Default Master Type */
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
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/* Fixed Index of Default Master */
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
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#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
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#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
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#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
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#endif
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/* Maximum Number of Allowed Cycles for a Burst */
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#if defined(CONFIG_AT91SAM9G45)
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#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
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#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
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defined(CONFIG_AT91SAM9263)
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#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
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#endif
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/* Arbitration Type */
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
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#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
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#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
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#endif
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/* Master Remap Control Register */
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
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defined(CONFIG_AT91SAM9G45)
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/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
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#define AT91_MATRIX_MRCR_RCB0 (1 << 0)
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
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#define AT91_MATRIX_MRCR_RCB1 (1 << 1)
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#endif
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#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
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#define AT91_MATRIX_MRCR_RCB2 0x00000004
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#define AT91_MATRIX_MRCR_RCB3 0x00000008
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#define AT91_MATRIX_MRCR_RCB4 0x00000010
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#define AT91_MATRIX_MRCR_RCB5 0x00000020
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#define AT91_MATRIX_MRCR_RCB6 0x00000040
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#define AT91_MATRIX_MRCR_RCB7 0x00000080
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#define AT91_MATRIX_MRCR_RCB8 0x00000100
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#endif
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#if defined(CONFIG_AT91SAM9G45)
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#define AT91_MATRIX_MRCR_RCB9 0x00000200
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#define AT91_MATRIX_MRCR_RCB10 0x00000400
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#define AT91_MATRIX_MRCR_RCB11 0x00000800
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#endif
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/* TCM Configuration Register */
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#if defined(CONFIG_AT91SAM9G45)
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/* Size of ITCM enabled memory block */
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000040
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/* Size of DTCM enabled memory block */
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
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#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
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/* Wait state TCM register */
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#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
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#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
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#endif
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#if defined(CONFIG_AT91SAM9263)
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/* Size of ITCM enabled memory block */
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
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#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
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/* Size of DTCM enabled memory block */
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
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#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
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#endif
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#if defined(CONFIG_AT91SAM9261)
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/* Size of ITCM enabled memory block */
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
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#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
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#define AT91_MATRIX_TCMR_ITCM_64 0x00000007
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/* Size of DTCM enabled memory block */
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
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#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
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#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
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#endif
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#if defined(CONFIG_AT91SAM9G45)
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/* Video Mode Configuration Register */
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#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
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#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
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/* Write Protect Mode Register */
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#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
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#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
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#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
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/* Write Protect Status Register */
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#define AT91_MATRIX_WPSR_NO_WPV 0x00000000
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#define AT91_MATRIX_WPSR_WPV 0x00000001
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#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
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#endif
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/* USB Pad Pull-Up Control Register */
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#if defined(CONFIG_AT91SAM9261)
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#define AT91_MATRIX_USBPUCR_PUON 0x40000000
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#endif
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#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
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#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
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#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
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#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */
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#endif
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@ -26,18 +26,19 @@
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#include <common.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/io.h>
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void coloured_LED_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
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1 << AT91SAM9263_ID_PIOCDE);
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writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer);
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at91_set_gpio_output(CONFIG_RED_LED, 1);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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at91_set_pio_output(CONFIG_RED_LED, 1);
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at91_set_pio_output(CONFIG_GREEN_LED, 1);
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at91_set_gpio_value(CONFIG_RED_LED, 0);
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at91_set_gpio_value(CONFIG_GREEN_LED, 1);
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at91_set_pio_value(CONFIG_RED_LED, 0);
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at91_set_pio_value(CONFIG_GREEN_LED, 1);
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}
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@ -27,13 +27,13 @@
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#include <common.h>
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#include <asm/sizes.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam9263_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#include <lcd.h>
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@ -55,52 +55,59 @@ DECLARE_GLOBAL_DATA_PTR;
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static void pm9263_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
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at91_sys_write(AT91_MATRIX_EBI0CSA,
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csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void pm9263_macb_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
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/*
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* PB27 enables the 50MHz oscillator for Ethernet PHY
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* 1 - enable
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* 0 - disable
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*/
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at91_set_gpio_output(AT91_PIN_PB27, 1);
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at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
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at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
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at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
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writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
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/*
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* Disable pull-up on:
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@ -110,19 +117,15 @@ static void pm9263_macb_hw_init(void)
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PC25),
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pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
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writel(pin_to_mask(AT91_PIN_PE25) |
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pin_to_mask(AT91_PIN_PE26),
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pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
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at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
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at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
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at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PC25),
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pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
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writel(pin_to_mask(AT91_PIN_PE25) |
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pin_to_mask(AT91_PIN_PE26),
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pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
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at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
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at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
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at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
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at91_macb_hw_init();
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}
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@ -148,17 +151,17 @@ vidinfo_t panel_info = {
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
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at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
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at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
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}
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#ifdef CONFIG_LCD_IN_PSRAM
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||||
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#define PSRAM_CRE_PIN AT91_PIN_PB29
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#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
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#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
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/* Initialize the PSRAM memory */
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@ -166,31 +169,34 @@ static int pm9263_lcd_hw_psram_init(void)
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{
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volatile uint16_t x;
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE;
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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/* Enable CS3 3.3v, no pull-ups */
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csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
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at91_sys_write(AT91_MATRIX_EBI1CSA,
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csa | AT91_MATRIX_EBI1_DBPUC |
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AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
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csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
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AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
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writel(csa, &matrix->csa[1]);
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/* Configure SMC1 CS0 for PSRAM - 16-bit */
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at91_sys_write(AT91_SMC1_SETUP(0),
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC1_PULSE(0),
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AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
|
||||
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
|
||||
at91_sys_write(AT91_SMC1_CYCLE(0),
|
||||
AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
|
||||
at91_sys_write(AT91_SMC1_MODE(0),
|
||||
AT91_SMC_DBW_16 |
|
||||
AT91_SMC_PMEN |
|
||||
AT91_SMC_PS_32);
|
||||
writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
|
||||
AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
|
||||
&smc->cs[0].setup);
|
||||
|
||||
writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
|
||||
AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
|
||||
&smc->cs[0].pulse);
|
||||
|
||||
writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
|
||||
&smc->cs[0].cycle);
|
||||
|
||||
writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
|
||||
&smc->cs[0].mode);
|
||||
|
||||
/* setup PB29 as output */
|
||||
at91_set_gpio_output(PSRAM_CRE_PIN, 1);
|
||||
at91_set_pio_output(PSRAM_CRE_PIN, 1);
|
||||
|
||||
at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
|
||||
at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
|
||||
|
||||
/* PSRAM: write BCR */
|
||||
x = readw(PSRAM_CTRL_REG);
|
||||
|
|
@ -216,7 +222,7 @@ static int pm9263_lcd_hw_psram_init(void)
|
|||
/* test if the chip is MT45W2M16B */
|
||||
if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
|
||||
/* try with CRE=1 (MT45W2M16A) */
|
||||
at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
|
||||
at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
|
||||
|
||||
/* write RCR of the PSRAM */
|
||||
x = readw(PSRAM_CTRL_REG);
|
||||
|
|
@ -229,17 +235,14 @@ static int pm9263_lcd_hw_psram_init(void)
|
|||
writew(0x1234, PHYS_PSRAM);
|
||||
writew(0x5678, PHYS_PSRAM+2);
|
||||
if ((readw(PHYS_PSRAM) != 0x1234)
|
||||
|| (readw(PHYS_PSRAM + 2) != 0x5678))
|
||||
|| (readw(PHYS_PSRAM + 2) != 0x5678))
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
/* Bus matrix */
|
||||
at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
|
||||
at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
|
||||
(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
|
||||
AT91_MATRIX_DEFMSTR_TYPE_FIXED |
|
||||
(AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
|
||||
writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
|
||||
writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -247,35 +250,37 @@ static int pm9263_lcd_hw_psram_init(void)
|
|||
|
||||
static void pm9263_lcd_hw_init(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
|
||||
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
|
||||
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
|
||||
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
|
||||
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
|
||||
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
|
||||
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
|
||||
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
|
||||
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
|
||||
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
|
||||
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
|
||||
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
|
||||
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
|
||||
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
|
||||
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
|
||||
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
|
||||
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
|
||||
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
|
||||
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
|
||||
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
|
||||
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
||||
|
||||
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
|
||||
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
|
||||
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
|
||||
|
||||
writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
|
||||
|
||||
/* Power Control */
|
||||
at91_set_gpio_output(AT91_PIN_PA22, 1);
|
||||
at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
|
||||
at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
|
||||
at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
|
||||
|
||||
#ifdef CONFIG_LCD_IN_PSRAM
|
||||
/* initialize te PSRAM */
|
||||
|
|
@ -337,13 +342,15 @@ void lcd_show_board_info(void)
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
|
||||
|
||||
/* Enable Ctrlc */
|
||||
console_init_f();
|
||||
|
||||
at91_sys_write(AT91_PMC_PCER,
|
||||
(1 << AT91SAM9263_ID_PIOA) |
|
||||
(1 << AT91SAM9263_ID_PIOCDE) |
|
||||
(1 << AT91SAM9263_ID_PIOB));
|
||||
writel((1 << AT91SAM9263_ID_PIOA) |
|
||||
(1 << AT91SAM9263_ID_PIOCDE) |
|
||||
(1 << AT91SAM9263_ID_PIOB),
|
||||
&pmc->pcer);
|
||||
|
||||
/* arch number of AT91SAM9263EK-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_PM9263;
|
||||
|
|
@ -394,7 +401,7 @@ int board_eth_init(bd_t *bis)
|
|||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_MACB
|
||||
rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
|
||||
rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_AT91_LEGACY
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
|
@ -49,41 +47,37 @@
|
|||
|
||||
/* clocks */
|
||||
#define CONFIG_SYS_MOR_VAL \
|
||||
(AT91_PMC_MOSCEN | \
|
||||
(AT91_PMC_MOR_MOSCEN | \
|
||||
(255 << 8)) /* Main Oscillator Start-up Time */
|
||||
#define CONFIG_SYS_PLLAR_VAL \
|
||||
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
|
||||
AT91_PMC_OUT | \
|
||||
AT91_PMC_PLLCOUNT | /* PLL Counter */ \
|
||||
(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
|
||||
AT91_PMC_PLLXR_OUT(3) | \
|
||||
AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
|
||||
(2 << 28) | /* PLL Clock Frequency Range */ \
|
||||
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
|
||||
|
||||
#if (MAIN_PLL_DIV == 2)
|
||||
/* PCK/2 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR1_VAL \
|
||||
(AT91_PMC_CSS_SLOW | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_2 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
(AT91_PMC_MCKR_CSS_SLOW | \
|
||||
AT91_PMC_MCKR_PRES_1 | \
|
||||
AT91_PMC_MCKR_MDIV_2)
|
||||
/* PCK/2 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR2_VAL \
|
||||
(AT91_PMC_CSS_PLLA | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_2 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
(AT91_PMC_MCKR_CSS_PLLA | \
|
||||
AT91_PMC_MCKR_PRES_1 | \
|
||||
AT91_PMC_MCKR_MDIV_2)
|
||||
#else
|
||||
/* PCK/4 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR1_VAL \
|
||||
(AT91_PMC_CSS_SLOW | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91RM9200_PMC_MDIV_3 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
(AT91_PMC_MCKR_CSS_SLOW | \
|
||||
AT91_PMC_MCKR_PRES_1 | \
|
||||
AT91_PMC_MCKR_MDIV_4)
|
||||
/* PCK/4 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR2_VAL \
|
||||
(AT91_PMC_CSS_PLLA | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91RM9200_PMC_MDIV_3 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
(AT91_PMC_MCKR_CSS_PLLA | \
|
||||
AT91_PMC_MCKR_PRES_1 | \
|
||||
AT91_PMC_MCKR_MDIV_4)
|
||||
#endif
|
||||
/* define PDC[31:16] as DATA[31:16] */
|
||||
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
|
||||
|
|
@ -91,8 +85,8 @@
|
|||
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
|
||||
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
|
||||
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
|
||||
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
|
||||
AT91_MATRIX_EBI0_CS1A_SDRAMC)
|
||||
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
|
||||
AT91_MATRIX_CSA_EBI_CS1A)
|
||||
|
||||
/* SDRAM */
|
||||
/* SDRAMC_MR Mode register */
|
||||
|
|
@ -135,32 +129,32 @@
|
|||
|
||||
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
|
||||
#define CONFIG_SYS_SMC0_SETUP0_VAL \
|
||||
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
|
||||
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
|
||||
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
|
||||
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
|
||||
#define CONFIG_SYS_SMC0_PULSE0_VAL \
|
||||
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
|
||||
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
|
||||
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
|
||||
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
|
||||
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
|
||||
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
|
||||
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
|
||||
#define CONFIG_SYS_SMC0_MODE0_VAL \
|
||||
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
|
||||
AT91_SMC_DBW_16 | \
|
||||
AT91_SMC_TDFMODE | \
|
||||
AT91_SMC_TDF_(6))
|
||||
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
|
||||
AT91_SMC_MODE_DBW_16 | \
|
||||
AT91_SMC_MODE_TDF | \
|
||||
AT91_SMC_MODE_TDF_CYCLE(6))
|
||||
|
||||
/* user reset enable */
|
||||
#define CONFIG_SYS_RSTC_RMR_VAL \
|
||||
(AT91_RSTC_KEY | \
|
||||
AT91_RSTC_PROCRST | \
|
||||
AT91_RSTC_RSTTYP_WAKEUP | \
|
||||
AT91_RSTC_RSTTYP_WATCHDOG)
|
||||
AT91_RSTC_CR_PROCRST | \
|
||||
AT91_RSTC_MR_ERSTL(1) | \
|
||||
AT91_RSTC_MR_ERSTL(2))
|
||||
|
||||
/* Disable Watchdog */
|
||||
#define CONFIG_SYS_WDTC_WDMR_VAL \
|
||||
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
|
||||
AT91_WDT_WDV | \
|
||||
AT91_WDT_WDDIS | \
|
||||
AT91_WDT_WDD)
|
||||
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
|
||||
AT91_WDT_MR_WDV(0xfff) | \
|
||||
AT91_WDT_MR_WDDIS | \
|
||||
AT91_WDT_MR_WDD(0xfff))
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
|
|
@ -196,8 +190,8 @@
|
|||
|
||||
/* LED */
|
||||
#define CONFIG_AT91_LED
|
||||
#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
|
||||
#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
|
||||
#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */
|
||||
#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
|
|
@ -258,8 +252,8 @@
|
|||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -273,6 +267,11 @@
|
|||
/* PSRAM */
|
||||
#define PHYS_PSRAM 0x70000000
|
||||
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
|
||||
/* Slave EBI1, PSRAM connected */
|
||||
#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
|
||||
AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
|
||||
AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
|
||||
AT91_MATRIX_SCFG_SLOT_CYCLE(255))
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB 1
|
||||
|
|
|
|||
Loading…
Reference in a new issue