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Merge branch '2021-09-23-assorted-updates' into next

Browse source 
- Rework lmb reservation so we have common code for all arches to use
- armv8 cache.S cleanups, crc32 speedup
- ENV_IS_NOWHWERE, pci io/memory base configuration fixes
This commit is contained in:
Tom Rini 2021-09-23 22:38:21 -04:00
commit 657668348b
37 changed files with 271 additions and 331 deletions
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30
arch/arc/lib/bootm.c
View file

@ -8,42 +8,12 @@
#include <env.h>
#include <image.h>
#include <irq_func.h>
#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp;
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
}
static int cleanup_before_linux(void)
{
disable_interrupts();

14
arch/arc/lib/cache.c
View file

@ -11,6 +11,7 @@
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <lmb.h>
#include <asm/arcregs.h>
#include <asm/arc-bcr.h>
#include <asm/cache.h>
@ -820,3 +821,16 @@ void sync_n_cleanup_cache_all(void)
__ic_entire_invalidate();
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

10
arch/arm/Kconfig
View file

@ -9,6 +9,16 @@ config ARM64
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
config ARM64_CRC32
bool "Enable support for CRC32 instruction"
depends on ARM64
default y
help
ARMv8 implements dedicated crc32 instruction for crc32 calculation.
This is faster than software crc32 calculation. This instruction may
not be present on all ARMv8.0, but is always present on ARMv8.1 and
newer.
config POSITION_INDEPENDENT
bool "Generate position-independent pre-relocation code"
depends on ARM64 || CPU_V7A

4
arch/arm/Makefile
View file

@ -18,7 +18,11 @@ arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7))
arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
ifeq ($(CONFIG_ARM64_CRC32),y)
arch-$(CONFIG_ARM64) =-march=armv8-a+crc
else
arch-$(CONFIG_ARM64) =-march=armv8-a
endif
# On Tegra systems we must build SPL for the armv4 core on the device
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH

19
arch/arm/cpu/armv8/cache.S
View file

@ -27,13 +27,11 @@ ENTRY(__asm_dcache_level)
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
clz w5, w3 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
@ -72,8 +70,7 @@ ENTRY(__asm_dcache_all)
mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
lsr x11, x10, #24
and x11, x11, #0x7 /* x11 <- loc */
ubfx x11, x10, #24, #3 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
@ -83,8 +80,7 @@ ENTRY(__asm_dcache_all)
/* x15 <- return address */
loop_level:
lsl x12, x0, #1
add x12, x12, x0 /* x0 <- tripled cache level */
add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
lsr x12, x10, x12
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
@ -131,8 +127,7 @@ ENDPROC(__asm_invalidate_dcache_all)
.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
lsr x3, x3, #16
and x3, x3, #0xf
ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */
@ -158,7 +153,7 @@ ENDPROC(__asm_flush_dcache_range)
.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
ubfm x3, x3, #16, #19
ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */

45
arch/arm/lib/bootm.c
View file

@ -16,7 +16,6 @@
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
#include <lmb.h>
#include <log.h>
#include <asm/global_data.h>
#include <dm/root.h>
@ -43,50 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp, bank_end;
int bank;
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
if (!gd->bd->bi_dram[bank].size ||
sp < gd->bd->bi_dram[bank].start)
continue;
/* Watch out for RAM at end of address space! */
bank_end = gd->bd->bi_dram[bank].start +
gd->bd->bi_dram[bank].size - 1;
if (sp > bank_end)
continue;
if (bank_end > gd->ram_top)
bank_end = gd->ram_top - 1;
lmb_reserve(lmb, sp, bank_end - sp + 1);
break;
}
}
__weak void board_quiesce_devices(void)
{
}

14
arch/arm/lib/stack.c
View file

@ -12,6 +12,7 @@
*/
#include <common.h>
#include <init.h>
#include <lmb.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@ -33,3 +34,16 @@ int arch_reserve_stacks(void)
return 0;
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 16384);
}

30
arch/arm/mach-imx/misc.c
View file

@ -77,33 +77,3 @@ int mxs_reset_block(struct mxs_register_32 *reg)
return 0;
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void board_lmb_reserve(struct lmb *lmb)
{
ulong sp, bank_end;
int bank;
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 16K to be safe */
sp -= 4096 << 2;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
if (sp < gd->bd->bi_dram[bank].start)
continue;
bank_end = gd->bd->bi_dram[bank].start +
gd->bd->bi_dram[bank].size;
if (sp >= bank_end)
continue;
lmb_reserve(lmb, sp, bank_end - sp);
break;
}
}

42
arch/arm/mach-mediatek/Kconfig
View file

@ -79,12 +79,40 @@ config TARGET_MT8518
endchoice
source "board/mediatek/mt7622/Kconfig"
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
source "board/mediatek/mt8183/Kconfig"
source "board/mediatek/mt8512/Kconfig"
source "board/mediatek/mt8516/Kconfig"
source "board/mediatek/mt8518/Kconfig"
config SYS_BOARD
string "Board name"
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
default ""
help
This option contains information about board name.
Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
be used.
config SYS_CONFIG_NAME
string "Board configuration name"
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
default ""
help
This option contains information about board configuration name.
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
default "lk=1" if TARGET_MT7623
endif

18
arch/m68k/lib/bootm.c
View file

@ -32,23 +32,7 @@ static void set_clocks_in_mhz (struct bd_info *kbd);
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp;
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug ("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 1K to be safe */
sp -= 1024;
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024);
}
int do_bootm_linux(int flag, int argc, char *const argv[],

28
arch/microblaze/lib/bootm.c
View file

@ -34,33 +34,7 @@ static ulong get_sp(void)
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp, bank_end;
int bank;
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
if (sp < gd->bd->bi_dram[bank].start)
continue;
bank_end = gd->bd->bi_dram[bank].start +
gd->bd->bi_dram[bank].size;
if (sp >= bank_end)
continue;
lmb_reserve(lmb, sp, bank_end - sp);
break;
}
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}
static void boot_jump_linux(bootm_headers_t *images, int flag)

9
arch/mips/lib/bootm.c
View file

@ -39,14 +39,7 @@ static ulong arch_get_sp(void)
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp;
sp = arch_get_sp();
debug("## Current stack ends at 0x%08lx\n", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
lmb_reserve(lmb, sp, gd->ram_top - sp);
arch_lmb_reserve_generic(lmb, arch_get_sp(), gd->ram_top, 4096);
}
static void linux_cmdline_init(void)

3
arch/mips/mach-mtmips/Kconfig
View file

@ -1,6 +1,9 @@
menu "MediaTek MIPS platforms"
depends on ARCH_MTMIPS
config SYS_VENDOR
default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
config SYS_MALLOC_F_LEN
default 0x1000

8
arch/mips/mach-mtmips/mt7620/Kconfig
View file

@ -66,6 +66,12 @@ config CPU_FREQ_MULTI
default 6 if CPU_FREQ_600MHZ
default 7 if CPU_FREQ_620MHZ
source "board/mediatek/mt7620/Kconfig"
config SYS_CONFIG_NAME
string "Board configuration name"
default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
config SYS_BOARD
string "Board name"
default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
endif

9
arch/mips/mach-mtmips/mt7628/Kconfig
View file

@ -44,8 +44,15 @@ config SPL_UART2_SPIS_PINMUX
Select this if the UART2 of your board is connected to GPIO 16/17
(shared with SPIS) rather than the usual GPIO 20/21.
config SYS_BOARD
string "Board name"
default "mt7628" if BOARD_MT7628_RFB
config SYS_CONFIG_NAME
string "Board configuration name"
default "mt7628" if BOARD_MT7628_RFB
source "board/gardena/smart-gateway-mt7688/Kconfig"
source "board/mediatek/mt7628/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
source "board/vocore/vocore2/Kconfig"

13
arch/nds32/lib/bootm.c
View file

@ -245,3 +245,16 @@ static void setup_end_tag(struct bd_info *bd)
}
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
static ulong get_sp(void)
{
ulong ret;
asm("move %0, $sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

16
arch/nios2/lib/bootm.c
View file

@ -10,6 +10,9 @@
#include <image.h>
#include <irq_func.h>
#include <log.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
@ -60,3 +63,16 @@ int do_bootm_linux(int flag, int argc, char *const argv[],
return 1;
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

18
arch/powerpc/lib/bootm.c
View file

@ -119,7 +119,7 @@ static void boot_jump_linux(bootm_headers_t *images)
void arch_lmb_reserve(struct lmb *lmb)
{
phys_size_t bootm_size;
ulong size, sp, bootmap_base;
ulong size, bootmap_base;
bootmap_base = env_get_bootm_low();
bootm_size = env_get_bootm_size();
@ -141,21 +141,7 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, base, bootm_size - size);
}
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug("## Current stack ends at 0x%08lx\n", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp));
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
#ifdef CONFIG_MP
cpu_mp_lmb_reserve(lmb);

13
arch/riscv/lib/bootm.c
View file

@ -135,3 +135,16 @@ int do_bootm_vxworks(int flag, int argc, char *const argv[],
{
return do_bootm_linux(flag, argc, argv, images);
}
static ulong get_sp(void)
{
ulong ret;
asm("mv %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

16
arch/sh/lib/bootm.c
View file

@ -12,8 +12,11 @@
#include <env.h>
#include <image.h>
#include <asm/byteorder.h>
#include <asm/global_data.h>
#include <asm/zimage.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_DEBUG
static void hexdump(unsigned char *buf, int len)
{
@ -111,3 +114,16 @@ int do_bootm_linux(int flag, int argc, char *const argv[],
/* does not return */
return 1;
}
static ulong get_sp(void)
{
ulong ret;
asm("mov r15, %0" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

18
arch/x86/lib/bootm.c
View file

@ -223,3 +223,21 @@ int do_bootm_linux(int flag, int argc, char *const argv[],
return boot_jump_linux(images);
}
static ulong get_sp(void)
{
ulong ret;
#if CONFIG_IS_ENABLED(X86_64)
ret = gd->start_addr_sp;
#else
asm("mov %%esp, %0" : "=r"(ret) : );
#endif
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

12
arch/xtensa/lib/bootm.c
View file

@ -197,3 +197,15 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
return 1;
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, a1" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

12
board/mediatek/mt7620/Kconfig
View file

@ -1,12 +0,0 @@
if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
config SYS_BOARD
default "mt7620"
config SYS_VENDOR
default "mediatek"
config SYS_CONFIG_NAME
default "mt7620"
endif

17
board/mediatek/mt7622/Kconfig
View file

@ -1,17 +0,0 @@
if TARGET_MT7622
config SYS_BOARD
default "mt7622"
config SYS_CONFIG_NAME
default "mt7622"
config MTK_BROM_HEADER_INFO
string
default "lk=1"
config MTK_BROM_HEADER_INFO
string
default "media=nor"
endif

13
board/mediatek/mt7623/Kconfig
View file

@ -1,13 +0,0 @@
if TARGET_MT7623
config SYS_BOARD
default "mt7623"
config SYS_CONFIG_NAME
default "mt7623"
config MTK_BROM_HEADER_INFO
string
default "lk=1"
endif

12
board/mediatek/mt7628/Kconfig
View file

@ -1,12 +0,0 @@
if BOARD_MT7628_RFB
config SYS_BOARD
default "mt7628"
config SYS_VENDOR
default "mediatek"
config SYS_CONFIG_NAME
default "mt7628"
endif

17
board/mediatek/mt7629/Kconfig
View file

@ -1,17 +0,0 @@
if TARGET_MT7629
config SYS_BOARD
default "mt7629"
config SYS_CONFIG_NAME
default "mt7629"
config MTK_SPL_PAD_SIZE
hex
default 0x10000
config MTK_BROM_HEADER_INFO
string
default "media=nor"
endif

13
board/mediatek/mt8183/Kconfig
View file

@ -1,13 +0,0 @@
if TARGET_MT8183
config SYS_BOARD
default "mt8183"
config SYS_CONFIG_NAME
default "mt8183"
config MTK_BROM_HEADER_INFO
string
default "media=emmc"
endif

14
board/mediatek/mt8512/Kconfig
View file

@ -1,14 +0,0 @@
if TARGET_MT8512
config SYS_BOARD
default "mt8512"
config SYS_CONFIG_NAME
default "mt8512"
config MTK_BROM_HEADER_INFO
string
default "media=nor"
endif

13
board/mediatek/mt8516/Kconfig
View file

@ -1,13 +0,0 @@
if TARGET_MT8516
config SYS_BOARD
default "mt8516"
config SYS_CONFIG_NAME
default "mt8516"
config MTK_BROM_HEADER_INFO
string
default "media=emmc"
endif

14
board/mediatek/mt8518/Kconfig
View file

@ -1,14 +0,0 @@
if TARGET_MT8518
config SYS_BOARD
default "mt8518"
config SYS_CONFIG_NAME
default "mt8518"
config MTK_BROM_HEADER_INFO
string
default "media=nor"
endif

2
common/image.c
View file

@ -216,6 +216,8 @@ static const struct comp_magic_map image_comp[] = {
{ IH_COMP_GZIP, "gzip", {0x1f, 0x8b},},
{ IH_COMP_LZMA, "lzma", {0x5d, 0x00},},
{ IH_COMP_LZO, "lzo", {0x89, 0x4c},},
{ IH_COMP_LZ4, "lz4", {0x04, 0x22},},
{ IH_COMP_ZSTD, "zstd", {0x28, 0xb5},},
{ IH_COMP_NONE, "none", {}, },
};

39
drivers/pci/pci_auto.c
View file

@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
u8 io_32;
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Configure bus number registers */
dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
* I/O space
*/
dm_pci_write_config16(dev, PCI_MEMORY_BASE,
(pci_mem->bus_lower & 0xfff00000) >> 16);
((pci_mem->bus_lower & 0xfff00000) >> 16) &
PCI_MEMORY_RANGE_MASK);
cmdstat |= PCI_COMMAND_MEMORY;
}
@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
* I/O space
*/
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff00000) >> 16);
(((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
prefechable_64);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_BASE,
(pci_io->bus_lower & 0x0000f000) >> 8);
dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
(((pci_io->bus_lower & 0x0000f000) >> 8) &
PCI_IO_RANGE_MASK) | io_32);
if (io_32 == PCI_IO_RANGE_TYPE_32)
dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_mem, 0x100000);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
(pci_mem->bus_lower - 1) >> 16);
((pci_mem->bus_lower - 1) >> 16) &
PCI_MEMORY_RANGE_MASK);
}
if (pci_prefetch) {
@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_prefetch, 0x100000);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
(pci_prefetch->bus_lower - 1) >> 16);
(((pci_prefetch->bus_lower - 1) >> 16) &
PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
}
if (pci_io) {
u8 io_32;
dm_pci_read_config8(dev, PCI_IO_LIMIT,
&io_32);
io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_LIMIT,
((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
PCI_IO_RANGE_MASK) | io_32);
if (io_32 == PCI_IO_RANGE_TYPE_32)
dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}

2
env/env.c vendored
View file

@ -336,7 +336,7 @@ int env_init(void)
debug("%s: Environment %s init done (ret=%d)\n", __func__,
drv->name, ret);
if (gd->env_valid == ENV_INVALID)
if (gd->env_valid == ENV_INVALID && drv->location != ENVL_NOWHERE)
ret = -ENOENT;
}

1
include/lmb.h
View file

@ -122,6 +122,7 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align);
/* Low level functions */

9
lib/crc32.c
View file

@ -84,7 +84,7 @@ static void __efi_runtime make_crc_table(void)
}
crc_table_empty = 0;
}
#else
#elif !defined(CONFIG_ARM64_CRC32)
/* ========================================================================
* Table of CRC-32's of all single-byte values (made by make_crc_table)
*/
@ -184,6 +184,12 @@ const uint32_t * ZEXPORT get_crc_table()
*/
uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len)
{
#ifdef CONFIG_ARM64_CRC32
crc = cpu_to_le32(crc);
while (len--)
crc = __builtin_aarch64_crc32b(crc, *buf++);
return le32_to_cpu(crc);
#else
const uint32_t *tab = crc_table;
const uint32_t *b =(const uint32_t *)buf;
size_t rem_len;
@ -221,6 +227,7 @@ uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len)
}
return le32_to_cpu(crc);
#endif
}
#undef DO_CRC

35
lib/lmb.c
View file

@ -12,6 +12,10 @@
#include <log.h>
#include <malloc.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define LMB_ALLOC_ANYWHERE 0
static void lmb_dump_region(struct lmb_region *rgn, char *name)
@ -113,6 +117,37 @@ void lmb_init(struct lmb *lmb)
lmb->reserved.cnt = 0;
}
void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align)
{
ulong bank_end;
int bank;
/*
* Reserve memory from aligned address below the bottom of U-Boot stack
* until end of U-Boot area using LMB to prevent U-Boot from overwriting
* that memory.
*/
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 4K to be safe */
sp -= align;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
if (!gd->bd->bi_dram[bank].size ||
sp < gd->bd->bi_dram[bank].start)
continue;
/* Watch out for RAM at end of address space! */
bank_end = gd->bd->bi_dram[bank].start +
gd->bd->bi_dram[bank].size - 1;
if (sp > bank_end)
continue;
if (bank_end > end)
bank_end = end - 1;
lmb_reserve(lmb, sp, bank_end - sp + 1);
break;
}
}
static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob)
{
arch_lmb_reserve(lmb);