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serial: npcm: support skip uart clock setting

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Skip the uart clock setting if CONFIG_SYS_SKIP_UART_INIT is enabled.
Fix divisor error.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu 2023-11-14 16:51:58 +08:00 committed by Tom Rini
parent 1504813eb8
commit 65660bfe85
1 changed files with 24 additions and 15 deletions
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39
drivers/serial/serial_npcm.c
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@ -83,8 +83,11 @@ static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
struct npcm_uart *uart = plat->reg; struct npcm_uart *uart = plat->reg;
u16 divisor; u16 divisor;
if (IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT))
return 0;
/* BaudOut = UART Clock / (16 * [Divisor + 2]) */ /* BaudOut = UART Clock / (16 * [Divisor + 2]) */
divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2; divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate) - 2;
setbits_8(&uart->lcr, LCR_DLAB); setbits_8(&uart->lcr, LCR_DLAB);
writeb(divisor & 0xff, &uart->dll); writeb(divisor & 0xff, &uart->dll);
@ -97,29 +100,35 @@ static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
static int npcm_serial_probe(struct udevice *dev) static int npcm_serial_probe(struct udevice *dev)
{ {
struct npcm_serial_plat *plat = dev_get_plat(dev); struct npcm_serial_plat *plat = dev_get_plat(dev);
struct npcm_uart *uart = plat->reg; struct npcm_uart *uart;
struct clk clk, parent; struct clk clk, parent;
u32 freq; u32 freq;
int ret; int ret;
plat->reg = dev_read_addr_ptr(dev); plat->reg = dev_read_addr_ptr(dev);
freq = dev_read_u32_default(dev, "clock-frequency", 0); uart = plat->reg;
ret = clk_get_by_index(dev, 0, &clk); if (!IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT)) {
if (ret < 0) freq = dev_read_u32_default(dev, "clock-frequency", 24000000);
return ret;
ret = clk_get_by_index(dev, 1, &parent); ret = clk_get_by_index(dev, 0, &clk);
if (!ret) { if (ret < 0)
ret = clk_set_parent(&clk, &parent);
if (ret)
return ret; return ret;
}
ret = clk_set_rate(&clk, freq); ret = clk_get_by_index(dev, 1, &parent);
if (ret < 0) if (!ret) {
return ret; ret = clk_set_parent(&clk, &parent);
plat->uart_clk = ret; if (ret)
return ret;
}
if (freq) {
ret = clk_set_rate(&clk, freq);
if (ret < 0)
return ret;
}
plat->uart_clk = clk_get_rate(&clk);
}
/* Disable all interrupt */ /* Disable all interrupt */
writeb(0, &uart->ier); writeb(0, &uart->ier);