Merge branch 'master' of git://git.denx.de/u-boot-microblaze

This commit is contained in:
Wolfgang Denk 2010-10-12 20:48:01 +02:00
commit 655c549752
5 changed files with 203 additions and 114 deletions

View file

@ -32,6 +32,22 @@ _start:
mts rmsr, r0 /* disable cache */
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* Find-out if u-boot is running on BIG/LITTLE endian platform
* There are some steps which is necessary to keep in mind:
* 1. Setup offset value to r6
* 2. Store word offset value to address 0x0
* 3. Load just byte from address 0x0
* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
* value that's why is on address 0x0
* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
*/
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
swi r6, r0, 0
lbui r10, r0, 0
swi r6, r0, 0x40
swi r10, r0, 0x50
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
swi r6, r0, 0x0 /* reset address */
@ -75,26 +91,52 @@ _start:
/* user_vector_exception */
addik r6, r0, _exception_handler
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0xa
shi r6, r0, 0xe
/*
* BIG ENDIAN memory map for user exception
* 0x8: 0xB000XXXX
* 0xC: 0xB808XXXX
*
* then it is necessary to count address for storing the most significant
* 16bits from _exception_handler address and copy it to
* 0xa address. Big endian use offset in r10=0 that's why is it just
* 0xa address. The same is done for the least significant 16 bits
* for 0xe address.
*
* LITTLE ENDIAN memory map for user exception
* 0x8: 0xXXXX00B0
* 0xC: 0xXXXX08B8
*
* Offset is for little endian setup to 0x2. rsubi instruction decrease
* address value to ensure that points to proper place which is
* 0x8 for the most significant 16 bits and
* 0xC for the least significant 16 bits
*/
lhu r7, r1, r10
rsubi r8, r10, 0xa
sh r7, r0, r8
rsubi r8, r10, 0xe
sh r6, r0, r8
#endif
#ifdef CONFIG_SYS_INTC_0
/* interrupt_handler */
addik r6, r0, _interrupt_handler
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0x12
shi r6, r0, 0x16
lhu r7, r1, r10
rsubi r8, r10, 0x12
sh r7, r0, r8
rsubi r8, r10, 0x16
sh r6, r0, r8
#endif
/* hardware exception */
addik r6, r0, _hw_exception_handler
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0x22
shi r6, r0, 0x26
lhu r7, r1, r10
rsubi r8, r10, 0x22
sh r7, r0, r8
rsubi r8, r10, 0x26
sh r6, r0, r8
/* enable instruction and data cache */
mfs r12, rmsr

View file

@ -50,6 +50,10 @@ static __inline__ __u16 ___arch__swab16 (__u16 half_word)
#endif /* __GNUC__ */
#ifdef __MICROBLAZEEL__
#include <linux/byteorder/little_endian.h>
#else
#include <linux/byteorder/big_endian.h>
#endif
#endif /* __MICROBLAZE_BYTEORDER_H__ */

View file

@ -31,6 +31,7 @@
#include <version.h>
#include <watchdog.h>
#include <stdio_dev.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -42,6 +43,7 @@ extern int gpio_init (void);
#ifdef CONFIG_SYS_INTC_0
extern int interrupts_init (void);
#endif
#if defined(CONFIG_CMD_NET)
extern int eth_init (bd_t * bis);
#endif
@ -165,8 +167,14 @@ void board_init (void)
#if defined(CONFIG_CMD_NET)
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
eth_init (bd);
bd->bi_ip_addr = getenv_IPaddr("ipaddr");
printf("Net: ");
eth_initialize(gd->bd);
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
printf("MAC: %pM\n", enetaddr);
#endif
/* main_loop */

View file

@ -27,6 +27,7 @@
#include <common.h>
#include <config.h>
#include <netdev.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
@ -66,3 +67,15 @@ int fsl_init2 (void) {
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
/*
* This board either has PCI NICs or uses the CPU's TSECs
* pci_eth_init() will return 0 if no NICs found, so in that case
* returning -1 will force cpu_eth_init() to be called.
*/
#ifdef CONFIG_XILINX_EMACLITE
return xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR);
#endif
}

View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2007-2008 Michal Simek
* (C) Copyright 2007-2010 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
@ -27,31 +27,33 @@
#include "../board/xilinx/microblaze-generic/xparameters.h"
#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
/* MicroBlaze CPU */
#define CONFIG_MICROBLAZE 1
#define MICROBLAZE_V5 1
/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
#define CONFIG_XILINX_UARTLITE
#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#define CONSOLE_ARG "console=console=ttyUL0,115200\0"
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
#define CONFIG_SYS_NS16550 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
#define CONFIG_BAUDRATE 115200
# define CONFIG_SYS_NS16550 1
# define CONFIG_SYS_NS16550_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE -4
# define CONFIG_CONS_INDEX 1
# define CONFIG_SYS_NS16550_COM1 \
(XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CONSOLE_ARG "console=console=ttyS0,115200\0"
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG "console=console=ttyS0,115200\0"
#else
#error Undefined uart
# error Undefined uart
#endif
/* setting reset address */
@ -59,41 +61,41 @@
/* ethernet */
#ifdef XILINX_EMACLITE_BASEADDR
#define CONFIG_XILINX_EMACLITE 1
#define CONFIG_SYS_ENET
# define CONFIG_XILINX_EMACLITE 1
# define CONFIG_SYS_ENET
#elif XILINX_LLTEMAC_BASEADDR
#define CONFIG_XILINX_LL_TEMAC 1
#define CONFIG_SYS_ENET
# define CONFIG_XILINX_LL_TEMAC 1
# define CONFIG_SYS_ENET
#endif
#undef ET_DEBUG
/* gpio */
#ifdef XILINX_GPIO_BASEADDR
#define CONFIG_SYS_GPIO_0 1
#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
# define CONFIG_SYS_GPIO_0 1
# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
#endif
/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
#define CONFIG_SYS_INTC_0 1
#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
# define CONFIG_SYS_INTC_0 1
# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
#endif
/* timer */
#ifdef XILINX_TIMER_BASEADDR
#if (XILINX_TIMER_IRQ != -1)
#define CONFIG_SYS_TIMER_0 1
#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
#endif
# if (XILINX_TIMER_IRQ != -1)
# define CONFIG_SYS_TIMER_0 1
# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
# define FREQUENCE XILINX_CLOCK_FREQ
# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
# endif
#elif XILINX_CLOCK_FREQ
#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
#else
#error BAD CLOCK FREQ
# error BAD CLOCK FREQ
#endif
/* FSL */
/* #define CONFIG_SYS_FSL_2 */
@ -135,15 +137,20 @@
/* global pointer */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size of global data */
/* start of global data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE \
- CONFIG_SYS_GBL_DATA_SIZE)
/* monitor code */
#define SIZE 0x40000
#define SIZE 0x40000
#define CONFIG_SYS_MONITOR_LEN (SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MONITOR_BASE \
(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MONITOR_END \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN SIZE
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_MALLOC_BASE \
(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
/* stack */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
@ -152,55 +159,62 @@
#define FLASH
#ifdef FLASH
#define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
#define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI 1
# define CONFIG_FLASH_CFI_DRIVER 1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO 1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS 1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT 512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
#ifdef RAMENV
#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
# ifdef RAMENV
# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#else /* !RAMENV */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#define CONFIG_ENV_SIZE 0x20000
#endif /* !RAMBOOT */
# else /* !RAMENV */
# define CONFIG_ENV_IS_IN_FLASH 1
/* 128K(one sector) for env */
# define CONFIG_ENV_SECT_SIZE 0x20000
# define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
# define CONFIG_ENV_SIZE 0x20000
# endif /* !RAMBOOT */
#else /* !FLASH */
/* ENV in RAM */
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH 1
# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
#endif /* !FLASH */
/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
#define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define SYSTEMACE_CONFIG_FPGA
#define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
#define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
#define CONFIG_DOS_PARTITION
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif
#if defined(XILINX_USE_ICACHE)
#define CONFIG_ICACHE
# define CONFIG_ICACHE
#else
#undef CONFIG_ICACHE
# undef CONFIG_ICACHE
#endif
#if defined(XILINX_USE_DCACHE)
#define CONFIG_DCACHE
# define CONFIG_DCACHE
#else
#undef CONFIG_DCACHE
# undef CONFIG_DCACHE
#endif
/*
@ -222,36 +236,39 @@
#define CONFIG_CMD_ECHO
#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
#define CONFIG_CMD_CACHE
# define CONFIG_CMD_CACHE
#else
#undef CONFIG_CMD_CACHE
# undef CONFIG_CMD_CACHE
#endif
#ifndef CONFIG_SYS_ENET
#undef CONFIG_CMD_NET
# undef CONFIG_CMD_NET
# undef CONFIG_NET_MULTI
#else
#define CONFIG_CMD_PING
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_NET_MULTI
#endif
#if defined(CONFIG_SYSTEMACE)
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif
#if defined(FLASH)
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMLS
#define CONFIG_CMD_JFFS2
# define CONFIG_CMD_ECHO
# define CONFIG_CMD_FLASH
# define CONFIG_CMD_IMLS
# define CONFIG_CMD_JFFS2
#if !defined(RAMENV)
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SAVES
#endif
# if !defined(RAMENV)
# define CONFIG_CMD_SAVEENV
# define CONFIG_CMD_SAVES
# endif
#else
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_IMLS
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_JFFS2
#endif
#if defined(CONFIG_CMD_JFFS2)
@ -259,21 +276,26 @@
#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ml401-0"
#define MTDIDS_DEFAULT "nor0=flash-0"
/* default mtd partition table */
#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
"256k(env),3m(kernel),1m(romfs),"\
"1m(cramfs),-(jffs2)"
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
/* size of console buffer */
#define CONFIG_SYS_CBSIZE 512
/* print buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 15
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */
/* default load address */
#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTARGS "root=romfs"
@ -290,9 +312,9 @@
#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
"nor0=ml401-0\0"\
"mtdparts=mtdparts=ml401-0:"\
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
"nor0=flash-0\0"\
"mtdparts=mtdparts=flash-0:"\
"256k(u-boot),256k(env),3m(kernel),"\
"1m(romfs),1m(cramfs),-(jffs2)\0"
@ -301,7 +323,7 @@
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
# define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#endif /* __CONFIG_H */