mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
ARM: am3517_evm: Remove hard-coded pin muxing
With updated device trees now supporting pinmuxing for USB, ethernet, MMC, and other peripherals necessary to start MLO and U-Boot, the hard-coded pinmux options can be removed since they are now handed by DM and only muxed when the respective peripheral needs it. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
This commit is contained in:
Adam Ford
Tom Rini
parent
72ce7818f9
commit
6553f154f2
1 changed files with 0 additions and 198 deletions
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@ -122,64 +122,7 @@ const omap3_sysinfo sysinfo = {
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
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/* - ETH_nRESET*/\
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
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/* DSS */\
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
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/* CAMERA */\
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MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
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/* - CAM_RESET*/\
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MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
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MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
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/* MMC */\
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MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
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@ -187,144 +130,15 @@ const omap3_sysinfo sysinfo = {
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
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/* WriteProtect */\
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MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\
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MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
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\
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MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
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/* McBSP */\
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MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
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MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
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\
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MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
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\
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MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
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\
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MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
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/* - LCD_INI*/\
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MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
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/* - LCD_ENVDD */\
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MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
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/* - LCD_QVGA/nVGA */\
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MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
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/* - LCD_RESB */\
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/* UART */\
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MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
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\
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MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
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\
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
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/* I2C */\
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MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
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/* McSPI */\
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MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
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MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
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/* - LAN_INTR*/\
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MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
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\
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MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
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MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
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/* CCDC */\
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MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
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MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
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MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
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/* RMII */\
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MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
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MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
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MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
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MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
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MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
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MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
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MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
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MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
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MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
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MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
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/* HECC */\
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MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
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/* HSUSB */\
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
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/* HDQ */\
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MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
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/* Control and debug */\
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MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
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/*SYS_nRESWARM */\
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MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
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/* - GPIO30 */\
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MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
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/* - PEN_IRQ */\
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MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
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MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
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MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
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MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
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MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
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MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
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/* - VIO_1V8*/\
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MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
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\
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@ -339,18 +153,6 @@ const omap3_sysinfo sysinfo = {
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MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
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/* ETK (ES2 onwards) */\
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MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
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MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
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MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
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MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
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MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
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MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
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MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
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MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
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MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
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MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
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MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
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MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
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MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
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