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ppc4xx: Correct 405EX PCIe UTL register mapping
Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
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parent
9ea61b5796
commit
653811a3c2
1 changed files with 3 additions and 3 deletions
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@ -412,14 +412,14 @@ static void ppc4xx_setup_utl(u32 port)
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case 0:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */
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mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
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break;
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case 1:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */
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mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
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break;
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@ -554,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
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#endif /* CONFIG_405EX */
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int ppc4xx_init_pcie_port_hw(int port, int rootport)
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__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
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__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
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/*
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* We map PCI Express configuration access into the 512MB regions
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