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board: rockchip: Add Pine64 SOQuartz on Model A

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The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz
CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI,
CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.

Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host

Device tree is imported from linux v6.4.

Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman 2023-07-30 12:26:45 +00:00 committed by Kever Yang
parent f52452bbea
commit 651492bfb2
8 changed files with 1046 additions and 0 deletions
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1
arch/arm/dts/Makefile
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@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-quartz64-a.dtb \
rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \

3
arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3566-soquartz-u-boot.dtsi"

232
arch/arm/dts/rk3566-soquartz-model-a.dts Normal file
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@ -0,0 +1,232 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-soquartz.dtsi"
/ {
model = "PINE64 RK3566 SOQuartz on Model A carrier board";
compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
/* labeled DCIN_12V in schematic */
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
/*
* Labelled VCC3V0_SD in schematic to not conflict with PMIC
* regulator, it's 3.3v in actuality
*/
vcc3v0_sd: vcc3v0-sd-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v0_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_dcin>;
};
vcc12v_pcie: vcc12v-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc12v_dcin>;
};
};
/* phy for pcie */
&combphy2 {
phy-supply = <&vcc3v3_sys>;
status = "okay";
};
&gmac1 {
status = "okay";
};
/*
* i2c1 is exposed on CM1 / Module1A
* pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
* pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
*/
&i2c1 {
status = "okay";
/*
* the rtc interrupt is tied to PMIC_PWRON,
* it will force reset the board if triggered.
*/
pcf85063: rtc@51 {
compatible = "nxp,pcf85063";
reg = <0x51>;
};
};
/*
* i2c2 is exposed on CM1 / Module1A - to PI40
* pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
* pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
*/
&i2c2 {
status = "disabled";
};
/*
* i2c3 is exposed on CM1 / Module1A - to PI40
* pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
* pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
*/
&i2c3 {
status = "disabled";
};
/*
* i2c4 is exposed on CM2 / Module1B - to PI40
* pin 45 - GPIO24 - i2c4_scl_m1
* pin 47 - GPIO23 - i2c4_sda_m1
*/
&i2c4 {
status = "disabled";
};
/*
* i2s1_8ch is exposed on CM1 / Module1A - to PI40
* pin 24 - GPIO26 - i2s1_sdi1_m1
* pin 25 - GPIO21 - i2s1_sdo0_m1
* pin 26 - GPIO19 - i2s1_lrck_tx_m1
* pin 27 - GPIO20 - i2s1_sdi0_m1
* pin 29 - GPIO16 - i2s1_sdi3_m1
* pin 30 - GPIO6 - i2s1_sdi2_m1
* pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
* pin 41 - GPIO25 - i2s1_sdo2_m1
* pin 49 - GPIO18 - i2s1_sclk_tx_m1
* pin 50 - GPIO17 - i2s1_mclk_m1
* pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
*/
&i2s1_8ch {
status = "disabled";
};
&led_diy {
status = "okay";
};
&led_work {
status = "okay";
};
&pcie2x1 {
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&rgmii_phy1 {
status = "okay";
};
&rgmii_phy1 {
status = "okay";
};
/*
* saradc is exposed on CM1 / Module1A - to J2
* pin 94 - AIN1 - saradc_vin3
* pin 96 - AIN0 - saradc_vin2
*/
&saradc {
status = "disabled";
};
/*
* vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
* the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
* so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
*/
&sdmmc0 {
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
/*
* spi3 is exposed on CM1 / Module1A - to PI40
* pin 37 - GPIO7 - spi3_cs1_m0
* pin 38 - GPIO11 - spi3_clk_m0
* pin 39 - GPIO8 - spi3_cs0_m0
* pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
* pin 44 - GPIO10 - spi3_mosi_m0
*/
&spi3 {
status = "disabled";
};
/*
* uart2 is exposed on CM1 / Module1A - to PI40
* pin 51 - GPIO15 - uart2_rx_m0
* pin 55 - GPIO14 - uart2_tx_m0
*/
&uart2 {
status = "okay";
};
/*
* uart7 is exposed on CM1 / Module1A - to PI40
* pin 46 - GPIO22 - uart7_tx_m2
* pin 47 - GPIO23 - uart7_rx_m2
*/
&uart7 {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb>;
status = "okay";
};
&usb_host0_xhci {
status = "okay";
};
&vbus {
vin-supply = <&vcc5v0_usb>;
};
&vcc3v3_sd {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
status = "okay";
};

26
arch/arm/dts/rk3566-soquartz-u-boot.dtsi Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
};
&uart2 {
bootph-all;
clock-frequency = <24000000>;
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
};

688
arch/arm/dts/rk3566-soquartz.dtsi Normal file
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@ -0,0 +1,688 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
model = "Pine64 RK3566 SoQuartz SOM";
compatible = "pine64,soquartz", "rockchip,rk3566";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
mmc2 = &sdmmc1;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
led_diy: led-diy {
label = "diy-led";
default-state = "on";
gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&diy_led_enable_h>;
retain-state-suspended;
status = "disabled";
};
led_work: led-work {
label = "work-led";
default-state = "off";
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&work_led_enable_h>;
retain-state-suspended;
status = "disabled";
};
};
sdio_pwrseq: sdio-pwrseq {
status = "okay";
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
};
vbus: vbus-regulator {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
/* sourced from vbus, vbus is provided by the carrier board */
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vbus>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_3v3>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2
&gmac1m0_rx_bus2
&gmac1m0_rgmii_clk
&gmac1m0_clkinout
&gmac1m0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
phy-handle = <&rgmii_phy1>;
status = "disabled";
};
&gpio0 {
nextrst-hog {
gpio-hog;
/*
* GPIO_ACTIVE_LOW + output-low here means that the pin is set
* to high, because output-low decides the value pre-inversion.
*/
gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
line-name = "nEXTRST";
output-low;
};
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdda0v9_image: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_image: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
status = "disabled";
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};
};
/*
* i2c1 is exposed on CM1 / Module1A
* pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
* pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
*/
&i2c1 {
status = "disabled";
};
/*
* i2c2 is exposed on CM1 / Module1A
* pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
* pin 58 - i2c2_sda_m1, pullup to vcc_3v3
*/
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2m1_xfer>;
status = "disabled";
};
/*
* i2c3 is exposed on CM1 / Module1A
* pin 35 - i2c3_scl_m0, pullup to vcc_3v3
* pin 36 - i2c3_sda_m0, pullup to vcc_3v3
*/
&i2c3 {
status = "disabled";
};
/*
* i2c4 is exposed on CM2 / Module1B
* pin 45 - i2c4_scl_m1
* pin 47 - i2c4_sda_m1
*/
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4m1_xfer>;
status = "disabled";
};
&i2s0_8ch {
status = "okay";
};
/*
* i2s1_8ch is exposed on CM1 / Module1A
* pin 24 - i2s1_sdi1_m1
* pin 25 - i2s1_sdo0_m1
* pin 26 - i2s1_lrck_tx_m1
* pin 27 - i2s1_sdi0_m1
* pin 29 - i2s1_sdi3_m1
* pin 30 - i2s1_sdi2_m1
* pin 40 - i2s1_sdo1_m1, shared with spi3
* pin 41 - i2s1_sdo2_m1
* pin 49 - i2s1_sclk_tx_m1
* pin 50 - i2s1_mclk_m1
* pin 56 - i2s1_sdo3_m1, shared with i2c2
*/
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
&i2s1m1_lrcktx &i2s1m1_lrckrx
&i2s1m1_sdi0 &i2s1m1_sdi1
&i2s1m1_sdi2 &i2s1m1_sdi3
&i2s1m1_sdo0 &i2s1m1_sdo1
&i2s1m1_sdo2 &i2s1m1_sdo3>;
status = "disabled";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
status = "disabled";
};
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_h>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
work_led_enable_h: work-led-enable-h {
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_enable_h: diy-led-enable-h {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_clkreq_h: pcie-clkreq-h {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_reset_h: pcie-reset-h {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
/*
* saradc is exposed on CM1 / Module1A
* pin 94 - saradc_vin3
* pin 96 - saradc_vin2
*/
&saradc {
vref-supply = <&vcca_1v8>;
status = "disabled";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
vqmmc-supply = <&vccio_sd>;
status = "disabled";
};
&sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
sd-uhs-sdr50;
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
/*
* spi3 is exposed on CM1 / Module1A
* pin 37 - spi3_cs1_m0
* pin 38 - spi3_clk_m0
* pin 39 - spi3_cs0_m0
* pin 40 - spi3_miso_m0, shared with i2s1_8ch
* pin 44 - spi3_mosi_m0
*/
&spi3 {
status = "disabled";
};
&tsadc {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca1v8_pmu>;
};
};
/*
* uart2 is exposed on CM1 / Module1A
* pin 51 - uart2_rx_m0
* pin 55 - uart2_tx_m0
*/
&uart2 {
status = "disabled";
};
/*
* uart7 is exposed on CM1 / Module1A
* pin 46 - uart7_tx_m2
* pin 47 - uart7_rx_m2
*/
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&uart7m2_xfer>;
status = "disabled";
};
/* dwc3_otg is the only usb port available */
&usb2phy0 {
status = "disabled";
};
&usb2phy0_otg {
status = "disabled";
};
&usb_host0_xhci {
status = "disabled";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

5
board/pine64/quartz64_rk3566/MAINTAINERS
View file

@ -6,7 +6,12 @@ F: board/pine64/quartz64_rk3566/
F: include/configs/quartz64_rk3566.h
F: configs/quartz64-a-rk3566_defconfig
F: configs/quartz64-b-rk3566_defconfig
F: configs/soquartz-model-a-rk3566_defconfig
F: arch/arm/dts/rk3566-quartz64-a.dts
F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
F: arch/arm/dts/rk3566-quartz64-b.dts
F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
F: arch/arm/dts/rk3566-soquartz.dtsi
F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi
F: arch/arm/dts/rk3566-soquartz-model-a.dts
F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi

90
configs/soquartz-model-a-rk3566_defconfig Normal file
View file

@ -0,0 +1,90 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZ64_RK3566=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

1
doc/board/rockchip/rockchip.rst
View file

@ -98,6 +98,7 @@ List of mainline supported Rockchip boards:
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
- Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
- Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
* rk3588
- Rockchip EVB (evb-rk3588)