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Merge branch 'denx'

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This commit is contained in:
Andy Fleming 2008-09-09 16:16:20 -05:00 committed by Andrew Fleming-AFLEMING
commit 650a9e7abc
105 changed files with 3238 additions and 996 deletions
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3
CREDITS
View file

@ -405,7 +405,8 @@ D: Atmel AT91CAP9ADK support
N: Ricardo Ribalda Delgado
E: ricardo.ribalda@uam.es
D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
D: Virtex ppc440 generic architecture
W: http://www.ii.uam.es/~rribalda
N: Stefan Roese

2
MAINTAINERS
View file

@ -314,6 +314,8 @@ Daniel Poirot <dan.poirot@windriver.com>
Ricardo Ribalda <ricardo.ribalda@uam.es>
ml507 PPC440x5
v5fx30teval PPC440x5
xilinx-pp440-generic PPC440x5
Stefan Roese <sr@denx.de>

4
MAKEALL
View file

@ -230,12 +230,16 @@ LIST_4xx=" \
sequoia_nand \
taihu \
taishan \
v5fx30teval \
v5fx30teval_flash \
VOH405 \
VOM405 \
W7OLMC \
W7OLMG \
walnut \
WUH405 \
xilinx-ppc440-generic \
xilinx-ppc440-generic_flash \
XPEDITE1K \
yellowstone \
yosemite \

66
Makefile
View file

@ -295,7 +295,7 @@ $(obj)u-boot.hex: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
$(obj)u-boot.srec: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
$(OBJCOPY) -O srec $< $@
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
@ -1242,12 +1242,15 @@ CMS700_config: unconfig
CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
CPCI405_config \
CPCI4052_config \
CPCI405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
CPCI4052_config \
CPCI405DT_config \
CPCI405AB_config: unconfig
@mkdir -p $(obj)board/esd/cpci405
@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
@echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
CPCIISER4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
@ -1356,16 +1359,23 @@ ML2_config: unconfig
ml300_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
ml507_flash_config: unconfig
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp $(obj)board/xilinx/ml507/u-boot-rom.lds $(obj)board/xilinx/ml507/u-boot.lds
@echo "TEXT_BASE = 0xFE360000" > $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
> $(obj)board/xilinx/ml507/config.tmp
@echo "TEXT_BASE := 0xFE360000" \
>> $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
ml507_config: unconfig
ml507_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp $(obj)board/xilinx/ml507/u-boot-ram.lds $(obj)board/xilinx/ml507/u-boot.lds
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
> $(obj)board/xilinx/ml507/config.tmp
@echo "TEXT_BASE := 0x04000000" \
>> $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
ocotea_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
@ -1461,6 +1471,24 @@ taihu_config: unconfig
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
v5fx30teval_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
> $(obj)board/avnet/v5fx30teval/config.tmp
@echo "TEXT_BASE := 0x03000000" \
>> $(obj)board/avnet/v5fx30teval/config.tmp
@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
v5fx30teval_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
> $(obj)/board/avnet/v5fx30teval/config.tmp
@echo "TEXT_BASE := 0xFF1C0000" \
>> $(obj)/board/avnet/v5fx30teval/config.tmp
@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
VOH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
@ -1479,6 +1507,22 @@ sycamore_config: unconfig
WUH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
xilinx-ppc440-generic_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
> $(obj)board/xilinx/ppc440-generic/config.tmp
@echo "TEXT_BASE := 0xFE360000" \
>> $(obj)board/xilinx/ppc440-generic/config.tmp
@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
xilinx-ppc440-generic_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
> $(obj)board/xilinx/ppc440-generic/config.tmp
@echo "TEXT_BASE := 0x04000000" \
>> $(obj)board/xilinx/ppc440-generic/config.tmp
@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
XPEDITE1K_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k

15
README
View file

@ -380,11 +380,11 @@ The following options need to be configured:
param header, the default value is zero if undefined.
- Serial Ports:
CFG_PL010_SERIAL
CONFIG_PL010_SERIAL
Define this if you want support for Amba PrimeCell PL010 UARTs.
CFG_PL011_SERIAL
CONFIG_PL011_SERIAL
Define this if you want support for Amba PrimeCell PL011 UARTs.
@ -3030,8 +3030,9 @@ details; basically, the header defines the following image properties:
* Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
LynxOS, pSOS, QNX, RTEMS, ARTOS;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
INTEGRITY).
* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
@ -3089,9 +3090,9 @@ But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
Just make sure your machine specific header file (for instance
include/asm-ppc/tqm8xx.h) includes the same definition of the Board
Information structure as we define in include/u-boot.h, and make
sure that your definition of IMAP_ADDR uses the same value as your
U-Boot configuration in CFG_IMMR.
Information structure as we define in include/asm-<arch>/u-boot.h,
and make sure that your definition of IMAP_ADDR uses the same value
as your U-Boot configuration in CFG_IMMR.
Configuring the Linux kernel:

1
board/atc/atc.c
View file

@ -380,7 +380,6 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

27
board/avnet/v5fx30teval/Makefile Normal file
View file

@ -0,0 +1,27 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
COBJS += $(BOARD).o
include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile

26
board/avnet/v5fx30teval/config.mk Normal file
View file

@ -0,0 +1,26 @@
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Work supported by Qtechnology http://www.qtec.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk

28
board/avnet/v5fx30teval/v5fx30teval.c Normal file
View file

@ -0,0 +1,28 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Avnet Virtex 5 FX30 Evaluation Board\n");
return 0;
}

33
board/avnet/v5fx30teval/xparameters.h Normal file
View file

@ -0,0 +1,33 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters.h by Xilinx
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

1
board/cpu86/cpu86.c
View file

@ -313,7 +313,6 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

1
board/cpu87/cpu87.c
View file

@ -323,7 +323,6 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

16
board/esd/cpci405/config.mk
View file

@ -21,20 +21,8 @@
# MA 02111-1307 USA
#
#
# esd CPCI405 boards
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifeq ($(BOARD_REVISION),CPCI4052)
TEXT_BASE = 0xFFFC0000
else
ifeq ($(BOARD_REVISION),CPCI405DT)
TEXT_BASE = 0xFFFC0000
else
ifeq ($(BOARD_REVISION),CPCI405AB)
TEXT_BASE = 0xFFFC0000
else
ifndef TEXT_BASE
TEXT_BASE = 0xFFFD0000
endif
endif
endif

15
board/esd/cpci405/u-boot.lds
View file

@ -57,22 +57,7 @@ SECTIONS
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)

2
board/gen860t/gen860t.c
View file

@ -223,8 +223,6 @@ phys_size_t initdram (int board_type)
* The DOC lives in the CS2* space
*/
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
printf ("Probing at 0x%.8x: ", DOC_BASE);

7
board/integratorcp/integratorcp.c
View file

@ -34,6 +34,7 @@
*/
#include <common.h>
#include <div64.h>
DECLARE_GLOBAL_DATA_PTR;
@ -244,7 +245,11 @@ ulong get_timer_masked (void)
total_count += lastdec - now;
}
lastdec = now;
timestamp = (ulong)(total_count/div_timer);
/* Reuse "now" */
now = total_count;
do_div(now, div_timer);
timestamp = now;
return timestamp;
}

1
board/mcc200/mcc200.c
View file

@ -323,7 +323,6 @@ void ide_set_reset (int idereset)
#endif
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

1
board/mpl/common/common_util.c
View file

@ -565,7 +565,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#if defined(CONFIG_CMD_DOC)
extern void doc_probe(ulong physadr);
void doc_init (void)
{
doc_probe(MULTI_PURPOSE_SOCKET_ADDR);

2
board/netstal/hcu5/sdram.c
View file

@ -122,7 +122,7 @@ void sdram_panic(const char *reason)
}
#ifdef CONFIG_DDR_ECC
static void blank_string(int size)
void blank_string(int size)
{
int i;

14
board/netta2/netta2.c
View file

@ -620,20 +620,6 @@ void hw_watchdog_reset(void)
#endif
#ifdef CONFIG_SHOW_ACTIVITY
/* called from timer interrupt every 1/CFG_HZ sec */
void board_show_activity(ulong timestamp)
{
}
/* called when looping */
void show_activity(int arg)
{
}
#endif
#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{

1
board/pm520/pm520.c
View file

@ -316,7 +316,6 @@ void ide_set_reset (int idereset)
#endif
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

1
board/pm826/pm826.c
View file

@ -312,7 +312,6 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

1
board/pm828/pm828.c
View file

@ -345,7 +345,6 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

10
board/sc520_cdp/sc520_cdp.c
View file

@ -114,7 +114,7 @@ static void irq_init(void)
}
#ifdef CONFIG_PCI
/* PCI stuff */
static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
@ -129,7 +129,7 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
};
static int next_irq_index=0;
char tmp_pin;
uchar tmp_pin;
int pin;
pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
@ -193,7 +193,7 @@ void pci_init_board(void)
{
pci_sc520_init(&sc520_cdp_hose);
}
#endif
static void silence_uart(int port)
{
@ -563,12 +563,12 @@ void spi_eeprom_probe(int x)
{
}
int spi_eeprom_read(int x, int offset, char *buffer, int len)
int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
{
return 0;
}
int spi_eeprom_write(int x, int offset, char *buffer, int len)
int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
{
return 0;
}

14
board/stxxtc/stxxtc.c
View file

@ -599,20 +599,6 @@ void hw_watchdog_reset(void)
#endif
#ifdef CONFIG_SHOW_ACTIVITY
/* called from timer interrupt every 1/CFG_HZ sec */
void board_show_activity(ulong timestamp)
{
}
/* called when looping */
void show_activity(int arg)
{
}
#endif
#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{

1
board/svm_sc8xx/svm_sc8xx.c
View file

@ -154,7 +154,6 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);

10
board/trab/tsc2000.c
View file

@ -27,6 +27,7 @@
#include <common.h>
#include <s3c2400.h>
#include <div64.h>
#include "tsc2000.h"
#include "Pt1000_temp_data.h"
@ -332,6 +333,7 @@ void tsc2000_reg_init (void)
int tsc2000_interpolate(long value, long data[][2], long *result)
{
int i;
unsigned long long val;
/* the data is sorted and the first element is upper
* limit so we can easily check for out-of-band values
@ -347,10 +349,10 @@ int tsc2000_interpolate(long value, long data[][2], long *result)
result in 'long long'.
*/
*result = data[i-1][1] +
((unsigned long long)(data[i][1] - data[i-1][1])
* (unsigned long long)(value - data[i-1][0]))
/ (data[i][0] - data[i-1][0]);
val = ((unsigned long long)(data[i][1] - data[i-1][1])
* (unsigned long long)(value - data[i-1][0]));
do_div(val, (data[i][0] - data[i-1][0]));
*result = data[i-1][1] + val;
return 0;
}

41
board/xilinx/ml507/Makefile
View file

@ -1,6 +1,7 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# See file CREDITS for list of people who contributed to this
# project.
@ -21,38 +22,6 @@
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
endif
COBJS += $(BOARD).o
INCS :=
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile

11
board/xilinx/ml507/config.mk
View file

@ -1,6 +1,7 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Work supported by Qtechnology http://www.qtec.com
#
# See file CREDITS for list of people who contributed to this
# project.
@ -20,8 +21,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
#
ifndef TEXT_BASE
TEXT_BASE = 0x04000000
endif
sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk

53
board/xilinx/ml507/init.S
View file

@ -1,53 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/* SDRAM */
tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R | AC_W | AC_X | SA_G | SA_I)
/* UART */
tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
/* PIC */
tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#ifdef XPAR_IIC_EEPROM_BASEADDR
/* I2C */
tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_LLTEMAC_0_BASEADDR
/* Net */
tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_FLASH_MEM0_BASEADDR
/*Flash*/
tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0,
AC_R | AC_W | AC_X | SA_G | SA_I)
#endif
tlbtab_end

21
board/xilinx/ml507/ml507.c
View file

@ -20,28 +20,9 @@
#include <common.h>
#include <asm/processor.h>
int board_pre_init(void)
{
return 0;
}
int checkboard(void)
{
puts("ML507 Board\n");
puts("Xilinx ML507 Board\n");
return 0;
}
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CFG_SDRAM_SIZE_MB * 1024 * 1024);
}
void get_sys_info(sys_info_t * sysInfo)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
return;
}

17
board/xilinx/ml507/xparameters.h
View file

@ -21,15 +21,14 @@
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_LLTEMAC_0_BASEADDR 0x81C00000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

62
board/xilinx/ppc440-generic/Makefile Normal file
View file

@ -0,0 +1,62 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Work supported by Qtechnology http://www.qtec.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
endif
INCS :=
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
SOBJS += ../../xilinx/ppc440-generic/init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

25
board/xilinx/ppc440-generic/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Work supported by Qtechnology http://www.qtec.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(obj)/board/$(BOARDDIR)/config.tmp

45
board/xilinx/ppc440-generic/init.S Normal file
View file

@ -0,0 +1,45 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
tlbtab_end

0
board/xilinx/ml507/u-boot-ram.lds → board/xilinx/ppc440-generic/u-boot-ram.lds
View file

0
board/xilinx/ml507/u-boot-rom.lds → board/xilinx/ppc440-generic/u-boot-rom.lds
View file

52
board/xilinx/ppc440-generic/xilinx_ppc440_generic.c Normal file
View file

@ -0,0 +1,52 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int __board_pre_init(void)
{
return 0;
}
int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
int __checkboard(void)
{
puts("Xilinx PPC440 Generic Board\n");
return 0;
}
int checkboard(void) __attribute__((weak, alias("__checkboard")));
phys_size_t __initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CFG_SDRAM_SIZE_MB * 1024 * 1024);
}
phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
void __get_sys_info(sys_info_t *sysInfo)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));

34
board/xilinx/ppc440-generic/xparameters.h Normal file
View file

@ -0,0 +1,34 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

9
common/Makefile
View file

@ -56,7 +56,8 @@ COBJS-y += env_nowhere.o
# command
COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
COBJS-$(CONFIG_AUTOSCRIPT)$(CONFIG_CMD_AUTOSCRIPT) += cmd_autoscript.o
COBJS-$(CONFIG_AUTOSCRIPT) += cmd_autoscript.o
COBJS-$(CONFIG_CMD_AUTOSCRIPT) += cmd_autoscript.o
COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
@ -110,7 +111,8 @@ COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
COBJS-y += cmd_mac.o
COBJS-y += cmd_mem.o
COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
COBJS-$(CONFIG_MII)$(CONFIG_CMD_MII) += miiphyutil.o
COBJS-$(CONFIG_MII) += miiphyutil.o
COBJS-$(CONFIG_CMD_MII) += miiphyutil.o
COBJS-$(CONFIG_CMD_MII) += cmd_mii.o
COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o
COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
@ -151,8 +153,7 @@ COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
COBJS-y += $(COBJS-yy)
COBJS := $(COBJS-y)
COBJS := $(sort $(COBJS-y))
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))

109
common/cmd_bootm.c
View file

@ -108,8 +108,8 @@ static boot_os_fn do_bootm_qnxelf;
int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif
#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC)
static boot_os_fn do_bootm_artos;
#if defined(CONFIG_INTEGRITY)
static boot_os_fn do_bootm_integrity;
#endif
ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */
@ -337,13 +337,13 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress)
return BOOTM_ERR_UNIMPLEMENTED;
}
puts ("OK\n");
debug (" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, load_end);
debug (" kernel loaded at 0x%08lx, end = 0x%8p\n", load, load_end);
if (boot_progress)
show_boot_progress (7);
if ((load < blob_end) && (*load_end > blob_start)) {
debug ("images.os.start = 0x%lX, images.os.end = 0x%lx\n", blob_start, blob_end);
debug ("images.os.load = 0x%lx, load_end = 0x%lx\n", load, load_end);
debug ("images.os.load = 0x%lx, load_end = 0x%p\n", load, load_end);
return BOOTM_ERR_OVERLAP;
}
@ -455,9 +455,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
break;
#endif
#ifdef CONFIG_ARTOS
case IH_OS_ARTOS:
do_bootm_artos (0, argc, argv, &images);
#ifdef CONFIG_INTEGRITY
case IH_OS_INTEGRITY:
do_bootm_integrity (0, argc, argv, &images);
break;
#endif
}
@ -854,6 +854,12 @@ static int image_info (ulong addr)
}
fit_print_contents (hdr);
if (!fit_all_image_check_hashes (hdr)) {
puts ("Bad hash in FIT image!\n");
return 1;
}
return 0;
#endif
default:
@ -1153,92 +1159,31 @@ static int do_bootm_qnxelf(int flag, int argc, char *argv[],
}
#endif
#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC)
static int do_bootm_artos (int flag, int argc, char *argv[],
#ifdef CONFIG_INTEGRITY
static int do_bootm_integrity (int flag, int argc, char *argv[],
bootm_headers_t *images)
{
ulong top;
char *s, *cmdline;
char **fwenv, **ss;
int i, j, nxt, len, envno, envsz;
bd_t *kbd;
void (*entry)(bd_t *bd, char *cmdline, char **fwenv, ulong top);
void (*entry_point)(void);
#if defined(CONFIG_FIT)
if (!images->legacy_hdr_valid) {
fit_unsupported_reset ("ARTOS");
fit_unsupported_reset ("INTEGRITY");
return 1;
}
#endif
entry_point = (void (*)(void))images->ep;
printf ("## Transferring control to INTEGRITY (at address %08lx) ...\n",
(ulong)entry_point);
show_boot_progress (15);
/*
* Booting an ARTOS kernel image + application
* INTEGRITY Parameters:
* None
*/
/* this used to be the top of memory, but was wrong... */
#ifdef CONFIG_PPC
/* get stack pointer */
asm volatile ("mr %0,1" : "=r"(top) );
#endif
debug ("## Current stack ends at 0x%08lX ", top);
top -= 2048; /* just to be sure */
if (top > CFG_BOOTMAPSZ)
top = CFG_BOOTMAPSZ;
top &= ~0xF;
debug ("=> set upper limit to 0x%08lX\n", top);
/* first check the artos specific boot args, then the linux args*/
if ((s = getenv( "abootargs")) == NULL && (s = getenv ("bootargs")) == NULL)
s = "";
/* get length of cmdline, and place it */
len = strlen (s);
top = (top - (len + 1)) & ~0xF;
cmdline = (char *)top;
debug ("## cmdline at 0x%08lX ", top);
strcpy (cmdline, s);
/* copy bdinfo */
top = (top - sizeof (bd_t)) & ~0xF;
debug ("## bd at 0x%08lX ", top);
kbd = (bd_t *)top;
memcpy (kbd, gd->bd, sizeof (bd_t));
/* first find number of env entries, and their size */
envno = 0;
envsz = 0;
for (i = 0; env_get_char (i) != '\0'; i = nxt + 1) {
for (nxt = i; env_get_char (nxt) != '\0'; ++nxt)
;
envno++;
envsz += (nxt - i) + 1; /* plus trailing zero */
}
envno++; /* plus the terminating zero */
debug ("## %u envvars total size %u ", envno, envsz);
top = (top - sizeof (char **) * envno) & ~0xF;
fwenv = (char **)top;
debug ("## fwenv at 0x%08lX ", top);
top = (top - envsz) & ~0xF;
s = (char *)top;
ss = fwenv;
/* now copy them */
for (i = 0; env_get_char (i) != '\0'; i = nxt + 1) {
for (nxt = i; env_get_char (nxt) != '\0'; ++nxt)
;
*ss++ = s;
for (j = i; j < nxt; ++j)
*s++ = env_get_char (j);
*s++ = '\0';
}
*ss++ = NULL; /* terminate */
entry = (void (*)(bd_t *, char *, char **, ulong))images->ep;
(*entry) (kbd, cmdline, fwenv, top);
(*entry_point)();
return 1;
}

67
common/image.c
View file

@ -105,9 +105,6 @@ static table_entry_t uimage_arch[] = {
static table_entry_t uimage_os[] = {
{ IH_OS_INVALID, NULL, "Invalid OS", },
#if defined(CONFIG_ARTOS) || defined(USE_HOSTCC)
{ IH_OS_ARTOS, "artos", "ARTOS", },
#endif
{ IH_OS_LINUX, "linux", "Linux", },
#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
{ IH_OS_LYNXOS, "lynxos", "LynxOS", },
@ -119,6 +116,9 @@ static table_entry_t uimage_os[] = {
{ IH_OS_QNX, "qnx", "QNX", },
{ IH_OS_VXWORKS, "vxworks", "VxWorks", },
#endif
#if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC)
{ IH_OS_INTEGRITY,"integrity", "INTEGRITY", },
#endif
#ifdef USE_HOSTCC
{ IH_OS_4_4BSD, "4_4bsd", "4_4BSD", },
{ IH_OS_DELL, "dell", "Dell", },
@ -2645,27 +2645,29 @@ int fit_image_check_hashes (const void *fit, int image_noffset)
continue;
if (fit_image_hash_get_algo (fit, noffset, &algo)) {
err_msg = "Can't get hash algo property";
err_msg = " error!\nCan't get hash algo "
"property";
goto error;
}
printf ("%s", algo);
if (fit_image_hash_get_value (fit, noffset, &fit_value,
&fit_value_len)) {
err_msg = "Can't get hash value property";
err_msg = " error!\nCan't get hash value "
"property";
goto error;
}
if (calculate_hash (data, size, algo, value, &value_len)) {
err_msg = "Unsupported hash algorithm";
err_msg = " error!\nUnsupported hash algorithm";
goto error;
}
if (value_len != fit_value_len) {
err_msg = "Bad hash value len";
err_msg = " error !\nBad hash value len";
goto error;
} else if (memcmp (value, fit_value, value_len) != 0) {
err_msg = "Bad hash value";
err_msg = " error!\nBad hash value";
goto error;
}
printf ("+ ");
@ -2681,6 +2683,55 @@ error:
return 0;
}
/**
* fit_all_image_check_hashes - verify data intergity for all images
* @fit: pointer to the FIT format image header
*
* fit_all_image_check_hashes() goes over all images in the FIT and
* for every images checks if all it's hashes are valid.
*
* returns:
* 1, if all hashes of all images are valid
* 0, otherwise (or on error)
*/
int fit_all_image_check_hashes (const void *fit)
{
int images_noffset;
int noffset;
int ndepth;
int count;
/* Find images parent node offset */
images_noffset = fdt_path_offset (fit, FIT_IMAGES_PATH);
if (images_noffset < 0) {
printf ("Can't find images parent node '%s' (%s)\n",
FIT_IMAGES_PATH, fdt_strerror (images_noffset));
return 0;
}
/* Process all image subnodes, check hashes for each */
printf ("## Checking hash(es) for FIT Image at %08lx ...\n",
(ulong)fit);
for (ndepth = 0, count = 0,
noffset = fdt_next_node (fit, images_noffset, &ndepth);
(noffset >= 0) && (ndepth > 0);
noffset = fdt_next_node (fit, noffset, &ndepth)) {
if (ndepth == 1) {
/*
* Direct child node of the images parent node,
* i.e. component image node.
*/
printf (" Hash(es) for Image %u (%s): ", count++,
fit_get_name (fit, noffset, NULL));
if (!fit_image_check_hashes (fit, noffset))
return 0;
printf ("\n");
}
}
return 1;
}
/**
* fit_image_check_os - check whether image node is of a given os type
* @fit: pointer to the FIT format image header

13
common/usb.c
View file

@ -126,10 +126,15 @@ int usb_init(void)
*/
int usb_stop(void)
{
asynch_allowed=1;
usb_started = 0;
usb_hub_reset();
return usb_lowlevel_stop();
int res = 0;
if (usb_started) {
asynch_allowed = 1;
usb_started = 0;
usb_hub_reset();
res = usb_lowlevel_stop();
}
return res;
}
/*

2
common/usb_kbd.c
View file

@ -162,6 +162,8 @@ int drv_usb_kbd_init(void)
/* scan all USB Devices */
for(i=0;i<USB_MAX_DEVICE;i++) {
dev=usb_get_dev_index(i); /* get device */
if(dev == NULL)
return -1;
if(dev->devnum!=-1) {
if(usb_kbd_probe(dev,0)==1) { /* Ok, we found a keyboard */
/* check, if it is already registered */

5
cpu/arm1176/s3c64xx/interrupts.c
View file

@ -41,6 +41,7 @@
#include <common.h>
#include <asm/proc-armv/ptrace.h>
#include <s3c6400.h>
#include <div64.h>
static ulong timer_load_val;
@ -148,7 +149,9 @@ void reset_timer(void)
ulong get_timer_masked(void)
{
return get_ticks() / (timer_load_val / (100 * CFG_HZ));
unsigned long long res = get_ticks();
do_div (res, (timer_load_val / (100 * CFG_HZ)));
return res;
}
ulong get_timer(ulong base)

7
cpu/arm946es/config.mk
View file

@ -25,3 +25,10 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
PLATFORM_CPPFLAGS += -march=armv4
# =========================================================================
#
# Supply options according to compiler version
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

7
cpu/arm_intcm/config.mk
View file

@ -25,3 +25,10 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
PLATFORM_CPPFLAGS += -march=armv4
# =========================================================================
#
# Supply options according to compiler version
#
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

158
cpu/ppc4xx/44x_spd_ddr2.c
View file

@ -60,8 +60,6 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
static inline void ppc4xx_ibm_ddr2_register_dump(void);
#if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+
@ -260,62 +258,19 @@ static void program_ecc_addr(unsigned long start_address,
unsigned long num_bytes,
unsigned long tlb_word2_i_value);
#endif
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
static void program_DQS_calibration(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
static void test(void);
#else
static void DQS_calibration_process(void);
#endif
#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
static u32 mfdcr_any(u32 dcr)
{
u32 val;
switch (dcr) {
case SDRAM_R0BAS + 0:
val = mfdcr(SDRAM_R0BAS + 0);
break;
case SDRAM_R0BAS + 1:
val = mfdcr(SDRAM_R0BAS + 1);
break;
case SDRAM_R0BAS + 2:
val = mfdcr(SDRAM_R0BAS + 2);
break;
case SDRAM_R0BAS + 3:
val = mfdcr(SDRAM_R0BAS + 3);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
val = 0; /* just to satisfy the compiler */
}
return val;
}
static void mtdcr_any(u32 dcr, u32 val)
{
switch (dcr) {
case SDRAM_R0BAS + 0:
mtdcr(SDRAM_R0BAS + 0, val);
break;
case SDRAM_R0BAS + 1:
mtdcr(SDRAM_R0BAS + 1, val);
break;
case SDRAM_R0BAS + 2:
mtdcr(SDRAM_R0BAS + 2, val);
break;
case SDRAM_R0BAS + 3:
mtdcr(SDRAM_R0BAS + 3, val);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
}
}
static unsigned char spd_read(uchar chip, uint addr)
{
unsigned char data[2];
@ -609,7 +564,11 @@ phys_size_t initdram(int board_type)
/*------------------------------------------------------------------
* DQS calibration.
*-----------------------------------------------------------------*/
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
DQS_autocalibration();
#else
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#endif
#ifdef CONFIG_DDR_ECC
/*------------------------------------------------------------------
@ -2329,18 +2288,6 @@ static unsigned long is_ecc_enabled(void)
return ecc;
}
static void blank_string(int size)
{
int i;
for (i=0; i<size; i++)
putc('\b');
for (i=0; i<size; i++)
putc(' ');
for (i=0; i<size; i++)
putc('\b');
}
#ifdef CONFIG_DDR_ECC
/*-----------------------------------------------------------------------------+
* program_ecc.
@ -2468,6 +2415,7 @@ static void program_ecc_addr(unsigned long start_address,
}
#endif
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*-----------------------------------------------------------------------------+
* program_DQS_calibration.
*-----------------------------------------------------------------------------*/
@ -3001,7 +2949,8 @@ static void test(void)
(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
| ecc_temp);
}
#endif
#endif /* !HARD_CODED_DQS */
#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
#else /* CONFIG_SPD_EEPROM */
@ -3104,9 +3053,12 @@ phys_size_t initdram(int board_type)
/* Set Delay Control Registers */
mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
@ -3115,18 +3067,98 @@ phys_size_t initdram(int board_type)
mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#if defined(CONFIG_DDR_ECC)
ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
ppc4xx_ibm_ddr2_register_dump();
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*
* Clear potential errors resulting from auto-calibration.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CFG_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
static inline void ppc4xx_ibm_ddr2_register_dump(void)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
u32 val;
switch (dcr) {
case SDRAM_R0BAS + 0:
val = mfdcr(SDRAM_R0BAS + 0);
break;
case SDRAM_R0BAS + 1:
val = mfdcr(SDRAM_R0BAS + 1);
break;
case SDRAM_R0BAS + 2:
val = mfdcr(SDRAM_R0BAS + 2);
break;
case SDRAM_R0BAS + 3:
val = mfdcr(SDRAM_R0BAS + 3);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
val = 0; /* just to satisfy the compiler */
}
return val;
}
void mtdcr_any(u32 dcr, u32 val)
{
switch (dcr) {
case SDRAM_R0BAS + 0:
mtdcr(SDRAM_R0BAS + 0, val);
break;
case SDRAM_R0BAS + 1:
mtdcr(SDRAM_R0BAS + 1, val);
break;
case SDRAM_R0BAS + 2:
mtdcr(SDRAM_R0BAS + 2, val);
break;
case SDRAM_R0BAS + 3:
mtdcr(SDRAM_R0BAS + 3, val);
break;
default:
printf("DCR %d not defined in case statement!!!\n", dcr);
}
}
#endif /* defined(CONFIG_440) */
void blank_string(int size)
{
int i;
for (i = 0; i < size; i++)
putc('\b');
for (i = 0; i < size; i++)
putc(' ');
for (i = 0; i < size; i++)
putc('\b');
}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{
#if defined(DEBUG)
printf("\nPPC4xx IBM DDR2 Register Dump:\n");

168
cpu/ppc4xx/4xx_enet.c
View file

@ -198,6 +198,7 @@
#define BI_PHYMODE_RMII 8
#endif
#endif
#define BI_PHYMODE_SGMII 9
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@ -216,6 +217,52 @@
#define MAL_RX_CHAN_MUL 1
#endif
/*--------------------------------------------------------------------+
* Fixed PHY (PHY-less) support for Ethernet Ports.
*--------------------------------------------------------------------*/
/*
* Some boards do not have a PHY for each ethernet port. These ports
* are known as Fixed PHY (or PHY-less) ports. For such ports, set
* the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
* then define CFG_FIXED_PHY_PORTS to define what the speed and
* duplex should be for these ports in the board configuration
* file.
*
* For Example:
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
*
* #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY1_ADDR 1
* #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY3_ADDR 3
*
* #define CFG_FIXED_PHY_PORT(devnum,speed,duplex) \
* {devnum, speed, duplex},
*
* #define CFG_FIXED_PHY_PORTS \
* CFG_FIXED_PHY_PORT(0,1000,FULL) \
* CFG_FIXED_PHY_PORT(2,100,HALF)
*/
#ifndef CONFIG_FIXED_PHY
#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
#endif
#ifndef CFG_FIXED_PHY_PORTS
#define CFG_FIXED_PHY_PORTS /* default is an empty array */
#endif
struct fixed_phy_port {
unsigned int devnum; /* ethernet port */
unsigned int speed; /* specified speed 10,100 or 1000 */
unsigned int duplex; /* specified duplex FULL or HALF */
};
static const struct fixed_phy_port fixed_phy_port[] = {
CFG_FIXED_PHY_PORTS /* defined in board configuration file */
};
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
@ -611,8 +658,17 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
#if defined(CONFIG_460EX)
mode = 9;
mfsdr(SDR0_ETH_CFG, eth_cfg);
if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
mode = 11; /* config SGMII */
#else
mode = 10;
mfsdr(SDR0_ETH_CFG, eth_cfg);
if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
mode = 12; /* config SGMII */
#endif
/* TODO:
@ -635,6 +691,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
/*
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2008-02-19
* Add SGMII support.
* vg - 2008-07-28
*/
switch (mode) {
case 1:
@ -761,6 +819,20 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
bis->bi_phymode[2] = BI_PHYMODE_RGMII;
bis->bi_phymode[3] = BI_PHYMODE_RGMII;
break;
case 11:
/* 2 SGMII - 460EX */
bis->bi_phymode[0] = BI_PHYMODE_SGMII;
bis->bi_phymode[1] = BI_PHYMODE_SGMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 12:
/* 3 SGMII - 460GT */
bis->bi_phymode[0] = BI_PHYMODE_SGMII;
bis->bi_phymode[1] = BI_PHYMODE_SGMII;
bis->bi_phymode[2] = BI_PHYMODE_SGMII;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
default:
break;
}
@ -945,9 +1017,50 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
/*
* In SGMII mode, GPCS access is needed for
* communication with the internal SGMII SerDes.
*/
switch (devnum) {
#if defined(CONFIG_GPCS_PHY_ADDR)
case 0:
reg = CONFIG_GPCS_PHY_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY1_ADDR)
case 1:
reg = CONFIG_GPCS_PHY1_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY2_ADDR)
case 2:
reg = CONFIG_GPCS_PHY2_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY3_ADDR)
case 3:
reg = CONFIG_GPCS_PHY3_ADDR;
break;
#endif
}
mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg);
out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
/* Configure GPCS interface to recommended setting for SGMII */
miiphy_reset(dev->name, reg);
miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
}
#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
#ifndef CONFIG_CS8952_PHY
switch (devnum) {
case 0:
reg = CONFIG_PHY_ADDR;
@ -974,6 +1087,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
bis->bi_phynum[devnum] = reg;
if (reg == CONFIG_FIXED_PHY)
goto get_speed;
#if defined(CONFIG_PHY_RESET)
/*
* Reset the phy, only if its the first time through
@ -986,6 +1102,27 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write (dev->name, reg, 0x09, 0x0e00);
miiphy_write (dev->name, reg, 0x04, 0x01e1);
#endif
#if defined(CONFIG_M88E1112_PHY)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
/*
* Marvell 88E1112 PHY needs to have the SGMII MAC
* interace (page 2) properly configured to
* communicate with the 460EX/GT GPCS interface.
*/
/* Set access to Page 2 */
miiphy_write(dev->name, reg, 0x16, 0x0002);
miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
miiphy_read(dev->name, reg, 0x1a, &reg_short);
reg_short |= 0x8000; /* bypass Auto-Negotiation */
miiphy_write(dev->name, reg, 0x1a, reg_short);
miiphy_reset(dev->name, reg); /* reset MAC interface */
/* Reset access to Page 0 */
miiphy_write(dev->name, reg, 0x16, 0x0000);
}
#endif /* defined(CONFIG_M88E1112_PHY) */
miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX) || \
@ -1022,7 +1159,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif
#endif /* defined(CONFIG_CIS8201_PHY) */
#if defined(CONFIG_ET1011C_PHY)
/*
@ -1041,9 +1178,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
miiphy_write(dev->name, reg, 0x1c, 0x74f0);
}
#endif
#endif /* defined(CONFIG_ET1011C_PHY) */
#endif
#endif /* defined(CONFIG_440GX) ... */
/* Start/Restart autonegotiation */
phy_setup_aneg (dev->name, reg);
udelay (1000);
@ -1073,15 +1210,30 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
}
udelay (1000); /* 1 ms */
miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
}
#endif /* #ifndef CONFIG_CS8952_PHY */
speed = miiphy_speed (dev->name, reg);
duplex = miiphy_duplex (dev->name, reg);
get_speed:
if (reg == CONFIG_FIXED_PHY) {
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
if (devnum == fixed_phy_port[i].devnum) {
speed = fixed_phy_port[i].speed;
duplex = fixed_phy_port[i].duplex;
break;
}
}
if (i == ARRAY_SIZE(fixed_phy_port)) {
printf("ERROR: PHY (%s) not configured correctly!\n",
dev->name);
return -1;
}
} else {
speed = miiphy_speed(dev->name, reg);
duplex = miiphy_duplex(dev->name, reg);
}
if (hw_p->print_speed) {
hw_p->print_speed = 0;

1212
cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c Normal file
View file

File diff suppressed because it is too large Load diff

3
cpu/ppc4xx/Makefile
View file

@ -35,6 +35,9 @@ SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
COBJS += 4xx_ibm_ddr2_autocalib.o
endif
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += bedbug_405.o

37
cpu/ppc4xx/miiphy.c
View file

@ -180,8 +180,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
*
* sr: Currently on 460EX only EMAC0 works with MDIO, so we always
* return EMAC0 offset here
* vg: For 460EX/460GT if internal GPCS PHY address is specified
* return appropriate EMAC offset
*/
unsigned int miiphy_getemac_offset (void)
unsigned int miiphy_getemac_offset(u8 addr)
{
#if (defined(CONFIG_440) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@ -233,6 +235,35 @@ unsigned int miiphy_getemac_offset (void)
return 0x100;
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
u32 eoffset = 0;
switch (addr) {
#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
case CONFIG_GPCS_PHY1_ADDR:
if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
eoffset = 0x100;
break;
#endif
#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
case CONFIG_GPCS_PHY2_ADDR:
if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
eoffset = 0x300;
break;
#endif
#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
case CONFIG_GPCS_PHY3_ADDR:
if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
eoffset = 0x400;
break;
#endif
default:
eoffset = 0;
break;
}
return eoffset;
#endif
return 0;
#endif
}
@ -262,7 +293,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
u32 emac_reg;
u32 sta_reg;
emac_reg = miiphy_getemac_offset();
emac_reg = miiphy_getemac_offset(addr);
/* wait for completion */
if (emac_miiphy_wait(emac_reg) != 0)
@ -311,7 +342,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned long sta_reg;
unsigned long emac_reg;
emac_reg = miiphy_getemac_offset ();
emac_reg = miiphy_getemac_offset(addr);
if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
return -1;

6
disk/part.c
View file

@ -124,6 +124,12 @@ void dev_print (block_dev_desc_t *dev_desc)
dev_desc->revision,
dev_desc->product);
break;
case IF_TYPE_USB:
printf ("Vendor: %s Rev: %s Prod: %s\n",
dev_desc->vendor,
dev_desc->revision,
dev_desc->product);
break;
case IF_TYPE_UNKNOWN:
default:
puts ("not available\n");

2
doc/uImage.FIT/source_file_format.txt
View file

@ -169,7 +169,7 @@ the '/images' node should have the following layout:
- os : OS name, mandatory for type="kernel", valid OS names are: "openbsd",
"netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix", "solaris", "irix",
"sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx", "u_boot",
"rtems", "artos", "unity".
"rtems", "unity", "integrity".
- arch : Architecture name, mandatory for types: "standalone", "kernel",
"firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha",
"arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc",

2
drivers/mtd/mw_eeprom.c
View file

@ -1,7 +1,7 @@
/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */
#include <common.h>
#include <ssi.h>
#include <asm/ic/ssi.h>
/*
* Serial EEPROM opcodes, including start bit

6
drivers/rtc/Makefile
View file

@ -32,8 +32,8 @@ COBJS-y += date.o
COBJS-$(CONFIG_RTC_DS12887) += ds12887.o
COBJS-$(CONFIG_RTC_DS1302) += ds1302.o
COBJS-$(CONFIG_RTC_DS1306) += ds1306.o
COBJS-$(CONFIG_RTC_DS1307)$(CONFIG_RTC_DS1338) += ds1307.o
COBJS-y += $(COBJS-yy)
COBJS-$(CONFIG_RTC_DS1307) += ds1307.o
COBJS-$(CONFIG_RTC_DS1338) += ds1307.o
COBJS-$(CONFIG_RTC_DS1337) += ds1337.o
COBJS-$(CONFIG_RTC_DS1374) += ds1374.o
COBJS-$(CONFIG_RTC_DS1556) += ds1556.o
@ -59,7 +59,7 @@ COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
COBJS-$(CONFIG_RTC_X1205) += x1205.o
COBJS := $(COBJS-y)
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

2
drivers/rtc/mk48t59.c
View file

@ -227,7 +227,7 @@ void rtc_reset (void)
rtc_write(RTC_CONTROLB, control_b);
}
int rtc_set_watchdog(short multi, short res)
void rtc_set_watchdog(short multi, short res)
{
uchar wd_value;

3
drivers/rtc/rs5c372.c
View file

@ -195,8 +195,7 @@ rtc_get (struct rtc_time *tmp)
/*
* Set the RTC
*/
void
rtc_set (struct rtc_time *tmp)
int rtc_set (struct rtc_time *tmp)
{
unsigned char buf[8], reg15;
int ret;

6
drivers/serial/Makefile
View file

@ -33,13 +33,13 @@ COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-y += serial.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-y += serial_pl010.o
COBJS-y += serial_pl011.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_USB_TTY) += usbtty.o
COBJS := $(COBJS-y)
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

161
drivers/serial/serial_pl011.c
View file

@ -1,161 +0,0 @@
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* (C) Copyright 2004
* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
/* Should be fairly simple to make it work with the PL010 as well */
#include <common.h>
#ifdef CFG_PL011_SERIAL
#include "serial_pl011.h"
#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
#define IO_READ(addr) (*(volatile unsigned int *)(addr))
/*
* IntegratorCP has two UARTs, use the first one, at 38400-8-N-1
* Versatile PB has four UARTs.
*/
#define CONSOLE_PORT CONFIG_CONS_INDEX
#define baudRate CONFIG_BAUDRATE
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
static void pl011_putc (int portnum, char c);
static int pl011_getc (int portnum);
static int pl011_tstc (int portnum);
int serial_init (void)
{
unsigned int temp;
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
/*
** First, disable everything.
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
/*
** Set baud rate
**
** IBRD = UART_CLK / (16 * BAUD_RATE)
** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
*/
temp = 16 * baudRate;
divider = CONFIG_PL011_CLOCK / temp;
remainder = CONFIG_PL011_CLOCK % temp;
temp = (8 * remainder) / baudRate;
fraction = (temp >> 1) + (temp & 1);
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
/*
** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
/*
** Finally, enable the UART
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE));
return 0;
}
void serial_putc (const char c)
{
if (c == '\n')
pl011_putc (CONSOLE_PORT, '\r');
pl011_putc (CONSOLE_PORT, c);
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
return pl011_getc (CONSOLE_PORT);
}
int serial_tstc (void)
{
return pl011_tstc (CONSOLE_PORT);
}
void serial_setbrg (void)
{
}
static void pl011_putc (int portnum, char c)
{
/* Wait until there is space in the FIFO */
while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
/* Send the character */
IO_WRITE (port[portnum] + UART_PL01x_DR, c);
}
static int pl011_getc (int portnum)
{
unsigned int data;
/* Wait until there is data in the FIFO */
while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
data = IO_READ (port[portnum] + UART_PL01x_DR);
/* Check for an error flag */
if (data & 0xFFFFFF00) {
/* Clear the error */
IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
return -1;
}
return (int) data;
}
static int pl011_tstc (int portnum)
{
return !(IO_READ (port[portnum] + UART_PL01x_FR) &
UART_PL01x_FR_RXFE);
}
#endif

88
drivers/serial/serial_pl010.c → drivers/serial/serial_pl01x.c
View file

@ -25,30 +25,31 @@
* MA 02111-1307 USA
*/
/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
/* Should be fairly simple to make it work with the PL010 as well */
/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
#include <common.h>
#include <watchdog.h>
#ifdef CFG_PL010_SERIAL
#include "serial_pl011.h"
#include "serial_pl01x.h"
#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
#define IO_READ(addr) (*(volatile unsigned int *)(addr))
/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */
/*
* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
* Integrator CP has two UARTs, use the first one, at 38400-8-N-1
* Versatile PB has four UARTs.
*/
#define CONSOLE_PORT CONFIG_CONS_INDEX
#define baudRate CONFIG_BAUDRATE
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
static void pl01x_putc (int portnum, char c);
static int pl01x_getc (int portnum);
static int pl01x_tstc (int portnum);
static void pl010_putc (int portnum, char c);
static int pl010_getc (int portnum);
static int pl010_tstc (int portnum);
#ifdef CONFIG_PL010_SERIAL
int serial_init (void)
{
@ -103,15 +104,64 @@ int serial_init (void)
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
return (0);
return 0;
}
#endif /* CONFIG_PL010_SERIAL */
#ifdef CONFIG_PL011_SERIAL
int serial_init (void)
{
unsigned int temp;
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
/*
** First, disable everything.
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
/*
** Set baud rate
**
** IBRD = UART_CLK / (16 * BAUD_RATE)
** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
*/
temp = 16 * baudRate;
divider = CONFIG_PL011_CLOCK / temp;
remainder = CONFIG_PL011_CLOCK % temp;
temp = (8 * remainder) / baudRate;
fraction = (temp >> 1) + (temp & 1);
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
/*
** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
/*
** Finally, enable the UART
*/
IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE));
return 0;
}
#endif /* CONFIG_PL011_SERIAL */
void serial_putc (const char c)
{
if (c == '\n')
pl010_putc (CONSOLE_PORT, '\r');
pl01x_putc (CONSOLE_PORT, '\r');
pl010_putc (CONSOLE_PORT, c);
pl01x_putc (CONSOLE_PORT, c);
}
void serial_puts (const char *s)
@ -123,19 +173,19 @@ void serial_puts (const char *s)
int serial_getc (void)
{
return pl010_getc (CONSOLE_PORT);
return pl01x_getc (CONSOLE_PORT);
}
int serial_tstc (void)
{
return pl010_tstc (CONSOLE_PORT);
return pl01x_tstc (CONSOLE_PORT);
}
void serial_setbrg (void)
{
}
static void pl010_putc (int portnum, char c)
static void pl01x_putc (int portnum, char c)
{
/* Wait until there is space in the FIFO */
while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
@ -145,7 +195,7 @@ static void pl010_putc (int portnum, char c)
IO_WRITE (port[portnum] + UART_PL01x_DR, c);
}
static int pl010_getc (int portnum)
static int pl01x_getc (int portnum)
{
unsigned int data;
@ -165,11 +215,9 @@ static int pl010_getc (int portnum)
return (int) data;
}
static int pl010_tstc (int portnum)
static int pl01x_tstc (int portnum)
{
WATCHDOG_RESET();
return !(IO_READ (port[portnum] + UART_PL01x_FR) &
UART_PL01x_FR_RXFE);
}
#endif

0
drivers/serial/serial_pl011.h → drivers/serial/serial_pl01x.h
View file

4
drivers/usb/usb_ohci.c
View file

@ -1943,7 +1943,9 @@ int usb_lowlevel_stop(void)
if(usb_cpu_stop())
return -1;
#endif
/* This driver is no longer initialised. It needs a new low-level
* init (board/cpu) before it can be used again. */
ohci_inited = 0;
return 0;
}
#endif /* CONFIG_USB_OHCI_NEW */

16
examples/82559_eeprom.c
View file

@ -51,13 +51,17 @@ static inline unsigned short swap16(unsigned short x)
}
static inline void *memcpy(void *dst, const void *src, unsigned int len)
void * memcpy(void * dest,const void *src,size_t count)
{
void * ret = dst;
while (len-- > 0) *((char *)dst)++ = *((char *)src)++;
return ret;
char *tmp = (char *) dest, *s = (char *) src;
while (count--)
*tmp++ = *s++;
return dest;
}
/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD (5)
#define EE_READ_CMD (6)
@ -156,7 +160,7 @@ static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
int size_test;
int i;
printf("Resetting i82559 EEPROM @ 0x%08x ... ", ioaddr);
printf("Resetting i82559 EEPROM @ 0x%08lx ... ", ioaddr);
size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
@ -305,7 +309,7 @@ write_config_word(int bus, int dev, int func, int reg, u16 data)
int main (int argc, char *argv[])
{
unsigned char *eth_addr;
char buf[6];
uchar buf[6];
int instance;
app_startup(argv);

4
include/asm-i386/byteorder.h
View file

@ -6,7 +6,7 @@
#ifdef __GNUC__
static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
static __inline__ __u32 ___arch__swab32(__u32 x)
{
#ifdef CONFIG_X86_BSWAP
__asm__("bswap %0" : "=r" (x) : "0" (x));
@ -20,7 +20,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
return x;
}
static __inline__ __const__ __u16 ___arch__swab16(__u16 x)
static __inline__ __u16 ___arch__swab16(__u16 x)
{
__asm__("xchgb %b0,%h0" /* swap bytes */ \
: "=q" (x) \

4
include/asm-i386/global_data.h
View file

@ -59,8 +59,8 @@ typedef struct {
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
extern gd_t *global_data;
extern gd_t *gd;
#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data
#define DECLARE_GLOBAL_DATA_PTR
#endif /* __ASM_GBL_DATA_H */

34
include/asm-i386/ic/ssi.h Normal file
View file

@ -0,0 +1,34 @@
/*
* (C) Copyright 2008
* Graeme Russ <graeme.russ@gmail.com>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_IC_SSI_H_
#define _ASM_IC_SSI_H_ 1
int ssi_set_interface(int, int, int, int);
void ssi_chip_select(int);
u8 ssi_txrx_byte(u8);
void ssi_tx_byte(u8);
u8 ssi_rx_byte(void);
#endif

1
include/asm-i386/pci.h
View file

@ -31,5 +31,4 @@ int pci_enable_legacy_video_ports(struct pci_controller* hose);
int pci_shadow_rom(pci_dev_t dev, unsigned char *dest);
void pci_remove_rom_window(struct pci_controller* hose, u32 addr);
u32 pci_get_rom_window(struct pci_controller* hose, int size);
#endif

2
include/asm-i386/string.h
View file

@ -5,6 +5,8 @@
* We don't do inline string functions, since the
* optimised inline asm versions are not small.
*/
#undef __HAVE_ARCH_STRNCPY
extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n);
#undef __HAVE_ARCH_STRRCHR
extern char * strrchr(const char * s, int c);

17
include/asm-ppc/ppc4xx-sdram.h
View file

@ -29,6 +29,7 @@
/*
* SDRAM Controller
*/
/*
* XXX - ToDo: Revisit file to change all these lower case defines into
* upper case. Also needs to be done in the controller setup code too
@ -256,6 +257,7 @@
#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
#if !defined(CONFIG_405EX)
/*
* Memory queue defines
*/
@ -293,7 +295,6 @@
#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
#if !defined(CONFIG_405EX)
/*
* Memory Bank 0-7 configuration
*/
@ -1401,4 +1402,18 @@
#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
#ifndef __ASSEMBLY__
/*
* Prototypes
*/
void inline blank_string(int size);
inline void ppc4xx_ibm_ddr2_register_dump(void);
u32 mfdcr_any(u32);
void mtdcr_any(u32, u32);
u32 ddr_wrdtr(u32);
u32 ddr_clktr(u32);
void spd_ddr_init_hang(void);
u32 DQS_autocalibration(void);
#endif /* __ASSEMBLY__ */
#endif /* _PPC4xx_SDRAM_H_ */

3
include/common.h
View file

@ -236,6 +236,9 @@ int autoscript (ulong addr, const char *fit_uname);
extern ulong load_addr; /* Default Load Address */
/* common/cmd_doc.c */
void doc_probe(unsigned long physadr);
/* common/cmd_nvedit.c */
int env_init (void);
void env_relocate (void);

6
include/configs/CPCI4052.h
View file

@ -146,6 +146,8 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
@ -219,6 +221,10 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/*-----------------------------------------------------------------------
* FLASH organization
*/

6
include/configs/CPCI405AB.h
View file

@ -144,6 +144,8 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@ -215,6 +217,10 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/*-----------------------------------------------------------------------
* FLASH organization
*/

2
include/configs/NETPHONE.h
View file

@ -487,8 +487,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_ARTOS /* include ARTOS support */
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/****************************************************************/

2
include/configs/NETTA.h
View file

@ -496,8 +496,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_ARTOS /* include ARTOS support */
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/***********************************************************************************************************

3
include/configs/NETTA2.h
View file

@ -488,8 +488,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_ARTOS /* include ARTOS support */
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/****************************************************************/
@ -745,7 +743,6 @@ typedef unsigned int led_id_t;
/* use board specific hardware */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG
#define CONFIG_SHOW_ACTIVITY
/*************************************************************************************************/

2
include/configs/NETVIA.h
View file

@ -357,8 +357,6 @@
/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET
#define CONFIG_ARTOS /* include ARTOS support */
/****************************************************************/
#define DSP_SIZE 0x00010000 /* 64K */

1
include/configs/PIP405.h
View file

@ -281,7 +281,6 @@
***********************************************************/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
/************************************************************
* RTC
***********************************************************/

2
include/configs/integratorap.h
View file

@ -58,7 +58,7 @@
/*
* PL010 Configuration
*/
#define CFG_PL010_SERIAL
#define CONFIG_PL010_SERIAL
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 38400
#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }

2
include/configs/integratorcp.h
View file

@ -61,7 +61,7 @@
/*
* NS16550 Configuration
*/
#define CFG_PL011_SERIAL
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 14745600
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_CONS_INDEX 0

19
include/configs/kilauea.h
View file

@ -223,6 +223,22 @@
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
/*
* CONFIG_PPC4xx_DDR_AUTOCALIBRATION
*
* Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
* SDRAM Controller DDR autocalibration values and takes a lot longer
* to run than Method_B.
* (See the Method_A and Method_B algorithm discription in the file:
* cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
*
* DDR Autocalibration Method_B is the default.
*/
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
/* DDR1/2 SDRAM Device Control Register Data Values */
@ -386,6 +402,9 @@
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 2
/* Debug messages for the DDR autocalibration */
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
/*
* Default environment variables
*/

91
include/configs/ml507.h
View file

@ -17,106 +17,33 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
#define DEBUG
#define ET_DEBUG
*/
/*CPU*/
#define CONFIG_XILINX_ML507 1
#define CONFIG_XILINX_440 1
/*CPU*/
#define CONFIG_440 1
#define CONFIG_4xx 1
#define CONFIG_XILINX_ML507 1
#include "../board/xilinx/ml507/xparameters.h"
/*Mem Map*/
#define CFG_SDRAM_BASE 0x0
#define CFG_SDRAM_SIZE_MB 256
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN ( 192 * 1024 )
#define CFG_MALLOC_LEN ( CFG_ENV_SIZE + 128 * 1024 )
/*Uart*/
#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE }
#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
/*Cmd*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_DTT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS
/*Env*/
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x20000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_OFFSET 0x340000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
#define CFG_ENV_OFFSET 0x340000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
/*Misc*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_LOOPW /* enable loopw command */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CFG_HUSH_PARSER /* Use the HUSH parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */
#define CFG_PROMPT "ml507:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Stack*/
#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*Speed*/
#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
/*Flash*/
#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CFG_FLASH_SIZE (32*1024*1024)
#define CFG_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 259
#define CFG_FLASH_PROTECTION
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

24
include/configs/sc520_cdp.h
View file

@ -28,6 +28,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define GRUSS_TESTING
/*
* High Level Configuration Options
* (easy to change)
@ -81,7 +82,11 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#ifndef GRUSS_TESTING
#define CONFIG_CMD_SATA
#else
#undef CONFIG_CMD_SATA
#endif
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NET
#define CONFIG_CMD_EEPROM
@ -175,10 +180,18 @@
/************************************************************
*SATA/Native Stuff
************************************************************/
#ifndef GRUSS_TESTING
#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
#define CFG_SATA_MAX_DEVICE (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
#define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */
#else
#undef CFG_SATA_MAXBUS
#undef CFG_SATA_DEVS_PER_BUS
#undef CFG_SATA_MAX_DEVICE
#undef CONFIG_ATA_PIIX
#endif
/************************************************************
* DISK Partition support
@ -190,7 +203,11 @@
/************************************************************
* Video/Keyboard support
************************************************************/
#ifndef GRUSS_TESTING
#define CONFIG_VIDEO /* To enable video controller support */
#else
#undef CONFIG_VIDEO
#endif
#define CONFIG_I8042_KBD
#define CFG_ISA_IO 0
@ -203,6 +220,7 @@
/*
* PCI stuff
*/
#ifndef GRUSS_TESTING
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW
@ -211,5 +229,11 @@
#define CFG_SECOND_PCI_IRQ 9
#define CFG_THIRD_PCI_IRQ 11
#define CFG_FORTH_PCI_IRQ 15
#else
#undef CONFIG_PCI
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
#endif
#endif /* __CONFIG_H */

1
include/configs/stxxtc.h
View file

@ -580,7 +580,6 @@ typedef unsigned int led_id_t;
/* use board specific hardware */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG
#define CONFIG_SHOW_ACTIVITY
/*****************************************************************************/

49
include/configs/v5fx30teval.h Normal file
View file

@ -0,0 +1,49 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_ML507 1
#include "../board/avnet/v5fx30teval/xparameters.h"
/*Mem Map*/
#define CFG_SDRAM_SIZE_MB 64
/*Env*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x20000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_OFFSET 0x1A0000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
/*Misc*/
#define CFG_PROMPT "v5fx30t:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CFG_FLASH_SIZE (16*1024*1024)
#define CFG_MAX_FLASH_SECT 131
#define MTDIDS_DEFAULT "nor0=v5fx30t-flash"
#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

2
include/configs/versatile.h
View file

@ -86,7 +86,7 @@
/*
* NS16550 Configuration
*/
#define CFG_PL011_SERIAL
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_CONS_INDEX 0

49
include/configs/xilinx-ppc440-generic.h Normal file
View file

@ -0,0 +1,49 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_PPC440_GENERIC 1
#include "../board/xilinx/ppc440-generic/xparameters.h"
/*Mem Map*/
#define CFG_SDRAM_SIZE_MB 256
/*Env*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x20000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_OFFSET 0x340000
#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET)
/*Misc*/
#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CFG_FLASH_SIZE (32*1024*1024)
#define CFG_MAX_FLASH_SECT 259
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

106
include/configs/xilinx-ppc440.h Normal file
View file

@ -0,0 +1,106 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_GEN_H
#define __CONFIG_GEN_H
/*
#define DEBUG
#define ET_DEBUG
*/
/*CPU*/
#define CONFIG_XILINX_440 1
#define CONFIG_440 1
#define CONFIG_4xx 1
/*Mem Map*/
#define CFG_SDRAM_BASE 0x0
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 * 1024)
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
/*Uart*/
#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE }
#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
/*Cmd*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
#undef CONFIG_CMD_SPI
#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_DTT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS
/*Misc*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_LOOPW /* enable loopw command */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CFG_HUSH_PARSER /* Use the HUSH parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
/*Stack*/
#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*Speed*/
#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
/*Flash*/
#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CFG_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_PROTECTION
#endif /* __CONFIG_H */

2
include/image.h
View file

@ -85,6 +85,7 @@
#define IH_OS_RTEMS 18 /* RTEMS */
#define IH_OS_ARTOS 19 /* ARTOS */
#define IH_OS_UNITY 20 /* Unity OS */
#define IH_OS_INTEGRITY 21 /* INTEGRITY */
/*
* CPU Architecture Codes (supported by Linux)
@ -573,6 +574,7 @@ int fit_image_hash_set_value (void *fit, int noffset, uint8_t *value,
int value_len);
int fit_image_check_hashes (const void *fit, int noffset);
int fit_all_image_check_hashes (const void *fit);
int fit_image_check_os (const void *fit, int noffset, uint8_t os);
int fit_image_check_arch (const void *fit, int noffset, uint8_t arch);
int fit_image_check_type (const void *fit, int noffset, uint8_t type);

1
include/onenand_uboot.h
View file

@ -15,6 +15,7 @@
#define __UBOOT_ONENAND_H
#include <linux/types.h>
#include <linux/mtd/mtd.h>
struct mtd_info;
struct erase_info;

13
include/ppc440.h
View file

@ -2064,19 +2064,6 @@
#ifndef __ASSEMBLY__
static inline u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static inline void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
#endif /* _ASMLANGUAGE */
#endif /* __PPC440_H__ */

13
include/ppc4xx.h
View file

@ -203,6 +203,19 @@ typedef struct
unsigned long pllPlbDiv;
} PPC4xx_SYS_INFO;
static inline u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static inline void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
#endif /* __ASSEMBLY__ */
#endif /* __PPC4XX_H__ */

3
include/ppc4xx_enet.h
View file

@ -376,6 +376,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M1_APP (0x08000000)
#define EMAC_M1_RSVD (0x06000000)
#define EMAC_M1_IST (0x01000000)
#define EMAC_M1_MF_1000GPCS (0x00C00000)
#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
#define EMAC_M1_MF_100MBPS (0x00400000)
#define EMAC_M1_RFS_MASK (0x00380000)
@ -394,6 +395,8 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M1_MWSW (0x00007000)
#define EMAC_M1_JUMBO_ENABLE (0x00000800)
#define EMAC_M1_IPPA (0x000007c0)
#define EMAC_M1_IPPA_SET(id) (((id) & 0x1f) << 6)
#define EMAC_M1_IPPA_GET(id) (((id) >> 6) & 0x1f)
#define EMAC_M1_OBCI_GT100 (0x00000020)
#define EMAC_M1_OBCI_100 (0x00000018)
#define EMAC_M1_OBCI_83 (0x00000010)

3
lib_arm/bootm.c
View file

@ -62,7 +62,6 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
char *s;
int machid = bd->bi_arch_number;
void (*theKernel)(int zero, int arch, uint params);
int ret;
#ifdef CONFIG_CMDLINE_TAG
char *commandline = getenv ("bootargs");
@ -125,7 +124,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
theKernel (0, machid, bd->bi_boot_params);
/* does not return */
error:
return 1;
}

6
lib_i386/bios_setup.c
View file

@ -140,8 +140,9 @@ int bios_setup(void)
{
static int done=0;
int vector;
#ifdef CONFIG_PCI
struct pci_controller *pri_hose;
#endif
if (done) {
return 0;
}
@ -223,12 +224,13 @@ int bios_setup(void)
* (This, ofcause break on multi hose systems,
* but our PCI BIOS only support one hose anyway)
*/
#ifdef CONFIG_PCI
pri_hose = pci_bus_to_hose(0);
if (NULL != pri_hose) {
/* fill in last pci bus number for use by the realmode
* PCI BIOS */
RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno;
}
#endif
return 0;
}

13
lib_i386/board.c
View file

@ -213,7 +213,7 @@ init_fnc_t *init_sequence[] = {
NULL,
};
gd_t *global_data;
gd_t *gd;
void start_i386boot (void)
{
@ -226,7 +226,7 @@ void start_i386boot (void)
show_boot_progress(0x21);
gd = global_data = &gd_data;
gd = &gd_data;
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
@ -266,7 +266,7 @@ void start_i386boot (void)
int i;
ulong reg;
char *s, *e;
uchar tmp[64];
char tmp[64];
i = getenv_r ("ethaddr", tmp, sizeof (tmp));
s = (i > 0) ? tmp : NULL;
@ -412,7 +412,10 @@ void hang (void)
unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[])
{
/*
* Nios function pointers are address >> 1
* TODO: Test this function - changed to fix compiler error.
* Original code was:
* return (entry >> 1) (argc, argv);
* with a comment about Nios function pointers are address >> 1
*/
return (entry >> 1) (argc, argv);
return (entry) (argc, argv);
}

2
lib_i386/bootm.c
View file

@ -34,7 +34,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
void *base_ptr;
ulong os_data, os_len;
image_header_t *hdr;
int ret;
#if defined(CONFIG_FIT)
const void *data;
size_t len;

3
lib_i386/video_bios.c
View file

@ -136,6 +136,8 @@ static u32 probe_pci_video(void)
#endif
#ifdef CONFIG_VIDEO
static int probe_isa_video(void)
{
u32 ptr;
@ -217,3 +219,4 @@ int video_bios_init(void)
return 1;
}
#endif

4
lib_mips/Makefile
View file

@ -28,7 +28,11 @@ LIB = $(obj)lib$(ARCH).a
SOBJS-y +=
COBJS-y += board.o
ifeq ($(CONFIG_QEMU_MIPS),y)
COBJS-y += bootm_qemu_mips.o
else
COBJS-y += bootm.o
endif
COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

2
lib_mips/bootm.c
View file

@ -73,7 +73,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
linux_env_set ("memsize", env_buf);
sprintf (env_buf, "0x%08X", (uint) UNCACHED_SDRAM (images->rd_start));
linux_env_set ("images->rd_start", env_buf);
linux_env_set ("initrd_start", env_buf);
sprintf (env_buf, "0x%X", (uint) (images->rd_end - images->rd_start));
linux_env_set ("initrd_size", env_buf);

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