mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
- Andes: Enable Andes CPU memboost and ECC feature by default - Sifive: Add private L2 cache driver
This commit is contained in:
commit
64e47952f5
17 changed files with 164 additions and 38 deletions
|
@ -31,19 +31,34 @@ void harts_early_init(void)
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/* Enable I/D-cache in SPL */
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
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unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
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mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
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MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
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mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
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MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
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MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
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MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
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if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
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mcache_ctl_val |= MCACHE_CTL_IC_EN;
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
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csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
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/*
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* Check mcache_ctl.DC_COHEN, we assume this platform does
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* not support CM if the bit is hard-wired to 0.
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*/
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if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
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/* Wait for DC_COHSTA bit to be set */
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while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
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/*
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* Check mcache_ctl.DC_COHEN, we assume this platform does
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* not support CM if the bit is hard-wired to 0.
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*/
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if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
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/* Wait for DC_COHSTA bit to be set */
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while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
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}
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}
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mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
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csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
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}
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}
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@ -12,7 +12,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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model = "AMD MicroBlaze V 32bit";
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compatible = "amd,mbv";
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compatible = "qemu,mbv", "amd,mbv";
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cpus: cpus {
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#address-cells = <1>;
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@ -12,20 +12,25 @@
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MMISC_CTL 0x7d0
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#define CSR_MARCHID 0xf12
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#define CSR_MCCTLCOMMAND 0x7cc
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#define MCACHE_CTL_IC_EN_OFFSET 0
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#define MCACHE_CTL_DC_EN_OFFSET 1
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_DC_COHEN_OFFSET 19
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#define MCACHE_CTL_DC_COHSTA_OFFSET 20
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/* mcache_ctl register */
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#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
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#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
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#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
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#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
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#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
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#define MCACHE_CTL_IC_EN BIT(0)
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#define MCACHE_CTL_DC_EN BIT(1)
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#define MCACHE_CTL_IC_ECCEN BIT(3)
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#define MCACHE_CTL_DC_ECCEN BIT(5)
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#define MCACHE_CTL_CCTL_SUEN BIT(8)
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#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
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#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
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#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
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#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
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#define MCACHE_CTL_TLB_ECCEN BIT(18)
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#define MCACHE_CTL_DC_COHEN BIT(19)
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#define MCACHE_CTL_DC_COHSTA BIT(20)
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/* mmisc_ctl register */
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#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
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#define CCTL_L1D_WBINVAL_ALL 6
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@ -142,6 +142,7 @@
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_MARCHID 0xf12
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#define CSR_MHARTID 0xf14
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#ifndef __ASSEMBLY__
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@ -7,7 +7,10 @@
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#include <cpu_func.h>
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#include <log.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#ifndef CONFIG_SPL_BUILD
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void enable_caches(void)
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{
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struct udevice *dev;
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@ -25,3 +28,21 @@ void enable_caches(void)
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log_debug("ccache enable failed");
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}
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}
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#else
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static inline void probe_cache_device(struct driver *driver, struct udevice *dev)
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{
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for (uclass_find_first_device(UCLASS_CACHE, &dev);
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dev;
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uclass_find_next_device(&dev)) {
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if (dev->driver == driver)
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device_probe(dev);
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}
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}
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void enable_caches(void)
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{
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struct udevice *dev = NULL;
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probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
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}
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#endif /* !CONFIG_SPL_BUILD */
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@ -13,7 +13,9 @@
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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#include <netdev.h>
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#endif
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#include <asm/csr.h>
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#include <asm/global_data.h>
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#include <asm/sbi.h>
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#include <linux/io.h>
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#include <faraday/ftsmc020.h>
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#include <fdtdec.h>
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@ -27,6 +29,27 @@ DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initializations
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*/
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#if IS_ENABLED(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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long csr_marchid = 0;
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const long mask_64 = 0x8000;
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const long mask_cpu = 0xff;
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char cpu_name[10] = {};
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#if CONFIG_IS_ENABLED(RISCV_SMODE)
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sbi_get_marchid(&csr_marchid);
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#elif CONFIG_IS_ENABLED(RISCV_MMODE)
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csr_marchid = csr_read(CSR_MARCHID);
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#endif
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if (mask_64 & csr_marchid)
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snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid));
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else
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snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
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return env_set("cpu", cpu_name);
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}
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#endif
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#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
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#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
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@ -102,7 +125,8 @@ void *board_fdt_blob_setup(int *err)
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void spl_board_init()
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{
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/* enable v5l2 cache */
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enable_caches();
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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enable_caches();
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}
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#endif
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@ -11,14 +11,15 @@ CONFIG_SYS_LOAD_ADDR=0x100000
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CONFIG_TARGET_ANDES_AE350=y
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CONFIG_SYS_MONITOR_BASE=0x88000000
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CONFIG_FIT=y
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_PBSIZE=1050
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_SYS_PBSIZE=1050
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF_TEST=y
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@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y
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CONFIG_SYS_MONITOR_BASE=0x88000000
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_PBSIZE=1050
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x100000
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CONFIG_SPL_BSS_START_ADDR=0x400000
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CONFIG_SPL_BOARD_INIT=y
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CONFIG_SPL_CACHE=y
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CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_SYS_PBSIZE=1050
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF_TEST=y
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@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y
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CONFIG_SYS_MONITOR_BASE=0x88000000
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_PBSIZE=1050
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x100000
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CONFIG_SPL_BSS_START_ADDR=0x400000
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CONFIG_SPL_BOARD_INIT=y
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CONFIG_SPL_CACHE=y
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CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_SYS_PBSIZE=1050
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF_TEST=y
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|
|
|
@ -12,14 +12,15 @@ CONFIG_TARGET_ANDES_AE350=y
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CONFIG_XIP=y
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CONFIG_SYS_MONITOR_BASE=0x88000000
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CONFIG_FIT=y
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_PBSIZE=1050
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SYS_PROMPT="RISC-V # "
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CONFIG_SYS_PBSIZE=1050
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF_TEST=y
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|
|
|
@ -11,14 +11,15 @@ CONFIG_TARGET_ANDES_AE350=y
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CONFIG_ARCH_RV64I=y
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CONFIG_SYS_MONITOR_BASE=0x88000000
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CONFIG_FIT=y
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_PBSIZE=1050
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CONFIG_DISPLAY_CPUINFO=y
|
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CONFIG_DISPLAY_BOARDINFO=y
|
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_MISC_INIT_R=y
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CONFIG_SYS_PROMPT="RISC-V # "
|
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CONFIG_SYS_PBSIZE=1050
|
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_MMC=y
|
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CONFIG_CMD_SF_TEST=y
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|
|
|
@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y
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CONFIG_SYS_MONITOR_BASE=0x88000000
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CONFIG_FIT=y
|
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
|
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CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
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CONFIG_BOOTDELAY=3
|
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CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
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CONFIG_DISPLAY_BOARDINFO=y
|
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CONFIG_BOARD_EARLY_INIT_F=y
|
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CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_MAX_SIZE=0x100000
|
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CONFIG_SPL_BSS_START_ADDR=0x400000
|
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CONFIG_SPL_BOARD_INIT=y
|
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CONFIG_SPL_CACHE=y
|
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CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
|
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CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_PBSIZE=1050
|
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CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF_TEST=y
|
||||
|
|
|
@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y
|
|||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
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CONFIG_FIT=y
|
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SPL_MAX_SIZE=0x100000
|
||||
CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_CACHE=y
|
||||
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF_TEST=y
|
||||
|
|
|
@ -12,14 +12,15 @@ CONFIG_ARCH_RV64I=y
|
|||
CONFIG_XIP=y
|
||||
CONFIG_SYS_MONITOR_BASE=0x88000000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_SYS_PROMPT="RISC-V # "
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_SYS_BOOTM_LEN=0x4000000
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF_TEST=y
|
||||
|
|
7
drivers/cache/Kconfig
vendored
7
drivers/cache/Kconfig
vendored
|
@ -45,4 +45,11 @@ config SIFIVE_CCACHE
|
|||
This driver is for SiFive Composable L2/L3 cache. It enables cache
|
||||
ways of composable cache.
|
||||
|
||||
config SIFIVE_PL2
|
||||
bool "SiFive private L2 cache"
|
||||
select CACHE
|
||||
help
|
||||
This driver is for SiFive Private L2 cache. It configures registers
|
||||
to enable the clock gating feature.
|
||||
|
||||
endmenu
|
||||
|
|
1
drivers/cache/Makefile
vendored
1
drivers/cache/Makefile
vendored
|
@ -5,3 +5,4 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
|
|||
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
|
||||
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
|
||||
obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
|
||||
obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o
|
||||
|
|
44
drivers/cache/cache-sifive-pl2.c
vendored
Normal file
44
drivers/cache/cache-sifive-pl2.c
vendored
Normal file
|
@ -0,0 +1,44 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 SiFive
|
||||
*/
|
||||
|
||||
#include <cache.h>
|
||||
#include <dm.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/device-internal.h>
|
||||
|
||||
#define SIFIVE_PL2CHICKENBIT_OFFSET 0x1000
|
||||
#define SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK BIT(3)
|
||||
|
||||
static int sifive_pl2_probe(struct udevice *dev)
|
||||
{
|
||||
fdt_addr_t base;
|
||||
u32 val;
|
||||
|
||||
base = dev_read_addr(dev);
|
||||
if (base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
/* Enable regionClockDisable bit */
|
||||
val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
|
||||
writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
|
||||
(void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id sifive_pl2_ids[] = {
|
||||
{ .compatible = "sifive,pl2cache0" },
|
||||
{ .compatible = "sifive,pl2cache1" },
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(sifive_pl2) = {
|
||||
.name = "sifive_pl2",
|
||||
.id = UCLASS_CACHE,
|
||||
.of_match = sifive_pl2_ids,
|
||||
.probe = sifive_pl2_probe,
|
||||
};
|
Loading…
Reference in a new issue