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Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next

Browse source 
- Andes: Enable Andes CPU memboost and ECC feature by default
- Sifive: Add private L2 cache driver
This commit is contained in:
Tom Rini 2023-12-28 07:54:54 -05:00
commit 64e47952f5
17 changed files with 164 additions and 38 deletions
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33
arch/riscv/cpu/andesv5/cpu.c
View file

@ -31,19 +31,34 @@ void harts_early_init(void)
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl_val |= MCACHE_CTL_IC_EN;
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/*
* Check mcache_ctl.DC_COHEN, we assume this platform does
* not support CM if the bit is hard-wired to 0.
*/
if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
/* Wait for DC_COHSTA bit to be set */
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
/*
* Check mcache_ctl.DC_COHEN, we assume this platform does
* not support CM if the bit is hard-wired to 0.
*/
if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
/* Wait for DC_COHSTA bit to be set */
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
}
}
mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
}
}

2
arch/riscv/dts/xilinx-mbv32.dts
View file

@ -12,7 +12,7 @@
#address-cells = <1>;
#size-cells = <1>;
model = "AMD MicroBlaze V 32bit";
compatible = "amd,mbv";
compatible = "qemu,mbv", "amd,mbv";
cpus: cpus {
#address-cells = <1>;

27
arch/riscv/include/asm/arch-andes/csr.h
View file

@ -12,20 +12,25 @@
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MARCHID 0xf12
#define CSR_MCCTLCOMMAND 0x7cc
#define MCACHE_CTL_IC_EN_OFFSET 0
#define MCACHE_CTL_DC_EN_OFFSET 1
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_DC_COHEN_OFFSET 19
#define MCACHE_CTL_DC_COHSTA_OFFSET 20
/* mcache_ctl register */
#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_IC_ECCEN BIT(3)
#define MCACHE_CTL_DC_ECCEN BIT(5)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_TLB_ECCEN BIT(18)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
/* mmisc_ctl register */
#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6

1
arch/riscv/include/asm/csr.h
View file

@ -142,6 +142,7 @@
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_MARCHID 0xf12
#define CSR_MHARTID 0xf14
#ifndef __ASSEMBLY__

21
arch/riscv/lib/sifive_cache.c
View file

@ -7,7 +7,10 @@
#include <cpu_func.h>
#include <log.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#ifndef CONFIG_SPL_BUILD
void enable_caches(void)
{
struct udevice *dev;
@ -25,3 +28,21 @@ void enable_caches(void)
log_debug("ccache enable failed");
}
}
#else
static inline void probe_cache_device(struct driver *driver, struct udevice *dev)
{
for (uclass_find_first_device(UCLASS_CACHE, &dev);
dev;
uclass_find_next_device(&dev)) {
if (dev->driver == driver)
device_probe(dev);
}
}
void enable_caches(void)
{
struct udevice *dev = NULL;
probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
}
#endif /* !CONFIG_SPL_BUILD */

26
board/AndesTech/ae350/ae350.c
View file

@ -13,7 +13,9 @@
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include <netdev.h>
#endif
#include <asm/csr.h>
#include <asm/global_data.h>
#include <asm/sbi.h>
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
@ -27,6 +29,27 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initializations
*/
#if IS_ENABLED(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
long csr_marchid = 0;
const long mask_64 = 0x8000;
const long mask_cpu = 0xff;
char cpu_name[10] = {};
#if CONFIG_IS_ENABLED(RISCV_SMODE)
sbi_get_marchid(&csr_marchid);
#elif CONFIG_IS_ENABLED(RISCV_MMODE)
csr_marchid = csr_read(CSR_MARCHID);
#endif
if (mask_64 & csr_marchid)
snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid));
else
snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
return env_set("cpu", cpu_name);
}
#endif
#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
@ -102,7 +125,8 @@ void *board_fdt_blob_setup(int *err)
void spl_board_init()
{
/* enable v5l2 cache */
enable_caches();
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
enable_caches();
}
#endif

5
configs/ae350_rv32_defconfig
View file

@ -11,14 +11,15 @@ CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_ANDES_AE350=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv32_spl_defconfig
View file

@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv32_spl_xip_defconfig
View file

@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv32_xip_defconfig
View file

@ -12,14 +12,15 @@ CONFIG_TARGET_ANDES_AE350=y
CONFIG_XIP=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv64_defconfig
View file

@ -11,14 +11,15 @@ CONFIG_TARGET_ANDES_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv64_spl_defconfig
View file

@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv64_spl_xip_defconfig
View file

@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

5
configs/ae350_rv64_xip_defconfig
View file

@ -12,14 +12,15 @@ CONFIG_ARCH_RV64I=y
CONFIG_XIP=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PBSIZE=1050
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y

7
drivers/cache/Kconfig vendored
View file

@ -45,4 +45,11 @@ config SIFIVE_CCACHE
This driver is for SiFive Composable L2/L3 cache. It enables cache
ways of composable cache.
config SIFIVE_PL2
bool "SiFive private L2 cache"
select CACHE
help
This driver is for SiFive Private L2 cache. It configures registers
to enable the clock gating feature.
endmenu

1
drivers/cache/Makefile vendored
View file

@ -5,3 +5,4 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o

44
drivers/cache/cache-sifive-pl2.c vendored Normal file
View file

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 SiFive
*/
#include <cache.h>
#include <dm.h>
#include <malloc.h>
#include <asm/io.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#define SIFIVE_PL2CHICKENBIT_OFFSET 0x1000
#define SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK BIT(3)
static int sifive_pl2_probe(struct udevice *dev)
{
fdt_addr_t base;
u32 val;
base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
/* Enable regionClockDisable bit */
val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
(void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
return 0;
}
static const struct udevice_id sifive_pl2_ids[] = {
{ .compatible = "sifive,pl2cache0" },
{ .compatible = "sifive,pl2cache1" },
{}
};
U_BOOT_DRIVER(sifive_pl2) = {
.name = "sifive_pl2",
.id = UCLASS_CACHE,
.of_match = sifive_pl2_ids,
.probe = sifive_pl2_probe,
};